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{
    "id": 74454,
    "url": "https://patches.dpdk.org/api/patches/74454/",
    "web_url": "https://patches.dpdk.org/patch/74454/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595182154-36508-13-git-send-email-orika@mellanox.com>",
    "date": "2020-07-19T18:09:12",
    "name": "[v5,12/13] regex/mlx5: implement dequeue function",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "bb628520d62bf6cdae9deaab503735e75202689f",
    "submitter": {
        "id": 795,
        "url": "https://patches.dpdk.org/api/people/795/",
        "name": "Ori Kam",
        "email": "orika@mellanox.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/patch/74454/mbox/",
    "series": [
        {
            "id": 11154,
            "url": "https://patches.dpdk.org/api/series/11154/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11154",
            "date": "2020-07-19T18:09:00",
            "name": "add Mellanox RegEx PMD",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/11154/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74454/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74454/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH v5 12/13] regex/mlx5: implement dequeue function",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Ori Kam <orika@mellanox.com>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E017BA0540;\n\tSun, 19 Jul 2020 20:11:42 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1FEE91C1BA;\n\tSun, 19 Jul 2020 20:10:31 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id CC02B1C1D0\n for <dev@dpdk.org>; Sun, 19 Jul 2020 20:10:13 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 19 Jul 2020 21:10:10 +0300",
            "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06JI9ISP009919;\n Sun, 19 Jul 2020 21:10:10 +0300"
        ],
        "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com, Shahaf Shuler <shahafs@mellanox.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Sun, 19 Jul 2020 18:09:12 +0000",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "In-Reply-To": "<1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n hemant.agrawal@nxp.com, opher@mellanox.com, alexr@mellanox.com,\n dovrat@marvell.com, pkapoor@marvell.com, nipun.gupta@nxp.com,\n bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com,\n Yuval Avnery <yuvalav@mellanox.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595182154-36508-13-git-send-email-orika@mellanox.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "From: Yuval Avnery <yuvalav@mellanox.com>\n\nImplement dequeue function for the regex API.\n\nSigned-off-by: Yuval Avnery <yuvalav@mellanox.com>\nAcked-by: Ori Kam <orika@mellanox.com>\n---\n drivers/common/mlx5/mlx5_prm.h           |  10 +++\n drivers/regex/mlx5/mlx5_regex.c          |   1 +\n drivers/regex/mlx5/mlx5_regex.h          |   4 ++\n drivers/regex/mlx5/mlx5_regex_control.c  |   1 +\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 108 ++++++++++++++++++++++++++++++-\n 5 files changed, 123 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 6a3f22e..8fab962 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -441,6 +441,12 @@ struct mlx5_ifc_regexp_metadata_bits {\n \tuint8_t reserved[0x80];\n };\n \n+struct mlx5_ifc_regexp_match_tuple_bits {\n+\tuint8_t length[0x10];\n+\tuint8_t start_ptr[0x10];\n+\tuint8_t rule_id[0x20];\n+};\n+\n /* Adding direct verbs to data-path. */\n \n /* CQ sequence number mask. */\n@@ -637,6 +643,10 @@ struct mlx5_modification_cmd {\n \t\t\t\t  __mlx5_16_bit_off(typ, fld))); \\\n \t} while (0)\n \n+#define MLX5_GET_VOLATILE(typ, p, fld) \\\n+\t((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\\\n+\t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n+\t__mlx5_mask(typ, fld))\n #define MLX5_GET(typ, p, fld) \\\n \t((rte_be_to_cpu_32(*((__be32 *)(p) +\\\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 607ca4d..fd457bf 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -168,6 +168,7 @@\n \t}\n \tpriv->regexdev->dev_ops = &mlx5_regexdev_ops;\n \tpriv->regexdev->enqueue = mlx5_regexdev_enqueue;\n+\tpriv->regexdev->dequeue = mlx5_regexdev_dequeue;\n \tpriv->regexdev->device = (struct rte_device *)pci_dev;\n \tpriv->regexdev->data->dev_private = priv;\n \tpriv->regexdev->state = RTE_REGEXDEV_READY;\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex fb81cb8..217a1a4 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -34,6 +34,7 @@ struct mlx5_regex_cq {\n \tuint32_t dbr_umem; /* Door bell record umem id. */\n \tvolatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */\n \tstruct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */\n+\tsize_t ci;\n \tuint32_t *dbr;\n };\n \n@@ -105,4 +106,7 @@ int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,\n int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id);\n uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,\n \t\t       struct rte_regex_ops **ops, uint16_t nb_ops);\n+uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,\n+\t\t       struct rte_regex_ops **ops, uint16_t nb_ops);\n+\n #endif /* MLX5_REGEX_H */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex f144c69..faafb76 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -120,6 +120,7 @@\n \tcq->cqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf,\n \t\t\t\t\t\tsizeof(struct mlx5_cqe) *\n \t\t\t\t\t\tcq_size, 7);\n+\tcq->ci = 0;\n \tif (!cq->cqe_umem) {\n \t\tDRV_LOG(ERR, \"Can't register cqe mem.\");\n \t\trte_errno  = ENOMEM;\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex ff6386b..fc5a7fc 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -35,6 +35,7 @@\n #define MLX5_REGEX_WQE_METADATA_OFFSET 16\n #define MLX5_REGEX_WQE_GATHER_OFFSET 32\n #define MLX5_REGEX_WQE_SCATTER_OFFSET 48\n+#define MLX5_REGEX_METADATA_OFF 32\n \n #define MLX5_REGEX_WQE_METADATA_OFFSET 16\n #define MLX5_REGEX_WQE_GATHER_OFFSET 32\n@@ -159,7 +160,7 @@ struct mlx5_regex_job {\n \n static inline uint32_t\n job_id_get(uint32_t qid, size_t sq_size, size_t index) {\n-\treturn qid*sq_size + index % sq_size;\n+\treturn qid * sq_size + (index & (sq_size - 1));\n }\n \n uint16_t\n@@ -192,6 +193,111 @@ struct mlx5_regex_job {\n \treturn i;\n }\n \n+#define MLX5_REGEX_RESP_SZ 8\n+\n+static inline void\n+extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job)\n+{\n+\tsize_t j, offset;\n+\top->user_id = job->user_id;\n+\top->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata +\n+\t\t\t\t\t   MLX5_REGEX_METADATA_OFF,\n+\t\t\t\t\t   match_count);\n+\top->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata,\n+\t\t\t\t\t\t  job->metadata +\n+\t\t\t\t\t\t  MLX5_REGEX_METADATA_OFF,\n+\t\t\t\t\t\t  detected_match_count);\n+\tfor (j = 0; j < op->nb_matches; j++) {\n+\t\toffset = MLX5_REGEX_RESP_SZ * j;\n+\t\top->matches[j].rule_id =\n+\t\t\tMLX5_GET_VOLATILE(regexp_match_tuple,\n+\t\t\t\t\t  (job->output + offset), rule_id);\n+\t\top->matches[j].start_offset =\n+\t\t\tMLX5_GET_VOLATILE(regexp_match_tuple,\n+\t\t\t\t\t  (job->output +  offset), start_ptr);\n+\t\top->matches[j].len =\n+\t\t\tMLX5_GET_VOLATILE(regexp_match_tuple,\n+\t\t\t\t\t  (job->output +  offset), length);\n+\t}\n+}\n+\n+static inline volatile struct mlx5_cqe *\n+poll_one(struct mlx5_regex_cq *cq)\n+{\n+\tvolatile struct mlx5_cqe *cqe;\n+\tsize_t next_cqe_offset;\n+\n+\tnext_cqe_offset =  (cq->ci & (cq_size_get(cq) - 1));\n+\tcqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset);\n+\trte_cio_wmb();\n+\n+\tint ret = check_cqe(cqe, cq_size_get(cq), cq->ci);\n+\n+\tif (unlikely(ret == MLX5_CQE_STATUS_ERR)) {\n+\t\tDRV_LOG(ERR, \"Completion with error on qp 0x%x\",  0);\n+\t\treturn NULL;\n+\t}\n+\n+\tif (unlikely(ret != MLX5_CQE_STATUS_SW_OWN))\n+\t\treturn NULL;\n+\n+\treturn cqe;\n+}\n+\n+\n+/**\n+ * DPDK callback for dequeue.\n+ *\n+ * @param dev\n+ *   Pointer to the regex dev structure.\n+ * @param qp_id\n+ *   The queue to enqueue the traffic to.\n+ * @param ops\n+ *   List of regex ops to dequeue.\n+ * @param nb_ops\n+ *   Number of ops in ops parameter.\n+ *\n+ * @return\n+ *   Number of packets successfully dequeued (<= pkts_n).\n+ */\n+uint16_t\n+mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,\n+\t\t      struct rte_regex_ops **ops, uint16_t nb_ops)\n+{\n+\tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_regex_qp *queue = &priv->qps[qp_id];\n+\tstruct mlx5_regex_cq *cq = &queue->cq;\n+\tvolatile struct mlx5_cqe *cqe;\n+\tsize_t i = 0;\n+\n+\twhile ((cqe = poll_one(cq))) {\n+\t\tuint16_t wq_counter\n+\t\t\t= (rte_be_to_cpu_16(cqe->wqe_counter) + 1) &\n+\t\t\t  MLX5_REGEX_MAX_WQE_INDEX;\n+\t\tsize_t sqid = cqe->rsvd3[2];\n+\t\tstruct mlx5_regex_sq *sq = &queue->sqs[sqid];\n+\t\twhile (sq->ci != wq_counter) {\n+\t\t\tif (unlikely(i == nb_ops)) {\n+\t\t\t\t/* Return without updating cq->ci */\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t\tuint32_t job_id = job_id_get(sqid, sq_size_get(sq),\n+\t\t\t\t\t\t     sq->ci);\n+\t\t\textract_result(ops[i], &queue->jobs[job_id]);\n+\t\t\tsq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX;\n+\t\t\ti++;\n+\t\t}\n+\t\tcq->ci = (cq->ci + 1) & 0xffffff;\n+\t\trte_wmb();\n+\t\tcq->dbr[0] = rte_cpu_to_be_32(cq->ci);\n+\t\tqueue->free_sqs |= (1 << sqid);\n+\t}\n+\n+out:\n+\tqueue->ci += i;\n+\treturn i;\n+}\n+\n static void\n setup_sqs(struct mlx5_regex_qp *queue)\n {\n",
    "prefixes": [
        "v5",
        "12/13"
    ]
}