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{
    "id": 74450,
    "url": "https://patches.dpdk.org/api/patches/74450/",
    "web_url": "https://patches.dpdk.org/patch/74450/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595182154-36508-9-git-send-email-orika@mellanox.com>",
    "date": "2020-07-19T18:09:08",
    "name": "[v5,08/13] regex/mlx5: add completion queue creation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2e86f72f46bc6ac05f13d7cda9fdeb104e48c3b6",
    "submitter": {
        "id": 795,
        "url": "https://patches.dpdk.org/api/people/795/",
        "name": "Ori Kam",
        "email": "orika@mellanox.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/patch/74450/mbox/",
    "series": [
        {
            "id": 11154,
            "url": "https://patches.dpdk.org/api/series/11154/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11154",
            "date": "2020-07-19T18:09:00",
            "name": "add Mellanox RegEx PMD",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/11154/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74450/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74450/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH v5 08/13] regex/mlx5: add completion queue\n\tcreation",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Ori Kam <orika@mellanox.com>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4D6FAA0540;\n\tSun, 19 Jul 2020 20:11:03 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F30861C1BC;\n\tSun, 19 Jul 2020 20:10:10 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id BDB1A1C194\n for <dev@dpdk.org>; Sun, 19 Jul 2020 20:09:58 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 19 Jul 2020 21:09:55 +0300",
            "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06JI9ISL009919;\n Sun, 19 Jul 2020 21:09:55 +0300"
        ],
        "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com",
        "X-Mailer": "git-send-email 1.8.3.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Sun, 19 Jul 2020 18:09:08 +0000",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "In-Reply-To": "<1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com,\n alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com,\n nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595182154-36508-9-git-send-email-orika@mellanox.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "This commit adds the creation of CQ\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/regex/mlx5/Makefile             |   1 +\n drivers/regex/mlx5/meson.build          |   1 +\n drivers/regex/mlx5/mlx5_regex.c         |   1 +\n drivers/regex/mlx5/mlx5_regex.h         |   4 +-\n drivers/regex/mlx5/mlx5_regex_control.c | 195 ++++++++++++++++++++++++++++++++\n drivers/regex/mlx5/mlx5_rxp.c           |   1 +\n 6 files changed, 201 insertions(+), 2 deletions(-)\n create mode 100644 drivers/regex/mlx5/mlx5_regex_control.c",
    "diff": "diff --git a/drivers/regex/mlx5/Makefile b/drivers/regex/mlx5/Makefile\nindex 01853246..8918ebe 100644\n--- a/drivers/regex/mlx5/Makefile\n+++ b/drivers/regex/mlx5/Makefile\n@@ -10,6 +10,7 @@ LIB = librte_pmd_mlx5_regex.a\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_rxp.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_devx.c\n+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_control.c\n \n # Basic CFLAGS.\n CFLAGS += -O3\ndiff --git a/drivers/regex/mlx5/meson.build b/drivers/regex/mlx5/meson.build\nindex 9354145..4495fa7 100644\n--- a/drivers/regex/mlx5/meson.build\n+++ b/drivers/regex/mlx5/meson.build\n@@ -13,6 +13,7 @@ sources = files(\n \t'mlx5_regex.c',\n \t'mlx5_rxp.c',\n \t'mlx5_regex_devx.c',\n+\t'mlx5_regex_control.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 72da3e2..309fde8 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -27,6 +27,7 @@\n \t.dev_info_get = mlx5_regex_info_get,\n \t.dev_configure = mlx5_regex_configure,\n \t.dev_db_import = mlx5_regex_rules_db_import,\n+\t.dev_qp_setup = mlx5_regex_qp_setup,\n };\n \n static struct ibv_device *\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex a2d2c9e..21770ca 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -19,7 +19,7 @@ struct mlx5_regex_sq {\n \tstruct mlx5_devx_obj *obj; /* The SQ DevX object. */\n \tint64_t dbr_offset; /* Door bell record offset. */\n \tuint32_t dbr_umem; /* Door bell record umem id. */\n-\tvolatile struct mlx5_cqe *wqe; /* The SQ ring buffer. */\n+\tuint8_t *wqe; /* The SQ ring buffer. */\n \tstruct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */\n };\n \n@@ -62,10 +62,10 @@ struct mlx5_regex_priv {\n \tstruct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +\n \t\t\t\tMLX5_RXP_EM_COUNT];\n \tuint32_t nb_engines; /* Number of RegEx engines. */\n-\tstruct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */\n \tuint32_t eqn; /* EQ number. */\n \tstruct mlx5dv_devx_uar *uar; /* UAR object. */\n \tstruct ibv_pd *pd;\n+\tstruct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */\n };\n \n /* mlx5_rxp.c */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nnew file mode 100644\nindex 0000000..577965f\n--- /dev/null\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -0,0 +1,195 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include <errno.h>\n+\n+#include <rte_log.h>\n+#include <rte_errno.h>\n+#include <rte_malloc.h>\n+#include <rte_regexdev.h>\n+#include <rte_regexdev_core.h>\n+#include <rte_regexdev_driver.h>\n+\n+#include <mlx5_common.h>\n+#include <mlx5_glue.h>\n+#include <mlx5_devx_cmds.h>\n+#include <mlx5_prm.h>\n+#include <mlx5_common_os.h>\n+\n+#include \"mlx5_regex.h\"\n+#include \"mlx5_regex_utils.h\"\n+#include \"mlx5_rxp_csrs.h\"\n+#include \"mlx5_rxp.h\"\n+\n+#define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64)\n+\n+/**\n+ * Returns the number of qp obj to be created.\n+ *\n+ * @param nb_desc\n+ *   The number of descriptors for the queue.\n+ *\n+ * @return\n+ *   The number of obj to be created.\n+ */\n+static uint16_t\n+regex_ctrl_get_nb_obj(uint16_t nb_desc)\n+{\n+\treturn ((nb_desc / MLX5_REGEX_NUM_WQE_PER_PAGE) +\n+\t\t!!(nb_desc % MLX5_REGEX_NUM_WQE_PER_PAGE));\n+}\n+\n+/**\n+ * destroy CQ.\n+ *\n+ * @param priv\n+ *   Pointer to the priv object.\n+ * @param cp\n+ *   Pointer to the CQ to be destroyed.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+regex_ctrl_destroy_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)\n+{\n+\tif (cq->cqe_umem) {\n+\t\tmlx5_glue->devx_umem_dereg(cq->cqe_umem);\n+\t\tcq->cqe_umem = NULL;\n+\t}\n+\tif (cq->cqe) {\n+\t\trte_free((void *)(uintptr_t)cq->cqe);\n+\t\tcq->cqe = NULL;\n+\t}\n+\tif (cq->dbr_offset) {\n+\t\tmlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);\n+\t\tcq->dbr_offset = -1;\n+\t}\n+\tif (cq->obj) {\n+\t\tmlx5_devx_cmd_destroy(cq->obj);\n+\t\tcq->obj = NULL;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * create the CQ object.\n+ *\n+ * @param priv\n+ *   Pointer to the priv object.\n+ * @param cp\n+ *   Pointer to the CQ to be created.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)\n+{\n+\tstruct mlx5_devx_cq_attr attr = {\n+\t\t.q_umem_valid = 1,\n+\t\t.db_umem_valid = 1,\n+\t\t.eqn = priv->eqn,\n+\t};\n+\tstruct mlx5_devx_dbr_page *dbr_page = NULL;\n+\tvoid *buf = NULL;\n+\tsize_t pgsize = sysconf(_SC_PAGESIZE);\n+\tuint32_t cq_size = 1 << cq->log_nb_desc;\n+\tuint32_t i;\n+\n+\tcq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page);\n+\tif (cq->dbr_offset < 0) {\n+\t\tDRV_LOG(ERR, \"Can't allocate cq door bell record.\");\n+\t\trte_errno  = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tcq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);\n+\tbuf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096);\n+\tif (!buf) {\n+\t\tDRV_LOG(ERR, \"Can't allocate cqe buffer.\");\n+\t\trte_errno  = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tcq->cqe = buf;\n+\tfor (i = 0; i < cq_size; i++)\n+\t\tcq->cqe[i].op_own = 0xff;\n+\tcq->cqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf,\n+\t\t\t\t\t\tsizeof(struct mlx5_cqe) *\n+\t\t\t\t\t\tcq_size, 7);\n+\tif (!cq->cqe_umem) {\n+\t\tDRV_LOG(ERR, \"Can't register cqe mem.\");\n+\t\trte_errno  = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tattr.db_umem_offset = cq->dbr_offset;\n+\tattr.db_umem_id = cq->dbr_umem;\n+\tattr.q_umem_id = mlx5_os_get_umem_id(cq->cqe_umem);\n+\tattr.log_cq_size = cq->log_nb_desc;\n+\tattr.uar_page_id = priv->uar->page_id;\n+\tattr.log_page_size = rte_log2_u32(pgsize);\n+\tcq->obj = mlx5_devx_cmd_create_cq(priv->ctx, &attr);\n+\tif (!cq->obj) {\n+\t\tDRV_LOG(ERR, \"Can't create cq object.\");\n+\t\trte_errno  = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\treturn 0;\n+error:\n+\tif (cq->cqe_umem)\n+\t\tmlx5_glue->devx_umem_dereg(cq->cqe_umem);\n+\tif (buf)\n+\t\trte_free(buf);\n+\tif (cq->dbr_offset)\n+\t\tmlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Setup the qp.\n+ *\n+ * @param dev\n+ *   Pointer to RegEx dev structure.\n+ * @param qp_ind\n+ *   The queue index to setup.\n+ * @param cfg\n+ *   The queue requested configuration.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,\n+\t\t    const struct rte_regexdev_qp_conf *cfg)\n+{\n+\tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_regex_qp *qp;\n+\tint ret;\n+\n+\tqp = &priv->qps[qp_ind];\n+\tqp->flags = cfg->qp_conf_flags;\n+\tqp->cq.log_nb_desc = rte_log2_u32(cfg->nb_desc);\n+\tqp->nb_desc = 1 << qp->cq.log_nb_desc;\n+\tif (qp->flags & RTE_REGEX_QUEUE_PAIR_CFG_OOS_F)\n+\t\tqp->nb_obj = regex_ctrl_get_nb_obj(qp->nb_desc);\n+\telse\n+\t\tqp->nb_obj = 1;\n+\tqp->sqs = rte_malloc(NULL,\n+\t\t\t     qp->nb_obj * sizeof(struct mlx5_regex_sq), 64);\n+\tif (!qp->sqs) {\n+\t\tDRV_LOG(ERR, \"Can't allocate sq array memory.\");\n+\t\trte_errno  = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tret = regex_ctrl_create_cq(priv, &qp->cq);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Can't create cq.\");\n+\t\tgoto error;\n+\t}\n+\treturn 0;\n+\n+error:\n+\tregex_ctrl_destroy_cq(priv, &qp->cq);\n+\treturn -rte_errno;\n+\n+}\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 5dfba26..b8fab79 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -118,6 +118,7 @@\n \tinfo->max_queue_pairs = 1;\n \tinfo->regexdev_capa = RTE_REGEXDEV_SUPP_PCRE_GREEDY_F;\n \tinfo->rule_flags = 0;\n+\tinfo->max_queue_pairs = 10;\n \treturn 0;\n }\n \n",
    "prefixes": [
        "v5",
        "08/13"
    ]
}