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{
    "id": 74448,
    "url": "https://patches.dpdk.org/api/patches/74448/",
    "web_url": "https://patches.dpdk.org/patch/74448/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595182154-36508-7-git-send-email-orika@mellanox.com>",
    "date": "2020-07-19T18:09:06",
    "name": "[v5,06/13] regex/mlx5: add configure function",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6b0ed90b9f2b6d942909e813b7416130c146ca1b",
    "submitter": {
        "id": 795,
        "url": "https://patches.dpdk.org/api/people/795/",
        "name": "Ori Kam",
        "email": "orika@mellanox.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/patch/74448/mbox/",
    "series": [
        {
            "id": 11154,
            "url": "https://patches.dpdk.org/api/series/11154/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11154",
            "date": "2020-07-19T18:09:00",
            "name": "add Mellanox RegEx PMD",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/11154/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74448/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74448/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH v5 06/13] regex/mlx5: add configure function",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Ori Kam <orika@mellanox.com>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8DB0A0540;\n\tSun, 19 Jul 2020 20:10:30 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E73431C19A;\n\tSun, 19 Jul 2020 20:09:57 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 925B21C194\n for <dev@dpdk.org>; Sun, 19 Jul 2020 20:09:48 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 19 Jul 2020 21:09:47 +0300",
            "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06JI9ISJ009919;\n Sun, 19 Jul 2020 21:09:47 +0300"
        ],
        "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com",
        "X-Mailer": "git-send-email 1.8.3.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Sun, 19 Jul 2020 18:09:06 +0000",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "In-Reply-To": "<1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com,\n alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com,\n nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595182154-36508-7-git-send-email-orika@mellanox.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "This commit implements the configure function.\nThis function is responsible to configure the RegEx engine.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/regex/mlx5/mlx5_regex.c |   2 +\n drivers/regex/mlx5/mlx5_regex.h |  15 +++\n drivers/regex/mlx5/mlx5_rxp.c   | 235 +++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 251 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex f37c2df..f834ac0 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -25,6 +25,7 @@\n \n const struct rte_regexdev_ops mlx5_regexdev_ops = {\n \t.dev_info_get = mlx5_regex_info_get,\n+\t.dev_configure = mlx5_regex_configure,\n };\n \n static struct ibv_device *\n@@ -145,6 +146,7 @@\n \tpriv->regexdev->dev_ops = &mlx5_regexdev_ops;\n \tpriv->regexdev->device = (struct rte_device *)pci_dev;\n \tpriv->regexdev->data->dev_private = priv;\n+\tpriv->regexdev->state = RTE_REGEXDEV_READY;\n \treturn 0;\n \n error:\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 082d134..f17b4f8 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -7,16 +7,31 @@\n \n #include <rte_regexdev.h>\n \n+struct mlx5_regex_sq {\n+\tuint32_t nb_desc; /* Number of desc for this object. */\n+};\n+\n+struct mlx5_regex_qp {\n+\tuint32_t flags; /* QP user flags. */\n+\tuint32_t nb_desc; /* Total number of desc for this qp. */\n+\tstruct mlx5_regex_sq *sqs; /* Pointer to sq array. */\n+};\n+\n struct mlx5_regex_priv {\n \tTAILQ_ENTRY(mlx5_regex_priv) next;\n \tstruct ibv_context *ctx; /* Device context. */\n \tstruct rte_pci_device *pci_dev;\n \tstruct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */\n+\tuint16_t nb_queues; /* Number of queues. */\n+\tstruct mlx5_regex_qp *qps; /* Pointer to the qp array. */\n+\tuint16_t nb_max_matches; /* Max number of matches. */\n };\n \n /* mlx5_rxp.c */\n int mlx5_regex_info_get(struct rte_regexdev *dev,\n \t\t\tstruct rte_regexdev_info *info);\n+int mlx5_regex_configure(struct rte_regexdev *dev,\n+\t\t\t const struct rte_regexdev_config *cfg);\n \n /* mlx5_regex_devx.c */\n int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex a5a6f15..18e2338 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -2,13 +2,22 @@\n  * Copyright 2020 Mellanox Technologies, Ltd\n  */\n \n+#include <errno.h>\n+\n #include <rte_log.h>\n #include <rte_errno.h>\n+#include <rte_malloc.h>\n #include <rte_regexdev.h>\n #include <rte_regexdev_core.h>\n #include <rte_regexdev_driver.h>\n \n+#include <mlx5_glue.h>\n+#include <mlx5_devx_cmds.h>\n+#include <mlx5_prm.h>\n+\n #include \"mlx5_regex.h\"\n+#include \"mlx5_regex_utils.h\"\n+#include \"mlx5_rxp_csrs.h\"\n \n #define MLX5_REGEX_MAX_MATCHES 255\n #define MLX5_REGEX_MAX_PAYLOAD_SIZE UINT16_MAX\n@@ -17,7 +26,7 @@\n \n int\n mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,\n-\t\t  struct rte_regexdev_info *info)\n+\t\t    struct rte_regexdev_info *info)\n {\n \tinfo->max_matches = MLX5_REGEX_MAX_MATCHES;\n \tinfo->max_payload_size = MLX5_REGEX_MAX_PAYLOAD_SIZE;\n@@ -27,3 +36,227 @@\n \tinfo->rule_flags = 0;\n \treturn 0;\n }\n+\n+static int\n+rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,\n+\t\t       uint32_t address, uint32_t expected_value,\n+\t\t       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)\n+{\n+\tunsigned int i;\n+\tint ret;\n+\n+\tret = -EBUSY;\n+\tfor (i = 0; i < timeout_ms; i++) {\n+\t\tif (mlx5_devx_regex_register_read(ctx, id, address, value))\n+\t\t\treturn -1;\n+\n+\t\tif ((*value & expected_mask) == expected_value) {\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\trte_delay_us(1000);\n+\t}\n+\treturn ret;\n+}\n+\n+static int\n+rxp_start_engine(struct ibv_context *ctx, uint8_t id)\n+{\n+\tuint32_t ctrl;\n+\tint ret;\n+\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\tctrl |= MLX5_RXP_CSR_CTRL_GO;\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n+\treturn ret;\n+}\n+\n+static int\n+rxp_stop_engine(struct ibv_context *ctx, uint8_t id)\n+{\n+\tuint32_t ctrl;\n+\tint ret;\n+\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\tctrl &= ~MLX5_RXP_CSR_CTRL_GO;\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n+\treturn ret;\n+}\n+\n+static int\n+rxp_init_rtru(struct ibv_context *ctx, uint8_t id, uint32_t init_bits)\n+{\n+\tuint32_t ctrl_value;\n+\tuint32_t poll_value;\n+\tuint32_t expected_value;\n+\tuint32_t expected_mask;\n+\tint ret = 0;\n+\n+\t/* Read the rtru ctrl CSR */\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t\t    &ctrl_value);\n+\tif (ret)\n+\t\treturn -1;\n+\t/* Clear any previous init modes */\n+\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);\n+\tif (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {\n+\t\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);\n+\t\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t\t       ctrl_value);\n+\t}\n+\t/* Set the init_mode bits in the rtru ctrl CSR */\n+\tctrl_value |= init_bits;\n+\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t       ctrl_value);\n+\t/* Need to sleep for a short period after pulsing the rtru init bit.  */\n+\trte_delay_us(20000);\n+\t/* Poll the rtru status CSR until all the init done bits are set. */\n+\tDRV_LOG(DEBUG, \"waiting for RXP rule memory to complete init\");\n+\t/* Set the init bit in the rtru ctrl CSR. */\n+\tctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;\n+\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t       ctrl_value);\n+\t/* Clear the init bit in the rtru ctrl CSR */\n+\tctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;\n+\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t       ctrl_value);\n+\t/* Check that the following bits are set in the RTRU_CSR. */\n+\tif (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {\n+\t\t/* Must be incremental mode */\n+\t\texpected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |\n+\t\t\t\t MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;\n+\t} else {\n+\t\texpected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |\n+\t\t\t\t MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |\n+\t\t\t\t MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;\n+\t}\n+\texpected_mask = expected_value;\n+\tret = rxp_poll_csr_for_value(ctx, &poll_value,\n+\t\t\t\t     MLX5_RXP_RTRU_CSR_STATUS,\n+\t\t\t\t     expected_value, expected_mask,\n+\t\t\t\t     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);\n+\tif (ret)\n+\t\treturn ret;\n+\tDRV_LOG(DEBUG, \"rule Memory initialise: 0x%08X\", poll_value);\n+\t/* Clear the init bit in the rtru ctrl CSR */\n+\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);\n+\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n+\t\t\t\t       ctrl_value);\n+\treturn 0;\n+}\n+\n+static int\n+rxp_init(struct mlx5_regex_priv *priv, uint8_t id)\n+{\n+\tuint32_t ctrl;\n+\tuint32_t reg;\n+\tstruct ibv_context *ctx = priv->ctx;\n+\tint ret;\n+\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\tif (ctrl & MLX5_RXP_CSR_CTRL_INIT) {\n+\t\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n+\t\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,\n+\t\t\t\t\t\t     ctrl);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tctrl |= MLX5_RXP_CSR_CTRL_INIT;\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n+\trte_delay_us(20000);\n+\n+\tret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,\n+\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n+\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n+\t\t\t\t     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,\n+\t\t\t\t\t     ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\trxp_init_rtru(ctx, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);\n+\tret = rxp_init_rtru(ctx, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,\n+\t\t\t\t\t    &reg);\n+\tif (ret)\n+\t\treturn ret;\n+\tDRV_LOG(DEBUG, \"max matches: %d, DDOS threshold: %d\", reg >> 16,\n+\t\treg & 0xffff);\n+\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_MATCH,\n+\t\t\t\t\t     priv->nb_max_matches);\n+\tret |= mlx5_devx_regex_register_write(ctx, id,\n+\t\t\t\t\t      MLX5_RXP_CSR_MAX_LATENCY, 0);\n+\tret |= mlx5_devx_regex_register_write(ctx, id,\n+\t\t\t\t\t      MLX5_RXP_CSR_MAX_PRI_THREAD, 0);\n+\treturn ret;\n+}\n+\n+int\n+mlx5_regex_configure(struct rte_regexdev *dev,\n+\t\t     const struct rte_regexdev_config *cfg)\n+{\n+\tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n+\tint ret;\n+\tuint8_t id;\n+\n+\tpriv->nb_queues = cfg->nb_queue_pairs;\n+\tpriv->qps = rte_zmalloc(NULL, sizeof(struct mlx5_regex_qp) *\n+\t\t\t\tpriv->nb_queues, 0);\n+\tif (!priv->nb_queues) {\n+\t\tDRV_LOG(ERR, \"can't allocate qps memory\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->nb_max_matches = cfg->nb_max_matches;\n+\tfor (id = 0; id < 2; id++) {\n+\t\tret = rxp_stop_engine(priv->ctx, id);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"can't stop engine.\");\n+\t\t\trte_errno = ENODEV;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tret = rxp_init(priv, id);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"can't init engine.\");\n+\t\t\trte_errno = ENODEV;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tret = mlx5_devx_regex_register_write(priv->ctx, id,\n+\t\t\t\t\t\t     MLX5_RXP_CSR_MAX_MATCH,\n+\t\t\t\t\t\t     priv->nb_max_matches);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"can't update number of matches.\");\n+\t\t\trte_errno = ENODEV;\n+\t\t\tgoto configure_error;\n+\t\t}\n+\t\tret = rxp_start_engine(priv->ctx, id);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"can't start engine.\");\n+\t\t\trte_errno = ENODEV;\n+\t\t\tgoto configure_error;\n+\t\t}\n+\n+\t}\n+\treturn 0;\n+configure_error:\n+\tif (priv->qps)\n+\t\trte_free(priv->qps);\n+\treturn -rte_errno;\n+}\n",
    "prefixes": [
        "v5",
        "06/13"
    ]
}