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{
    "id": 74447,
    "url": "https://patches.dpdk.org/api/patches/74447/",
    "web_url": "https://patches.dpdk.org/patch/74447/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595182154-36508-6-git-send-email-orika@mellanox.com>",
    "date": "2020-07-19T18:09:05",
    "name": "[v5,05/13] regex/mlx5: add engine status check",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8d4a2b9a5188b0050bfa455c29ce1a108a60265e",
    "submitter": {
        "id": 795,
        "url": "https://patches.dpdk.org/api/people/795/",
        "name": "Ori Kam",
        "email": "orika@mellanox.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/patch/74447/mbox/",
    "series": [
        {
            "id": 11154,
            "url": "https://patches.dpdk.org/api/series/11154/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11154",
            "date": "2020-07-19T18:09:00",
            "name": "add Mellanox RegEx PMD",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/11154/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74447/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74447/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH v5 05/13] regex/mlx5: add engine status check",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Ori Kam <orika@mellanox.com>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A131A0540;\n\tSun, 19 Jul 2020 20:10:21 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A49FD1C124;\n\tSun, 19 Jul 2020 20:09:56 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 785301C193\n for <dev@dpdk.org>; Sun, 19 Jul 2020 20:09:48 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 19 Jul 2020 21:09:43 +0300",
            "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06JI9ISI009919;\n Sun, 19 Jul 2020 21:09:43 +0300"
        ],
        "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com, Shahaf Shuler <shahafs@mellanox.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Sun, 19 Jul 2020 18:09:05 +0000",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "In-Reply-To": "<1595182154-36508-1-git-send-email-orika@mellanox.com>",
        "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n hemant.agrawal@nxp.com, opher@mellanox.com, alexr@mellanox.com,\n dovrat@marvell.com, pkapoor@marvell.com, nipun.gupta@nxp.com,\n bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595182154-36508-6-git-send-email-orika@mellanox.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "This commit checks the engine status.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/common/mlx5/mlx5_prm.h       |  91 ++++++++++\n drivers/regex/mlx5/Makefile          |   1 +\n drivers/regex/mlx5/meson.build       |   1 +\n drivers/regex/mlx5/mlx5_regex.c      |  28 +++\n drivers/regex/mlx5/mlx5_regex.h      |   8 +\n drivers/regex/mlx5/mlx5_regex_devx.c |  61 +++++++\n drivers/regex/mlx5/mlx5_rxp_csrs.h   | 338 +++++++++++++++++++++++++++++++++++\n 7 files changed, 528 insertions(+)\n create mode 100644 drivers/regex/mlx5/mlx5_regex_devx.c\n create mode 100644 drivers/regex/mlx5/mlx5_rxp_csrs.h",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 364db81..a59acc7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -806,6 +806,10 @@ enum {\n \tMLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,\n \tMLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,\n \tMLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,\n+\tMLX5_CMD_SET_REGEX_PARAMS = 0xb04,\n+\tMLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,\n+\tMLX5_CMD_SET_REGEX_REGISTERS = 0xb06,\n+\tMLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,\n \tMLX5_CMD_OP_ACCESS_REGISTER_USER = 0xB0C,\n };\n \n@@ -2680,6 +2684,93 @@ struct mlx5_ifc_parse_graph_flex_out_bits {\n \tstruct mlx5_ifc_parse_graph_flex_bits capability;\n };\n \n+struct regexp_params_field_select_bits {\n+\tu8 reserved_at_0[0x1e];\n+\tu8 stop_engine[0x1];\n+\tu8 db_umem_id[0x1];\n+};\n+\n+struct mlx5_ifc_regexp_params_bits {\n+\tu8 reserved_at_0[0x1f];\n+\tu8 stop_engine[0x1];\n+\tu8 db_umem_id[0x20];\n+\tu8 db_umem_offset[0x40];\n+\tu8 reserved_at_80[0x100];\n+};\n+\n+struct mlx5_ifc_set_regexp_params_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x18];\n+\tu8 engine_id[0x8];\n+\tstruct regexp_params_field_select_bits field_select;\n+\tstruct mlx5_ifc_regexp_params_bits regexp_params;\n+};\n+\n+struct mlx5_ifc_set_regexp_params_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_18[0x40];\n+};\n+\n+struct mlx5_ifc_query_regexp_params_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x18];\n+\tu8 engine_id[0x8];\n+\tu8 reserved[0x20];\n+};\n+\n+struct mlx5_ifc_query_regexp_params_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved[0x40];\n+\tstruct mlx5_ifc_regexp_params_bits regexp_params;\n+};\n+\n+struct mlx5_ifc_set_regexp_register_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x18];\n+\tu8 engine_id[0x8];\n+\tu8 register_address[0x20];\n+\tu8 register_data[0x20];\n+\tu8 reserved[0x40];\n+};\n+\n+struct mlx5_ifc_set_regexp_register_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved[0x40];\n+};\n+\n+struct mlx5_ifc_query_regexp_register_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x18];\n+\tu8 engine_id[0x8];\n+\tu8 register_address[0x20];\n+};\n+\n+struct mlx5_ifc_query_regexp_register_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved[0x20];\n+\tu8 register_data[0x20];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/regex/mlx5/Makefile b/drivers/regex/mlx5/Makefile\nindex 8fe61f8..01853246 100644\n--- a/drivers/regex/mlx5/Makefile\n+++ b/drivers/regex/mlx5/Makefile\n@@ -9,6 +9,7 @@ LIB = librte_pmd_mlx5_regex.a\n # Sources.\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_rxp.c\n+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_devx.c\n \n # Basic CFLAGS.\n CFLAGS += -O3\ndiff --git a/drivers/regex/mlx5/meson.build b/drivers/regex/mlx5/meson.build\nindex bfb25e2..9354145 100644\n--- a/drivers/regex/mlx5/meson.build\n+++ b/drivers/regex/mlx5/meson.build\n@@ -12,6 +12,7 @@ deps += ['common_mlx5', 'bus_pci', 'bus_mlx5_pci', 'eal', 'regexdev']\n sources = files(\n \t'mlx5_regex.c',\n \t'mlx5_rxp.c',\n+\t'mlx5_regex_devx.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 1f4d967..f37c2df 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -19,6 +19,7 @@\n \n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n+#include \"mlx5_rxp_csrs.h\"\n \n int mlx5_regex_logtype;\n \n@@ -53,6 +54,28 @@\n \tmlx5_glue->free_device_list(ibv_list);\n \treturn ibv_match;\n }\n+static int\n+mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)\n+{\n+\tuint32_t fpga_ident = 0;\n+\tint err;\n+\tint i;\n+\n+\tfor (i = 0; i < num_engines; i++) {\n+\t\terr = mlx5_devx_regex_register_read(ctx, i,\n+\t\t\t\t\t\t    MLX5_RXP_CSR_IDENTIFIER,\n+\t\t\t\t\t\t    &fpga_ident);\n+\t\tfpga_ident = (fpga_ident & (0x0000FFFF));\n+\t\tif (err || fpga_ident != MLX5_RXP_IDENTIFIER) {\n+\t\t\tDRV_LOG(ERR, \"Failed setup RXP %d err %d database \"\n+\t\t\t\t\"memory 0x%x\", i, err, fpga_ident);\n+\t\t\tif (!err)\n+\t\t\t\terr = EINVAL;\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n \n static void\n mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused)\n@@ -99,6 +122,11 @@\n \t\trte_errno = ENOTSUP;\n \t\tgoto error;\n \t}\n+\tif (mlx5_regex_engines_status(ctx, 2)) {\n+\t\tDRV_LOG(ERR, \"RegEx engine error.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n \tpriv = rte_zmalloc(\"mlx5 regex device private\", sizeof(*priv),\n \t\t\t   RTE_CACHE_LINE_SIZE);\n \tif (!priv) {\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 9d0fc16..082d134 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -5,6 +5,8 @@\n #ifndef MLX5_REGEX_H\n #define MLX5_REGEX_H\n \n+#include <rte_regexdev.h>\n+\n struct mlx5_regex_priv {\n \tTAILQ_ENTRY(mlx5_regex_priv) next;\n \tstruct ibv_context *ctx; /* Device context. */\n@@ -16,4 +18,10 @@ struct mlx5_regex_priv {\n int mlx5_regex_info_get(struct rte_regexdev *dev,\n \t\t\tstruct rte_regexdev_info *info);\n \n+/* mlx5_regex_devx.c */\n+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,\n+\t\t\t\t   uint32_t addr, uint32_t data);\n+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,\n+\t\t\t\t  uint32_t addr, uint32_t *data);\n+\n #endif /* MLX5_REGEX_H */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c\nnew file mode 100644\nindex 0000000..1ffc008\n--- /dev/null\n+++ b/drivers/regex/mlx5/mlx5_regex_devx.c\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include <rte_errno.h>\n+#include <rte_log.h>\n+\n+#include <mlx5_glue.h>\n+#include <mlx5_devx_cmds.h>\n+#include <mlx5_prm.h>\n+\n+#include \"mlx5_regex.h\"\n+#include \"mlx5_regex_utils.h\"\n+\n+int\n+mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,\n+\t\t\t       uint32_t addr, uint32_t data)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(set_regexp_register_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(set_regexp_register_in)] = {0};\n+\tint ret;\n+\n+\tMLX5_SET(set_regexp_register_in, in, opcode,\n+\t\t MLX5_CMD_SET_REGEX_REGISTERS);\n+\tMLX5_SET(set_regexp_register_in, in, engine_id, engine_id);\n+\tMLX5_SET(set_regexp_register_in, in, register_address, addr);\n+\tMLX5_SET(set_regexp_register_in, in, register_data, data);\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n+\t\t\t\t\t  sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Set regexp register failed %d\", ret);\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,\n+\t\t\t      uint32_t addr, uint32_t *data)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(query_regexp_register_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(query_regexp_register_in)] = {0};\n+\tint ret;\n+\n+\tMLX5_SET(query_regexp_register_in, in, opcode,\n+\t\t MLX5_CMD_QUERY_REGEX_REGISTERS);\n+\tMLX5_SET(query_regexp_register_in, in, engine_id, engine_id);\n+\tMLX5_SET(query_regexp_register_in, in, register_address, addr);\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n+\t\t\t\t\t  sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Query regexp register failed %d\", ret);\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\t*data = MLX5_GET(query_regexp_register_out, out, register_data);\n+\treturn 0;\n+}\ndiff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h\nnew file mode 100644\nindex 0000000..acc927a\n--- /dev/null\n+++ b/drivers/regex/mlx5/mlx5_rxp_csrs.h\n@@ -0,0 +1,338 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+#ifndef _MLX5_RXP_CSRS_H_\n+#define _MLX5_RXP_CSRS_H_\n+\n+/*\n+ * Common to all RXP implementations\n+ */\n+#define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul\n+#define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul\n+#define MLX5_RXP_STATS_CSR_BASE_ADDRESS\t0x0200ul\n+#define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul\n+\n+#define MLX5_RXP_CSR_WIDTH 4\n+\n+/* This is the identifier we expect to see in the first RXP CSR */\n+#define MLX5_RXP_IDENTIFIER 0x5254\n+\n+/* Hyperion specific BAR0 offsets */\n+#define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul\n+#define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul\n+#define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul\n+#define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul\n+#define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul\n+#define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul\n+\n+/* Offset to the RXP common 4K CSR space */\n+#define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul\n+\n+/* FPGA CSRs */\n+\n+#define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \\\n+\t\t\t       MLX5_RXP_CSR_WIDTH * 0)\n+\n+/* PCIe CSRs */\n+#define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 1)\n+#define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 2)\n+#define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 3)\n+#define MLX5_RXP_PCIE_INIT_CTRL\t(MLX5_RXP_PCIE_BASE_ADDRESS + \\\n+\t\t\t\t MLX5_RXP_CSR_WIDTH * 4)\n+\n+/* IDMA CSRs */\n+#define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)\n+#define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)\n+#define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001\n+#define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002\n+#define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004\n+#define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008\n+#define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)\n+#define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF\n+#define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00\n+#define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)\n+#define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t     MLX5_RXP_CSR_WIDTH * 7)\n+#define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t     MLX5_RXP_CSR_WIDTH * 8)\n+#define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t     MLX5_RXP_CSR_WIDTH * 9)\n+#define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t    MLX5_RXP_CSR_WIDTH * 10)\n+#define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 16)\n+#define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 17)\n+#define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 18)\n+#define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 24)\n+#define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 25)\n+#define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 26)\n+\n+#define MLX5_RXP_IDMA_QCSR_BASE\t(MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t MLX5_RXP_CSR_WIDTH * 128)\n+#define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001\n+#define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002\n+#define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004\n+#define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008\n+#define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 192)\n+#define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 256)\n+#define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 320)\n+#define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 384)\n+#define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 385)\n+\n+/* EDMA CSRs */\n+#define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)\n+#define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)\n+#define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001\n+#define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002\n+#define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004\n+#define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008\n+#define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)\n+#define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF\n+#define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00\n+#define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)\n+#define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t     MLX5_RXP_CSR_WIDTH * 7)\n+#define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t     MLX5_RXP_CSR_WIDTH * 8)\n+#define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t    MLX5_RXP_CSR_WIDTH * 10)\n+#define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 16)\n+#define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 17)\n+#define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 18)\n+#define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 24)\n+#define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 25)\n+#define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t      MLX5_RXP_CSR_WIDTH * 26)\n+\n+#define MLX5_RXP_EDMA_QCSR_BASE\t(MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t\t MLX5_RXP_CSR_WIDTH * 128)\n+#define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001\n+#define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002\n+#define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004\n+#define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008\n+#define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 256)\n+#define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 320)\n+#define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 384)\n+#define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 385)\n+\n+/* Main CSRs */\n+#define MLX5_RXP_CSR_IDENTIFIER\t(MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t MLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t       MLX5_RXP_CSR_WIDTH * 1)\n+#define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 2)\n+#define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 3)\n+#define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 4)\n+#define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 5)\n+#define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 6)\n+#define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 7)\n+#define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 8)\n+#define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 9)\n+#define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 10)\n+#define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001\n+#define MLX5_RXP_CSR_STATUS_GOING 0x0008\n+#define MLX5_RXP_CSR_STATUS_IDLE 0x0040\n+#define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080\n+#define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100\n+#define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t    MLX5_RXP_CSR_WIDTH * 11)\n+#define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t    MLX5_RXP_CSR_WIDTH * 12)\n+#define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 13)\n+/* 14 + 15 reserved */\n+#define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 16)\n+#define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 17)\n+#define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 18)\n+#define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 19)\n+#define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 20)\n+#define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 21)\n+#define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 22)\n+#define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 23)\n+#define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)\n+#define MLX5_RXP_CSR_CTRL_INIT 0x0001\n+#define MLX5_RXP_CSR_CTRL_GO 0x0008\n+#define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 25)\n+#define MLX5_RXP_CSR_MAX_PREFIX\t(MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t MLX5_RXP_CSR_WIDTH * 26)\n+#define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 27)\n+#define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 28)\n+#define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 29)\n+#define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 30)\n+#define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \\\n+\t\t\t\t\t MLX5_RXP_CSR_WIDTH * 31)\n+\n+/* Runtime Rule Update CSRs */\n+/* 0 + 1 reserved */\n+#define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 2)\n+/* 3-9 reserved */\n+#define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 10)\n+#define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002\n+#define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010\n+#define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020\n+#define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040\n+#define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080\n+#define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 11)\n+/* 12-15 reserved */\n+#define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 16)\n+#define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 17)\n+#define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 18)\n+/* 19 + 20 reserved */\n+#define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 21)\n+#define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   MLX5_RXP_CSR_WIDTH * 22)\n+/* 23 reserved */\n+#define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 24)\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001\n+#define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002\n+#define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)\n+#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)\n+#define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\tMLX5_RXP_CSR_WIDTH * 25)\n+#define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 26)\n+#define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 27)\n+/* 28-31 reserved */\n+\n+/* Statistics CSRs */\n+#define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t\t    MLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 24)\n+#define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 25)\n+#define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t       MLX5_RXP_CSR_WIDTH * 28)\n+#define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t       MLX5_RXP_CSR_WIDTH * 30)\n+#define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \\\n+\t\t\t       MLX5_RXP_CSR_WIDTH * 31)\n+\n+/* Sysmon Stats CSRs */\n+#define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t    MLX5_RXP_CSR_WIDTH * 0)\n+#define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 1)\n+#define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 2)\n+#define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 20)\n+#define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 21)\n+#define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 22)\n+#define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 23)\n+#define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t  MLX5_RXP_CSR_WIDTH * 28)\n+#define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 29)\n+#define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t      MLX5_RXP_CSR_WIDTH * 30)\n+#define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \\\n+\t\t\t\t     MLX5_RXP_CSR_WIDTH * 31)\n+\n+/* In Service Programming CSRs */\n+\n+/* RXP-F1 and RXP-ZYNQ specific CSRs */\n+#define MLX5_RXP_MQ_CP_BASE (0x0500ul)\n+#define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \\\n+\t\t\t\t\t2 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n+\t\t\t\t     0 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n+\t\t\t\t     1 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n+\t\t\t\t     2 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \\\n+\t\t\t\t     3 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \\\n+\t\t\t\t\t 11 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n+\t\t\t\t       0 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n+\t\t\t\t       1 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n+\t\t\t\t       2 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \\\n+\t\t\t\t       3 * MLX5_RXP_CSR_WIDTH)\n+\n+/* Royalty tracker / licensing related CSRs */\n+#define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n+\t\t\t      0 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */\n+#define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n+\t\t\t\t   2 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXPL__TYPE_MASK 0xFF\n+#define MLX5_RXPL__TYPE_NONE 0\n+#define MLX5_RXPL__TYPE_MAXIM 1\n+#define MLX5_RXPL__TYPE_XILINX_DNA 2\n+#define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n+\t\t\t       10 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n+\t\t\t\t16 * MLX5_RXP_CSR_WIDTH)\n+#define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \\\n+\t\t\t      24 * MLX5_RXP_CSR_WIDTH)\n+\n+#endif /* _MLX5_RXP_CSRS_H_ */\n",
    "prefixes": [
        "v5",
        "05/13"
    ]
}