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GET /api/patches/7393/?format=api
https://patches.dpdk.org/api/patches/7393/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/a7507ca2b31bc01afa744cdcec253d17ed2556db.1443737626.git.viktorin@rehivetech.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<a7507ca2b31bc01afa744cdcec253d17ed2556db.1443737626.git.viktorin@rehivetech.com>", "list_archive_url": "https://inbox.dpdk.org/dev/a7507ca2b31bc01afa744cdcec253d17ed2556db.1443737626.git.viktorin@rehivetech.com", "date": "2015-10-03T08:58:10", "name": "[dpdk-dev,v1,04/12] eal/arm: cpu cycle operations for ARM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7948b950d352ac5caf90a033b05b8d0b9d7888e0", "submitter": { "id": 292, "url": "https://patches.dpdk.org/api/people/292/?format=api", "name": "Jan Viktorin", "email": "viktorin@rehivetech.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/a7507ca2b31bc01afa744cdcec253d17ed2556db.1443737626.git.viktorin@rehivetech.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7393/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7393/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 389B48E9B;\n\tSat, 3 Oct 2015 10:59:04 +0200 (CEST)", "from we2-f167.wedos.net (w-smtp-out-7.wedos.net [46.28.106.5])\n\tby dpdk.org (Postfix) with ESMTP id 2F5608E79\n\tfor <dev@dpdk.org>; Sat, 3 Oct 2015 10:58:52 +0200 (CEST)", "from ([147.229.13.147])\n\tby we2-f167.wedos.net (WEDOS Mail Server mail2) with ASMTP (SSL) id\n\tQWJ00050; Sat, 03 Oct 2015 10:58:50 +0200" ], "From": "Jan Viktorin <viktorin@rehivetech.com>", "To": "dev@dpdk.org", "Date": "Sat, 3 Oct 2015 10:58:10 +0200", "Message-Id": "<a7507ca2b31bc01afa744cdcec253d17ed2556db.1443737626.git.viktorin@rehivetech.com>", "X-Mailer": "git-send-email 2.6.0", "In-Reply-To": [ "<cover.1443737626.git.viktorin@rehivetech.com>", "<cover.1443737626.git.viktorin@rehivetech.com>" ], "References": [ "<cover.1443737626.git.viktorin@rehivetech.com>", "<cover.1443737626.git.viktorin@rehivetech.com>" ], "Cc": "Vlastimil Kosar <kosar@rehivetech.com>,\n\tJan Viktorin <viktorin@rehivetech.com>", "Subject": "[dpdk-dev] [PATCH v1 04/12] eal/arm: cpu cycle operations for ARM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vlastimil Kosar <kosar@rehivetech.com>\n\nARM architecture doesn't have a suitable source of CPU cycles. This\npatch uses clock_gettime instead. The implementation should be improved\nin the future.\n\nSigned-off-by: Vlastimil Kosar <kosar@rehivetech.com>\nSigned-off-by: Jan Viktorin <viktorin@rehivetech.com>\n---\n .../common/include/arch/arm/rte_cycles.h | 85 ++++++++++++++++++++++\n 1 file changed, 85 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles.h b/lib/librte_eal/common/include/arch/arm/rte_cycles.h\nnew file mode 100644\nindex 0000000..ff66ae2\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles.h\n@@ -0,0 +1,85 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of RehiveTech nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CYCLES_ARM_H_\n+#define _RTE_CYCLES_ARM_H_\n+\n+/* ARM v7 does not have suitable source of clock signals. The only clock counter\n+ available in the core is 32 bit wide. Therefore it is unsuitable as the\n+ counter overlaps every few seconds and probably is not accessible by\n+ userspace programs. Therefore we use clock_gettime(CLOCK_MONOTONIC_RAW) to\n+ simulate counter running at 1GHz.\n+*/\n+\n+#include <time.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\tstruct timespec val;\n+\tuint64_t v;\n+\n+\twhile (clock_gettime(CLOCK_MONOTONIC_RAW, &val) != 0)\n+\t\t/* no body */;\n+\n+\tv = (uint64_t) val.tv_sec * 1000000000LL;\n+\tv += (uint64_t) val.tv_nsec;\n+\treturn v;\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\trte_mb();\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CYCLES_ARM_H_ */\n", "prefixes": [ "dpdk-dev", "v1", "04/12" ] }{ "id": 7393, "url": "