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GET /api/patches/7387/?format=api
{ "id": 7387, "url": "https://patches.dpdk.org/api/patches/7387/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/64691a080e885cb89558f0a7202b05a126a39a9e.1443737626.git.viktorin@rehivetech.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<64691a080e885cb89558f0a7202b05a126a39a9e.1443737626.git.viktorin@rehivetech.com>", "list_archive_url": "https://inbox.dpdk.org/dev/64691a080e885cb89558f0a7202b05a126a39a9e.1443737626.git.viktorin@rehivetech.com", "date": "2015-10-03T08:58:08", "name": "[dpdk-dev,v1,02/12] eal/arm: atomic operations for ARM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a7e7d660721472ca0cac890f69cf1fcd73f74402", "submitter": { "id": 292, "url": "https://patches.dpdk.org/api/people/292/?format=api", "name": "Jan Viktorin", "email": "viktorin@rehivetech.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/64691a080e885cb89558f0a7202b05a126a39a9e.1443737626.git.viktorin@rehivetech.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7387/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7387/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1BA9E8E80;\n\tSat, 3 Oct 2015 10:58:58 +0200 (CEST)", "from we2-f167.wedos.net (w-smtp-out-7.wedos.net [46.28.106.5])\n\tby dpdk.org (Postfix) with ESMTP id 1CA548E65\n\tfor <dev@dpdk.org>; Sat, 3 Oct 2015 10:58:52 +0200 (CEST)", "from ([147.229.13.147])\n\tby we2-f167.wedos.net (WEDOS Mail Server mail2) with ASMTP (SSL) id\n\tQWJ00050; Sat, 03 Oct 2015 10:58:50 +0200" ], "From": "Jan Viktorin <viktorin@rehivetech.com>", "To": "dev@dpdk.org", "Date": "Sat, 3 Oct 2015 10:58:08 +0200", "Message-Id": "<64691a080e885cb89558f0a7202b05a126a39a9e.1443737626.git.viktorin@rehivetech.com>", "X-Mailer": "git-send-email 2.6.0", "In-Reply-To": [ "<cover.1443737626.git.viktorin@rehivetech.com>", "<cover.1443737626.git.viktorin@rehivetech.com>" ], "References": [ "<cover.1443737626.git.viktorin@rehivetech.com>", "<cover.1443737626.git.viktorin@rehivetech.com>" ], "Cc": "Vlastimil Kosar <kosar@rehivetech.com>,\n\tJan Viktorin <viktorin@rehivetech.com>", "Subject": "[dpdk-dev] [PATCH v1 02/12] eal/arm: atomic operations for ARM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vlastimil Kosar <kosar@rehivetech.com>\n\nThis patch adds architecture specific atomic operation file\nfor ARM architecture. It utilizes compiler intrinsics only.\n\nSigned-off-by: Vlastimil Kosar <kosar@rehivetech.com>\nSigned-off-by: Jan Viktorin <viktorin@rehivetech.com>\n---\n .../common/include/arch/arm/rte_atomic.h | 257 +++++++++++++++++++++\n 1 file changed, 257 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\nnew file mode 100644\nindex 0000000..aac5b0a\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\n@@ -0,0 +1,257 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of RehiveTech nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_ATOMIC_ARM_H_\n+#define _RTE_ATOMIC_ARM_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ */\n+#define\trte_mb() __sync_synchronize()\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ */\n+#define\trte_wmb() __sync_synchronize()\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ */\n+#define\trte_rmb() __sync_synchronize()\n+\n+/*------------------------- 16 bit atomic operations -------------------------*/\n+\n+// FIXME: nechapu: We use intrinsics even if RTE_FORCE_INTRINSICS is not set.\n+#ifndef RTE_FORCE_INTRINSICS\n+static inline int\n+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n+{\n+\treturn __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,\n+\t\t__ATOMIC_ACQUIRE) ? 1 : 0;\n+}\n+\n+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n+{\n+\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void\n+rte_atomic16_inc(rte_atomic16_t *v)\n+{\n+\t__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic16_dec(rte_atomic16_t *v)\n+{\n+\t__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+/*------------------------- 32 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n+{\n+\treturn __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,\n+\t\t__ATOMIC_ACQUIRE) ? 1 : 0;\n+}\n+\n+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n+{\n+\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void\n+rte_atomic32_inc(rte_atomic32_t *v)\n+{\n+\t__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic32_dec(rte_atomic32_t *v)\n+{\n+\t__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+/*------------------------- 64 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n+{\n+\treturn __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,\n+\t\t__ATOMIC_ACQUIRE) ? 1 : 0;\n+}\n+\n+static inline void\n+rte_atomic64_init(rte_atomic64_t *v)\n+{\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t tmp, 0);\n+\t}\n+}\n+\n+static inline int64_t\n+rte_atomic64_read(rte_atomic64_t *v)\n+{\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\t/* replace the value by itself */\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *) &v->cnt,\n+\t\t tmp, tmp);\n+\t}\n+\treturn tmp;\n+}\n+\n+static inline void\n+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n+{\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t tmp, new_value);\n+\t}\n+}\n+\n+static inline void\n+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n+{\n+\t__atomic_fetch_add(&v->cnt, inc, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n+{\n+\t__atomic_fetch_sub(&v->cnt, dec, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic64_inc(rte_atomic64_t *v)\n+{\n+\t__atomic_fetch_add(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline void\n+rte_atomic64_dec(rte_atomic64_t *v)\n+{\n+\t__atomic_fetch_sub(&v->cnt, 1, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int64_t\n+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n+{\n+\treturn __atomic_add_fetch(&v->cnt, inc, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int64_t\n+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n+{\n+\treturn __atomic_sub_fetch(&v->cnt, dec, __ATOMIC_ACQUIRE);\n+}\n+\n+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n+{\n+\treturn (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n+{\n+\treturn (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n+}\n+\n+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n+}\n+\n+/**\n+ * Atomically set a 64-bit counter to 0.\n+ *\n+ * @param v\n+ * A pointer to the atomic counter.\n+ */\n+static inline void rte_atomic64_clear(rte_atomic64_t *v)\n+{\n+\trte_atomic64_set(v, 0);\n+}\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_ARM_H_ */\n", "prefixes": [ "dpdk-dev", "v1", "02/12" ] }