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GET /api/patches/73622/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 73622,
    "url": "https://patches.dpdk.org/api/patches/73622/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200709164533.13150-1-tianfei.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200709164533.13150-1-tianfei.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200709164533.13150-1-tianfei.zhang@intel.com",
    "date": "2020-07-09T16:45:33",
    "name": "[v2,2/2] raw/ifpga/base: fix NIOS SPI initial",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "9003b798ed00ffb437887c7c57f162240fb54d75",
    "submitter": {
        "id": 987,
        "url": "https://patches.dpdk.org/api/people/987/?format=api",
        "name": "Zhang, Tianfei",
        "email": "tianfei.zhang@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200709164533.13150-1-tianfei.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 10919,
            "url": "https://patches.dpdk.org/api/series/10919/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10919",
            "date": "2020-07-09T16:45:20",
            "name": "[v2,1/2] raw/ifpga/base: fix spi transaction issue",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/10919/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73622/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/73622/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5455AA0526;\n\tThu,  9 Jul 2020 10:56:39 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 293FC1E494;\n\tThu,  9 Jul 2020 10:56:39 +0200 (CEST)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by dpdk.org (Postfix) with ESMTP id A56161DFEF;\n Thu,  9 Jul 2020 10:56:37 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jul 2020 01:56:36 -0700",
            "from figo-optiplex-9020.sh.intel.com ([10.238.169.50])\n by orsmga008.jf.intel.com with ESMTP; 09 Jul 2020 01:56:35 -0700"
        ],
        "IronPort-SDR": [
            "\n 2IUHhbZRCnGK6US+Smwkt7Lc8/SEvmwzmd2XxR06g8bZZW5Uyy/60cDiFzanC7oyRybbuwD20Z\n Nx8W2ebOdamg==",
            "\n 9/dO8XQILsKK8DSWDG7gDlNktt+x55g6JdlFXpdH7MhEAxIYiVnQ0n30U4EdE13MNfcfGLiFn3\n 1hjMzs0o404w=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9676\"; a=\"147954723\"",
            "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"147954723\"",
            "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"314898816\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Tianfei zhang <tianfei.zhang@intel.com>",
        "To": "dev@dpdk.org,\n\trosen.xu@intel.com",
        "Cc": "Tianfei Zhang <tianfei.zhang@intel.com>,\n\tstable@dpdk.org",
        "Date": "Fri, 10 Jul 2020 00:45:33 +0800",
        "Message-Id": "<20200709164533.13150-1-tianfei.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "Subject": "[dpdk-dev] [PATCH v2 2/2] raw/ifpga/base: fix NIOS SPI initial",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Tianfei Zhang <tianfei.zhang@intel.com>\n\nAdd fecmode setting on NIOS SPI primary initialization.\nthis SPI is shared by NIOS core inside FPGA, NIOS will\nuse this SPI primary to do some one time initialization\nafter power up, and then release the control to DPDK.\n\nFix the timeout initialization for polling the\nNIOS_INIT_DONE.\n\nFixes: bc44402f (\"raw/ifpga/base: configure FEC mode\")\nCc: stable@dpdk.org\n\nSigned-off-by: Tianfei Zhang <tianfei.zhang@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++-------\n drivers/raw/ifpga/base/opae_spi.h  |  1 +\n 2 files changed, 21 insertions(+), 7 deletions(-)",
    "diff": "diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c\nindex c31a94cf8..9057087b5 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme.c\n@@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = {\n static int nios_spi_wait_init_done(struct altera_spi_device *dev)\n {\n \tu32 val = 0;\n-\tunsigned long timeout = msecs_to_timer_cycles(10000);\n+\tunsigned long timeout = rte_get_timer_cycles() +\n+\t\t\tmsecs_to_timer_cycles(10000);\n \tunsigned long ticks;\n \tint major_version;\n+\tint fecmode = FEC_MODE_NO;\n \n \tif (spi_reg_read(dev, NIOS_VERSION, &val))\n \t\treturn -EIO;\n \n-\tmajor_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &\n-\t\tNIOS_VERSION_MAJOR;\n-\tdev_debug(dev, \"A10 NIOS FW version %d\\n\", major_version);\n+\tmajor_version =\n+\t\t(val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;\n+\tdev_info(dev, \"A10 NIOS FW version %d\\n\", major_version);\n \n \tif (major_version >= 3) {\n \t\t/* read NIOS_INIT to check if PKVL INIT done or not */\n \t\tif (spi_reg_read(dev, NIOS_INIT, &val))\n \t\t\treturn -EIO;\n \n+\t\tdev_debug(dev, \"read NIOS_INIT: 0x%x\\n\", val);\n+\n \t\t/* check if PKVLs are initialized already */\n \t\tif (val & NIOS_INIT_DONE || val & NIOS_INIT_START)\n \t\t\tgoto nios_init_done;\n \n \t\t/* start to config the default FEC mode */\n-\t\tval = NIOS_INIT_START;\n+\t\tval = fecmode | NIOS_INIT_START;\n \n \t\tif (spi_reg_write(dev, NIOS_INIT, val))\n \t\t\treturn -EIO;\n@@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev)\n \tdo {\n \t\tif (spi_reg_read(dev, NIOS_INIT, &val))\n \t\t\treturn -EIO;\n-\t\tif (val)\n+\t\tif (val & NIOS_INIT_DONE)\n \t\t\tbreak;\n \n \t\tticks = rte_get_timer_cycles();\n \t\tif (time_after(ticks, timeout))\n \t\t\treturn -ETIMEDOUT;\n \t\tmsleep(100);\n-\t} while (!val);\n+\t} while (1);\n+\n+\t/* get the fecmode */\n+\tif (spi_reg_read(dev, NIOS_INIT, &val))\n+\t\treturn -EIO;\n+\tdev_debug(dev, \"read NIOS_INIT: 0x%x\\n\", val);\n+\tfecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;\n+\tdev_info(dev, \"fecmode: 0x%x, %s\\n\", fecmode,\n+\t\t\t(fecmode == FEC_MODE_KR) ? \"kr\" :\n+\t\t\t((fecmode == FEC_MODE_RS) ? \"rs\" : \"no\"));\n \n \treturn 0;\n }\ndiff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h\nindex d20a4c3ed..73a227673 100644\n--- a/drivers/raw/ifpga/base/opae_spi.h\n+++ b/drivers/raw/ifpga/base/opae_spi.h\n@@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);\n \n #define NIOS_INIT\t\t0x1000\n #define REQ_FEC_MODE\t\tGENMASK(23, 8)\n+#define REQ_FEC_MODE_SHIFT      8\n #define FEC_MODE_NO\t\t0x0\n #define FEC_MODE_KR\t\t0x5555\n #define FEC_MODE_RS\t\t0xaaaa\n",
    "prefixes": [
        "v2",
        "2/2"
    ]
}