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[
    {
        "id": 115600,
        "web_url": "https://patches.dpdk.org/comment/115600/",
        "msgid": "<BYAPR11MB3477E5A303C29236B15695AFE3640@BYAPR11MB3477.namprd11.prod.outlook.com>",
        "date": "2020-07-09T08:59:21",
        "subject": "Re: [dpdk-dev] [PATCH v1 2/2] raw/ifpga/base: fix NIOS SPI initial",
        "submitter": {
            "id": 987,
            "url": "https://patches.dpdk.org/api/people/987/",
            "name": "Tianfei zhang",
            "email": "tianfei.zhang@intel.com"
        },
        "content": "The message include \"master\", it suggested that replace by \" primary \", I will send the V2.\n\n-----Original Message-----\nFrom: Zhang, Tianfei <tianfei.zhang@intel.com> \nSent: Friday, July 10, 2020 12:36 AM\nTo: dev@dpdk.org; Xu, Rosen <rosen.xu@intel.com>\nCc: Zhang, Tianfei <tianfei.zhang@intel.com>; stable@dpdk.org\nSubject: [PATCH v1 2/2] raw/ifpga/base: fix NIOS SPI initial\n\nFrom: Tianfei Zhang <tianfei.zhang@intel.com>\n\nAdd fecmode setting on NIOS SPI master initialization.\nthis SPI is shared by NIOS core inside FPGA, NIOS will use this SPI master to do some one time initialization after power up, and then release the control to DPDK.\n\nFix the timeout initialization for polling the NIOS_INIT_DONE.\n\nFixes: bc44402f (\"raw/ifpga/base: configure FEC mode\")\nCc: stable@dpdk.org\n\nSigned-off-by: Tianfei Zhang <tianfei.zhang@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++-------  drivers/raw/ifpga/base/opae_spi.h  |  1 +\n 2 files changed, 21 insertions(+), 7 deletions(-)\n\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c\nindex c31a94cf8..9057087b5 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme.c\n@@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = {  static int nios_spi_wait_init_done(struct altera_spi_device *dev)  {\n \tu32 val = 0;\n-\tunsigned long timeout = msecs_to_timer_cycles(10000);\n+\tunsigned long timeout = rte_get_timer_cycles() +\n+\t\t\tmsecs_to_timer_cycles(10000);\n \tunsigned long ticks;\n \tint major_version;\n+\tint fecmode = FEC_MODE_NO;\n \n \tif (spi_reg_read(dev, NIOS_VERSION, &val))\n \t\treturn -EIO;\n \n-\tmajor_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &\n-\t\tNIOS_VERSION_MAJOR;\n-\tdev_debug(dev, \"A10 NIOS FW version %d\\n\", major_version);\n+\tmajor_version =\n+\t\t(val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;\n+\tdev_info(dev, \"A10 NIOS FW version %d\\n\", major_version);\n \n \tif (major_version >= 3) {\n \t\t/* read NIOS_INIT to check if PKVL INIT done or not */\n \t\tif (spi_reg_read(dev, NIOS_INIT, &val))\n \t\t\treturn -EIO;\n \n+\t\tdev_debug(dev, \"read NIOS_INIT: 0x%x\\n\", val);\n+\n \t\t/* check if PKVLs are initialized already */\n \t\tif (val & NIOS_INIT_DONE || val & NIOS_INIT_START)\n \t\t\tgoto nios_init_done;\n \n \t\t/* start to config the default FEC mode */\n-\t\tval = NIOS_INIT_START;\n+\t\tval = fecmode | NIOS_INIT_START;\n \n \t\tif (spi_reg_write(dev, NIOS_INIT, val))\n \t\t\treturn -EIO;\n@@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev)\n \tdo {\n \t\tif (spi_reg_read(dev, NIOS_INIT, &val))\n \t\t\treturn -EIO;\n-\t\tif (val)\n+\t\tif (val & NIOS_INIT_DONE)\n \t\t\tbreak;\n \n \t\tticks = rte_get_timer_cycles();\n \t\tif (time_after(ticks, timeout))\n \t\t\treturn -ETIMEDOUT;\n \t\tmsleep(100);\n-\t} while (!val);\n+\t} while (1);\n+\n+\t/* get the fecmode */\n+\tif (spi_reg_read(dev, NIOS_INIT, &val))\n+\t\treturn -EIO;\n+\tdev_debug(dev, \"read NIOS_INIT: 0x%x\\n\", val);\n+\tfecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;\n+\tdev_info(dev, \"fecmode: 0x%x, %s\\n\", fecmode,\n+\t\t\t(fecmode == FEC_MODE_KR) ? \"kr\" :\n+\t\t\t((fecmode == FEC_MODE_RS) ? \"rs\" : \"no\"));\n \n \treturn 0;\n }\ndiff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h\nindex d20a4c3ed..73a227673 100644\n--- a/drivers/raw/ifpga/base/opae_spi.h\n+++ b/drivers/raw/ifpga/base/opae_spi.h\n@@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);\n \n #define NIOS_INIT\t\t0x1000\n #define REQ_FEC_MODE\t\tGENMASK(23, 8)\n+#define REQ_FEC_MODE_SHIFT      8\n #define FEC_MODE_NO\t\t0x0\n #define FEC_MODE_KR\t\t0x5555\n #define FEC_MODE_RS\t\t0xaaaa\n--\n2.17.1",
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            "Thread-Topic": "[PATCH v1 2/2] raw/ifpga/base: fix NIOS SPI initial",
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            "Subject": "Re: [dpdk-dev] [PATCH v1 2/2] raw/ifpga/base: fix NIOS SPI initial",
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            "Date": "Thu, 9 Jul 2020 08:59:21 +0000",
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            "From": "\"Zhang, Tianfei\" <tianfei.zhang@intel.com>",
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