get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/73602/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 73602,
    "url": "https://patches.dpdk.org/api/patches/73602/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200709080046.65879-6-guinanx.sun@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200709080046.65879-6-guinanx.sun@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200709080046.65879-6-guinanx.sun@intel.com",
    "date": "2020-07-09T08:00:32",
    "name": "[v3,05/19] net/ixgbe/base: added register definitions for NVM update",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "0138714e35ec02b4e78741e6f4da96dab7afa6d4",
    "submitter": {
        "id": 1476,
        "url": "https://patches.dpdk.org/api/people/1476/?format=api",
        "name": "Guinan Sun",
        "email": "guinanx.sun@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200709080046.65879-6-guinanx.sun@intel.com/mbox/",
    "series": [
        {
            "id": 10915,
            "url": "https://patches.dpdk.org/api/series/10915/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10915",
            "date": "2020-07-09T08:00:27",
            "name": "update ixgbe base code",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/10915/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73602/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73602/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3B93CA0526;\n\tThu,  9 Jul 2020 10:14:38 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A23181DD8F;\n\tThu,  9 Jul 2020 10:14:05 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 348DF1DD43\n for <dev@dpdk.org>; Thu,  9 Jul 2020 10:13:59 +0200 (CEST)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jul 2020 01:13:58 -0700",
            "from intel.sh.intel.com ([10.239.255.18])\n by orsmga002.jf.intel.com with ESMTP; 09 Jul 2020 01:13:55 -0700"
        ],
        "IronPort-SDR": [
            "\n 7T+zrCuc9mddYdVzl+X5Mkp3Wru6hthF1e+ssmwbzcFofqZlt/BmRAwpV1pnpDI3NnhonUQ9Lm\n xeFNndrSLCjw==",
            "\n dDwFD76WrhIh5LnlD8a9PXNZp2vLtDhFByYY0K8pyyOGjEaQV7IH5n12GqpIRMievpVPAUghMS\n mdR8Ot4FMOCQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9676\"; a=\"212869344\"",
            "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"212869344\"",
            "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"297989057\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Guinan Sun <guinanx.sun@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jeff Guo <jia.guo@intel.com>, Zhao1 Wei <wei.zhao1@intel.com>,\n Guinan Sun <guinanx.sun@intel.com>,\n Piotr Skajewski <piotrx.skajewski@intel.com>",
        "Date": "Thu,  9 Jul 2020 08:00:32 +0000",
        "Message-Id": "<20200709080046.65879-6-guinanx.sun@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200709080046.65879-1-guinanx.sun@intel.com>",
        "References": "<20200702031329.4495-1-guinanx.sun@intel.com>\n <20200709080046.65879-1-guinanx.sun@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 05/19] net/ixgbe/base: added register\n\tdefinitions for NVM update",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Added additional register for X550 and above device family.\n\nSigned-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\nReviewed-by: Wei Zhao <wei.zhao1@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_type.h | 2 ++\n 1 file changed, 2 insertions(+)",
    "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex bc927a34e..51cdff39d 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -1082,8 +1082,10 @@ struct ixgbe_dmac_config {\n #define IXGBE_HSMC0R\t\t0x15F04\n #define IXGBE_HSMC1R\t\t0x15F08\n #define IXGBE_SWSR\t\t0x15F10\n+#define IXGBE_FWRESETCNT\t0x15F40\n #define IXGBE_HFDR\t\t0x15FE8\n #define IXGBE_FLEX_MNG\t\t0x15800 /* 0x15800 - 0x15EFC */\n+#define IXGBE_FLEX_MNG_PTR(_i)\t(IXGBE_FLEX_MNG + ((_i) * 4))\n \n #define IXGBE_HICR_EN\t\t0x01  /* Enable bit - RO */\n /* Driver sets this bit when done to put command in RAM */\n",
    "prefixes": [
        "v3",
        "05/19"
    ]
}