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{
    "id": 73588,
    "url": "https://patches.dpdk.org/api/patches/73588/",
    "web_url": "https://patches.dpdk.org/patch/73588/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200709073452.948894-7-parav@mellanox.com>",
    "date": "2020-07-09T07:34:49",
    "name": "[v5,6/9] bus/mlx5_pci: add mlx5 PCI bus",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "60261fb290106a42a6a381dba0390657fc53bbc7",
    "submitter": {
        "id": 1780,
        "url": "https://patches.dpdk.org/api/people/1780/",
        "name": "Parav Pandit",
        "email": "parav@mellanox.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@mellanox.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73588/mbox/",
    "series": [
        {
            "id": 10912,
            "url": "https://patches.dpdk.org/api/series/10912/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10912",
            "date": "2020-07-09T07:34:43",
            "name": "Improve mlx5 PMD driver framework for multiple classes",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/10912/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73588/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73588/checks/",
    "tags": {},
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        "References": "<20200610171728.89-2-parav@mellanox.com>\n <20200709073452.948894-1-parav@mellanox.com>",
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        ],
        "Subject": "[dpdk-dev] [PATCH v5 6/9] bus/mlx5_pci: add mlx5 PCI bus",
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        "Cc": "rasland@mellanox.com, orika@mellanox.com, matan@mellanox.com,\n joyce.kong@arm.com, Parav Pandit <parav@mellanox.com>",
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        "From": "Parav Pandit <parav@mellanox.com>",
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    },
    "content": "Add mlx5 PCI bus which enables multiple mlx5 drivers to bind to single\npci device.\n\nSigned-off-by: Parav Pandit <parav@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\nChangelog:\nv4->v5:\n - Merged maintainers update patch with this patch\nv2->v3:\n - Addressed comments from Thomas and Asaf\n - Moved pci_driver structure instance as first in driver\n - Removed white spaces at the end of line in diagram\n - Address comments from Matan\n - Removed CONFIG_RTE_LIBRTE_MLX5_PCI_BUS from config files\n - Changed alignedment to mlx5 specific aligment instead of standard\n   DPDK\n - Using uint32_t instead of mlx5_class enum\nv1->v2:\n - Address comments from Thomas and Gaetan\n - Inheriting ret_pci_driver instead of rte_driver\n - Added design and description of the mlx5_pci bus\n---\n MAINTAINERS                                   |  5 ++\n drivers/bus/meson.build                       |  2 +-\n drivers/bus/mlx5_pci/Makefile                 | 38 +++++++++\n drivers/bus/mlx5_pci/meson.build              | 19 +++++\n drivers/bus/mlx5_pci/mlx5_pci_bus.c           | 14 ++++\n drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h       | 84 +++++++++++++++++++\n .../bus/mlx5_pci/rte_bus_mlx5_pci_version.map |  5 ++\n 7 files changed, 166 insertions(+), 1 deletion(-)\n create mode 100644 drivers/bus/mlx5_pci/Makefile\n create mode 100644 drivers/bus/mlx5_pci/meson.build\n create mode 100644 drivers/bus/mlx5_pci/mlx5_pci_bus.c\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map",
    "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 53a5e9a9e..e3fec55ca 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -517,6 +517,11 @@ Intel FPGA bus\n M: Rosen Xu <rosen.xu@intel.com>\n F: drivers/bus/ifpga/\n \n+Melllanox mlx5 PCI bus driver\n+M: Parav Pandit <parav@mellaox.com>\n+M: Matan Azrad <matan@mellanox.com>\n+F: drivers/bus/mlx5_pci\n+\n NXP buses\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n M: Sachin Saxena <sachin.saxena@nxp.com>\ndiff --git a/drivers/bus/meson.build b/drivers/bus/meson.build\nindex 80de2d91d..b1381838d 100644\n--- a/drivers/bus/meson.build\n+++ b/drivers/bus/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'vdev', 'vmbus']\n+drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'mlx5_pci', 'vdev', 'vmbus']\n std_deps = ['eal']\n config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'\n driver_name_fmt = 'rte_bus_@0@'\ndiff --git a/drivers/bus/mlx5_pci/Makefile b/drivers/bus/mlx5_pci/Makefile\nnew file mode 100644\nindex 000000000..de4ccd83f\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/Makefile\n@@ -0,0 +1,38 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2020 Mellanox Technologies, Ltd\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_bus_mlx5_pci.a\n+\n+CFLAGS += -O3 -Wall -Wextra\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -Wno-strict-prototypes\n+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5\n+CFLAGS += -I$(BUILDDIR)/drivers/common/mlx5\n+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5/linux\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci\n+LDLIBS += -lrte_eal\n+LDLIBS += -lrte_common_mlx5\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# versioning export map\n+EXPORT_MAP := rte_bus_mlx5_pci_version.map\n+\n+SRCS-y += mlx5_pci_bus.c\n+\n+# DEBUG which is usually provided on the command-line may enable\n+# CONFIG_RTE_LIBRTE_MLX5_DEBUG.\n+ifeq ($(DEBUG),1)\n+CONFIG_RTE_LIBRTE_MLX5_DEBUG := y\n+endif\n+\n+#\n+# Export include files\n+#\n+SYMLINK-y-include += rte_bus_mlx5_pci.h\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/bus/mlx5_pci/meson.build b/drivers/bus/mlx5_pci/meson.build\nnew file mode 100644\nindex 000000000..64a17cbad\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/meson.build\n@@ -0,0 +1,19 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Mellanox Technologies Ltd\n+\n+deps += ['pci', 'bus_pci', 'common_mlx5']\n+install_headers('rte_bus_mlx5_pci.h')\n+sources = files('mlx5_pci_bus.c')\n+\n+cflags_options = [\n+\t'-std=c11',\n+\t'-Wno-strict-prototypes',\n+\t'-D_BSD_SOURCE',\n+\t'-D_DEFAULT_SOURCE',\n+\t'-D_XOPEN_SOURCE=600'\n+]\n+foreach option:cflags_options\n+\tif cc.has_argument(option)\n+\t\tcflags += option\n+\tendif\n+endforeach\ndiff --git a/drivers/bus/mlx5_pci/mlx5_pci_bus.c b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\nnew file mode 100644\nindex 000000000..66db3c7b0\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include \"rte_bus_mlx5_pci.h\"\n+\n+static TAILQ_HEAD(mlx5_pci_bus_drv_head, rte_mlx5_pci_driver) drv_list =\n+\t\t\t\tTAILQ_HEAD_INITIALIZER(drv_list);\n+\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver)\n+{\n+\tTAILQ_INSERT_TAIL(&drv_list, driver, next);\n+}\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\nnew file mode 100644\nindex 000000000..9f8d22e2b\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef _RTE_BUS_MLX5_PCI_H_\n+#define _RTE_BUS_MLX5_PCI_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE Mellanox PCI Bus Interface\n+ * Mellanox ConnectX PCI device supports multiple class (net/vdpa/regex)\n+ * devices. This bus enables creating such multiple class of devices on a\n+ * single PCI device by allowing to bind multiple class specific device\n+ * driver to attach to mlx5_pci bus driver.\n+ *\n+ * -----------    ------------    -----------------\n+ * |   mlx5  |    |   mlx5   |    |   mlx5        |\n+ * | net pmd |    | vdpa pmd |    | new class pmd |\n+ * -----------    ------------    -----------------\n+ *      \\              |                /\n+ *       \\             |               /\n+ *        \\       -------------       /\n+ *         \\______|   mlx5    |_____ /\n+ *                |   pci bus |\n+ *                -------------\n+ *                     |\n+ *                 -----------\n+ *                 |   mlx5  |\n+ *                 | pci dev |\n+ *                 -----------\n+ *\n+ * - mlx5 pci bus driver binds to mlx5 PCI devices defined by PCI\n+ *   ID table of all related mlx5 PCI devices.\n+ * - mlx5 class driver such as net, vdpa, regex PMD defines its\n+ *   specific PCI ID table and mlx5 bus driver probes matching\n+ *   class drivers.\n+ * - mlx5 pci bus driver is cental place that validates supported\n+ *   class combinations.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif /* __cplusplus */\n+\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#include <mlx5_common.h>\n+\n+/**\n+ * A structure describing a mlx5 pci driver.\n+ */\n+struct rte_mlx5_pci_driver {\n+\tstruct rte_pci_driver pci_driver;\t/**< Inherit core pci driver. */\n+\tuint32_t dev_class;\t/**< Class of this driver, enum mlx5_class */\n+\tTAILQ_ENTRY(rte_mlx5_pci_driver) next;\n+};\n+\n+/**\n+ * Register a mlx5_pci device driver.\n+ *\n+ * @param driver\n+ *   A pointer to a rte_mlx5_pci_driver structure describing the driver\n+ *   to be registered.\n+ */\n+__rte_internal\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver);\n+\n+#define RTE_PMD_REGISTER_MLX5_PCI(nm, drv) \\\n+\tstatic const char *mlx5_pci_drvinit_fn_ ## nm; \\\n+\tRTE_INIT(mlx5_pci_drvinit_fn_ ##drv) \\\n+\t{ \\\n+\t\t(drv).driver.name = RTE_STR(nm); \\\n+\t\trte_mlx5_pci_driver_register(&drv); \\\n+\t} \\\n+\tRTE_PMD_EXPORT_NAME(nm, __COUNTER__)\n+\n+#ifdef __cplusplus\n+}\n+#endif /* __cplusplus */\n+\n+#endif /* _RTE_BUS_MLX5_PCI_H_ */\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\nnew file mode 100644\nindex 000000000..4cfd3db10\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\n@@ -0,0 +1,5 @@\n+INTERNAL {\n+\tglobal:\n+\n+\trte_mlx5_pci_driver_register;\n+};\n",
    "prefixes": [
        "v5",
        "6/9"
    ]
}