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[ { "id": 116316, "web_url": "https://patches.dpdk.org/comment/116316/", "msgid": "<BL0PR11MB2931813A8EE2601B3EB9DD85EB7B0@BL0PR11MB2931.namprd11.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/BL0PR11MB2931813A8EE2601B3EB9DD85EB7B0@BL0PR11MB2931.namprd11.prod.outlook.com", "date": "2020-07-20T14:37:35", "subject": "Re: [dpdk-dev] [PATCH v3] lib/table: fix cache alignment issue", "submitter": { "id": 19, "url": "https://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "content": "> -----Original Message-----\n> From: Xu, Ting <ting.xu@intel.com>\n> Sent: Thursday, July 9, 2020 2:48 AM\n> To: dev@dpdk.org\n> Cc: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; Xu, Ting\n> <ting.xu@intel.com>; stable@dpdk.org\n> Subject: [PATCH v3] lib/table: fix cache alignment issue\n> \n> When create softnic hash table with 16 keys, it failed on 32bit\n> environment because of the structure rte_bucket_4_16 alignment\n> issue. Add __rte_cache_aligned to ensure correct cache align.\n> \n> Fixes: 8aa327214c (\"table: hash\")\n> Cc: stable@dpdk.org\n> \n> Signed-off-by: Ting Xu <ting.xu@intel.com>\n> \n> ---\n> v2->v3: Rebase\n> v1->v2: Correct patch time\n> ---\n> lib/librte_table/rte_table_hash_key16.c | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/lib/librte_table/rte_table_hash_key16.c\n> b/lib/librte_table/rte_table_hash_key16.c\n> index 2cca1c924..5e1665c15 100644\n> --- a/lib/librte_table/rte_table_hash_key16.c\n> +++ b/lib/librte_table/rte_table_hash_key16.c\n> @@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n> \tuint64_t key[4][2];\n> \n> \t/* Cache line 2 */\n> -\tuint8_t data[0];\n> +\tuint8_t data[0] __rte_cache_aligned;\n> };\n> \n> struct rte_table_hash {\n> --\n> 2.17.1\n\nHi Ting,\n\nThis fix is breaking the execution for systems with cache line of 128 bytes, as typically (on 64-bit systems) this structure would be 64-byte in size and adding the __rte_cache_aligned would force doubling the size of this structure through padding enforced by the compiler.\n\nCan you please confirm this is caused by check below failing in the table create function:\n\tsizeof(struct rte_bucket_4_16) % 64) != 0\n\nSince all the other fields in this data structure are explicitly declared as 64-bit fields, due to the alignment rules I was expecting the compiler to add a 32-bit padding field after the \"next\" field, which is a pointer that would only take 32 bits on 32-bit systems. I am not sure why this did not take place in your case, any thoughts?\n\nNot sure why we would run Soft NIC on 32-bit systems, might be better to disable Soft NIC for 32-bit systems.\n\nThanks,\nCristian", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8D50EA0527;\n\tMon, 20 Jul 2020 16:37:51 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EAC831BFC4;\n\tMon, 20 Jul 2020 16:37:40 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 4BB9B1BFE3;\n Mon, 20 Jul 2020 16:37:38 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Jul 2020 07:37:37 -0700", "from fmsmsx601.amr.corp.intel.com ([10.18.126.81])\n by fmsmga005.fm.intel.com with ESMTP; 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dev@dpdk.org\n> Cc: stable@dpdk.org\n> Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> \n> Hi, Cristian\n> \n> > -----Original Message-----\n> > From: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>\n> > Sent: Monday, July 20, 2020 10:38 PM\n> > To: Xu, Ting <ting.xu@intel.com>; dev@dpdk.org\n> > Cc: stable@dpdk.org\n> > Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> >\n> >\n> >\n> > > -----Original Message-----\n> > > From: Xu, Ting <ting.xu@intel.com>\n> > > Sent: Thursday, July 9, 2020 2:48 AM\n> > > To: dev@dpdk.org\n> > > Cc: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; Xu, Ting\n> > > <ting.xu@intel.com>; stable@dpdk.org\n> > > Subject: [PATCH v3] lib/table: fix cache alignment issue\n> > >\n> > > When create softnic hash table with 16 keys, it failed on 32bit\n> > > environment because of the structure rte_bucket_4_16 alignment issue.\n> > > Add __rte_cache_aligned to ensure correct cache align.\n> > >\n> > > Fixes: 8aa327214c (\"table: hash\")\n> > > Cc: stable@dpdk.org\n> > >\n> > > Signed-off-by: Ting Xu <ting.xu@intel.com>\n> > >\n> > > ---\n> > > v2->v3: Rebase\n> > > v1->v2: Correct patch time\n> > > ---\n> > > lib/librte_table/rte_table_hash_key16.c | 2 +-\n> > > 1 file changed, 1 insertion(+), 1 deletion(-)\n> > >\n> > > diff --git a/lib/librte_table/rte_table_hash_key16.c\n> > > b/lib/librte_table/rte_table_hash_key16.c\n> > > index 2cca1c924..5e1665c15 100644\n> > > --- a/lib/librte_table/rte_table_hash_key16.c\n> > > +++ b/lib/librte_table/rte_table_hash_key16.c\n> > > @@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n> > > \tuint64_t key[4][2];\n> > >\n> > > \t/* Cache line 2 */\n> > > -\tuint8_t data[0];\n> > > +\tuint8_t data[0] __rte_cache_aligned;\n> > > };\n> > >\n> > > struct rte_table_hash {\n> > > --\n> > > 2.17.1\n> >\n> > Hi Ting,\n> >\n> > This fix is breaking the execution for systems with cache line of 128 bytes,\n> as\n> > typically (on 64-bit systems) this structure would be 64-byte in size and\n> > adding the __rte_cache_aligned would force doubling the size of this\n> > structure through padding enforced by the compiler.\n> >\n> > Can you please confirm this is caused by check below failing in the table\n> > create function:\n> > \tsizeof(struct rte_bucket_4_16) % 64) != 0\n> >\n> \n> The result of sizeof(struct rte_bucket_4_16) is 124 byte in this case, and this\n> is the direct reason causing this failure.\n> \n> > Since all the other fields in this data structure are explicitly declared as 64-\n> bit\n> > fields, due to the alignment rules I was expecting the compiler to add a 32-\n> bit\n> > padding field after the \"next\" field, which is a pointer that would only take\n> 32\n> > bits on 32-bit systems. I am not sure why this did not take place in your\n> case,\n> > any thoughts?\n> >\n> \n> It shows that the size of the field struct rte_bucket_4_16 *next in struct\n> rte_bucket_4_16 is only 32 bits. And there is no padding added by the\n> compiler in my and the reporter's case.\n> I tried to add a 32 bits pad field after the field next manually, and the result is\n> correct then.\n> Is it because in 32-bit system, the compiler will not extend the 32 bits pointer\n> to 64 bits, since the 32 bits size has already matched the cache line?\n> \n> > Not sure why we would run Soft NIC on 32-bit systems, might be better to\n> > disable Soft NIC for 32-bit systems.\n> >\n> \n\nMy proposed solution, which IMO provides the cleanest and most readable way to fix / maintain this code:\n\n#ifdef RTE_ARCH_64\n\nstruct rte_bucket_4_16 {\n\t//current definition of this struct\n};\n\n#else\n\nstruct rte_bucket_4_16 {\n\t//definition with padding fields for the 32-bit pointers to keep this struct to a multiple of 64 bytes\n};\n\n#endif\n\nWe need to apply the same for 8-byte key and 32-byte key hash functions from the same folder.\n\nWhat do you think, Ting?\n\n> To be honest, I do not know why we should run softnic on 32-bit system, I\n> was just assigned this specific bug. It seems there is a complete test case for\n> validation team to test softnic in 32-bit system.\n> I am not sure is it OK to tell the validation team that we should disable softnic\n> in 32-bit system now. Or we should fix this issue this time and discuss about\n> the problem later?\n> \n> Thanks!\n> \n> > Thanks,\n> > Cristian", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E0E0BA0526;\n\tTue, 21 Jul 2020 23:16:50 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 796761C0AE;\n\tTue, 21 Jul 2020 23:16:49 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 5742E1C07E;\n Tue, 21 Jul 2020 23:16:47 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 14:16:46 -0700", "from orsmsx102.amr.corp.intel.com ([10.22.225.129])\n by FMSMGA003.fm.intel.com with ESMTP; 21 Jul 2020 14:16:46 -0700", "from ORSEDG001.ED.cps.intel.com (10.7.248.4) by\n ORSMSX102.amr.corp.intel.com (10.22.225.129) with Microsoft SMTP Server (TLS)\n id 14.3.439.0; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "BYAPR11MB2935.namprd11.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1defc0f3-383b-4dbe-978f-08d82dbb5ed6", "X-MS-Exchange-CrossTenant-originalarrivaltime": "21 Jul 2020 21:16:44.4542 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "46c98d88-e344-4ed4-8496-4ed7712e255d", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n U747lGZqTe9W5ZUi4Rf2lMTcpHfMkS7Ow/VqYjFaR0A/eYVLNvfLasCuDPYShkRQLarpEcFRygCY7DEOX92N5uC9X6cHMB7w0gFJKT+8vwo=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR11MB2758", "X-OriginatorOrg": "intel.com", "Subject": "Re: [dpdk-dev] [PATCH v3] lib/table: fix cache alignment issue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 116367, "web_url": "https://patches.dpdk.org/comment/116367/", "msgid": "<CY4PR1101MB2310C59B19F5CD8C2E1D60FFF8780@CY4PR1101MB2310.namprd11.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/CY4PR1101MB2310C59B19F5CD8C2E1D60FFF8780@CY4PR1101MB2310.namprd11.prod.outlook.com", "date": "2020-07-21T05:15:55", "subject": "Re: [dpdk-dev] [PATCH v3] lib/table: fix cache alignment issue", "submitter": { "id": 1363, "url": "https://patches.dpdk.org/api/people/1363/?format=api", "name": "Xu, Ting", "email": "ting.xu@intel.com" }, "content": "Hi, Cristian\n\n> -----Original Message-----\n> From: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>\n> Sent: Monday, July 20, 2020 10:38 PM\n> To: Xu, Ting <ting.xu@intel.com>; dev@dpdk.org\n> Cc: stable@dpdk.org\n> Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> \n> \n> \n> > -----Original Message-----\n> > From: Xu, Ting <ting.xu@intel.com>\n> > Sent: Thursday, July 9, 2020 2:48 AM\n> > To: dev@dpdk.org\n> > Cc: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; Xu, Ting\n> > <ting.xu@intel.com>; stable@dpdk.org\n> > Subject: [PATCH v3] lib/table: fix cache alignment issue\n> >\n> > When create softnic hash table with 16 keys, it failed on 32bit\n> > environment because of the structure rte_bucket_4_16 alignment issue.\n> > Add __rte_cache_aligned to ensure correct cache align.\n> >\n> > Fixes: 8aa327214c (\"table: hash\")\n> > Cc: stable@dpdk.org\n> >\n> > Signed-off-by: Ting Xu <ting.xu@intel.com>\n> >\n> > ---\n> > v2->v3: Rebase\n> > v1->v2: Correct patch time\n> > ---\n> > lib/librte_table/rte_table_hash_key16.c | 2 +-\n> > 1 file changed, 1 insertion(+), 1 deletion(-)\n> >\n> > diff --git a/lib/librte_table/rte_table_hash_key16.c\n> > b/lib/librte_table/rte_table_hash_key16.c\n> > index 2cca1c924..5e1665c15 100644\n> > --- a/lib/librte_table/rte_table_hash_key16.c\n> > +++ b/lib/librte_table/rte_table_hash_key16.c\n> > @@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n> > \tuint64_t key[4][2];\n> >\n> > \t/* Cache line 2 */\n> > -\tuint8_t data[0];\n> > +\tuint8_t data[0] __rte_cache_aligned;\n> > };\n> >\n> > struct rte_table_hash {\n> > --\n> > 2.17.1\n> \n> Hi Ting,\n> \n> This fix is breaking the execution for systems with cache line of 128 bytes, as\n> typically (on 64-bit systems) this structure would be 64-byte in size and\n> adding the __rte_cache_aligned would force doubling the size of this\n> structure through padding enforced by the compiler.\n> \n> Can you please confirm this is caused by check below failing in the table\n> create function:\n> \tsizeof(struct rte_bucket_4_16) % 64) != 0\n> \n\nThe result of sizeof(struct rte_bucket_4_16) is 124 byte in this case, and this is the direct reason causing this failure.\n\n> Since all the other fields in this data structure are explicitly declared as 64-bit\n> fields, due to the alignment rules I was expecting the compiler to add a 32-bit\n> padding field after the \"next\" field, which is a pointer that would only take 32\n> bits on 32-bit systems. I am not sure why this did not take place in your case,\n> any thoughts?\n> \n\nIt shows that the size of the field struct rte_bucket_4_16 *next in struct rte_bucket_4_16 is only 32 bits. And there is no padding added by the compiler in my and the reporter's case.\nI tried to add a 32 bits pad field after the field next manually, and the result is correct then.\nIs it because in 32-bit system, the compiler will not extend the 32 bits pointer to 64 bits, since the 32 bits size has already matched the cache line?\n\n> Not sure why we would run Soft NIC on 32-bit systems, might be better to\n> disable Soft NIC for 32-bit systems.\n> \n\nTo be honest, I do not know why we should run softnic on 32-bit system, I was just assigned this specific bug. It seems there is a complete test case for validation team to test softnic in 32-bit system.\nI am not sure is it OK to tell the validation team that we should disable softnic in 32-bit system now. Or we should fix this issue this time and discuss about the problem later?\n\nThanks!\n\n> Thanks,\n> Cristian", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F3BE5A0526;\n\tTue, 21 Jul 2020 07:16:02 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2CA4B1BFFC;\n\tTue, 21 Jul 2020 07:16:01 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id F0C3F1BFFB;\n Tue, 21 Jul 2020 07:15:58 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Jul 2020 22:15:57 -0700", "from fmsmsx108.amr.corp.intel.com ([10.18.124.206])\n by fmsmga002.fm.intel.com with ESMTP; 20 Jul 2020 22:15:57 -0700", "from fmsmsx152.amr.corp.intel.com (10.18.125.5) by\n FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS)\n id 14.3.439.0; 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dev@dpdk.org\n> Cc: stable@dpdk.org\n> Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> \n> \n> \n> > -----Original Message-----\n> > From: Xu, Ting <ting.xu@intel.com>\n> > Sent: Tuesday, July 21, 2020 6:16 AM\n> > To: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; dev@dpdk.org\n> > Cc: stable@dpdk.org\n> > Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> >\n> > Hi, Cristian\n> >\n> > > -----Original Message-----\n> > > From: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>\n> > > Sent: Monday, July 20, 2020 10:38 PM\n> > > To: Xu, Ting <ting.xu@intel.com>; dev@dpdk.org\n> > > Cc: stable@dpdk.org\n> > > Subject: RE: [PATCH v3] lib/table: fix cache alignment issue\n> > >\n> > >\n> > >\n> > > > -----Original Message-----\n> > > > From: Xu, Ting <ting.xu@intel.com>\n> > > > Sent: Thursday, July 9, 2020 2:48 AM\n> > > > To: dev@dpdk.org\n> > > > Cc: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; Xu, Ting\n> > > > <ting.xu@intel.com>; stable@dpdk.org\n> > > > Subject: [PATCH v3] lib/table: fix cache alignment issue\n> > > >\n> > > > When create softnic hash table with 16 keys, it failed on 32bit\n> > > > environment because of the structure rte_bucket_4_16 alignment issue.\n> > > > Add __rte_cache_aligned to ensure correct cache align.\n> > > >\n> > > > Fixes: 8aa327214c (\"table: hash\")\n> > > > Cc: stable@dpdk.org\n> > > >\n> > > > Signed-off-by: Ting Xu <ting.xu@intel.com>\n> > > >\n> > > > ---\n> > > > v2->v3: Rebase\n> > > > v1->v2: Correct patch time\n> > > > ---\n> > > > lib/librte_table/rte_table_hash_key16.c | 2 +-\n> > > > 1 file changed, 1 insertion(+), 1 deletion(-)\n> > > >\n> > > > diff --git a/lib/librte_table/rte_table_hash_key16.c\n> > > > b/lib/librte_table/rte_table_hash_key16.c\n> > > > index 2cca1c924..5e1665c15 100644\n> > > > --- a/lib/librte_table/rte_table_hash_key16.c\n> > > > +++ b/lib/librte_table/rte_table_hash_key16.c\n> > > > @@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n> > > > \tuint64_t key[4][2];\n> > > >\n> > > > \t/* Cache line 2 */\n> > > > -\tuint8_t data[0];\n> > > > +\tuint8_t data[0] __rte_cache_aligned;\n> > > > };\n> > > >\n> > > > struct rte_table_hash {\n> > > > --\n> > > > 2.17.1\n> > >\n> > > Hi Ting,\n> > >\n> > > This fix is breaking the execution for systems with cache line of\n> > > 128 bytes,\n> > as\n> > > typically (on 64-bit systems) this structure would be 64-byte in\n> > > size and adding the __rte_cache_aligned would force doubling the\n> > > size of this structure through padding enforced by the compiler.\n> > >\n> > > Can you please confirm this is caused by check below failing in the\n> > > table create function:\n> > > \tsizeof(struct rte_bucket_4_16) % 64) != 0\n> > >\n> >\n> > The result of sizeof(struct rte_bucket_4_16) is 124 byte in this case,\n> > and this is the direct reason causing this failure.\n> >\n> > > Since all the other fields in this data structure are explicitly\n> > > declared as 64-\n> > bit\n> > > fields, due to the alignment rules I was expecting the compiler to\n> > > add a 32-\n> > bit\n> > > padding field after the \"next\" field, which is a pointer that would\n> > > only take\n> > 32\n> > > bits on 32-bit systems. I am not sure why this did not take place in\n> > > your\n> > case,\n> > > any thoughts?\n> > >\n> >\n> > It shows that the size of the field struct rte_bucket_4_16 *next in\n> > struct\n> > rte_bucket_4_16 is only 32 bits. And there is no padding added by the\n> > compiler in my and the reporter's case.\n> > I tried to add a 32 bits pad field after the field next manually, and\n> > the result is correct then.\n> > Is it because in 32-bit system, the compiler will not extend the 32\n> > bits pointer to 64 bits, since the 32 bits size has already matched the cache\n> line?\n> >\n> > > Not sure why we would run Soft NIC on 32-bit systems, might be\n> > > better to disable Soft NIC for 32-bit systems.\n> > >\n> >\n> \n> My proposed solution, which IMO provides the cleanest and most readable\n> way to fix / maintain this code:\n> \n> #ifdef RTE_ARCH_64\n> \n> struct rte_bucket_4_16 {\n> \t//current definition of this struct\n> };\n> \n> #else\n> \n> struct rte_bucket_4_16 {\n> \t//definition with padding fields for the 32-bit pointers to keep this\n> struct to a multiple of 64 bytes };\n> \n> #endif\n> \n> We need to apply the same for 8-byte key and 32-byte key hash functions\n> from the same folder.\n> \n> What do you think, Ting?\n> \n\nThanks for your advice. I think it makes sense.\nI have updated a new patch version based on this method, could you please help review?\n\nThanks!\n\n> > To be honest, I do not know why we should run softnic on 32-bit\n> > system, I was just assigned this specific bug. It seems there is a\n> > complete test case for validation team to test softnic in 32-bit system.\n> > I am not sure is it OK to tell the validation team that we should\n> > disable softnic in 32-bit system now. Or we should fix this issue this\n> > time and discuss about the problem later?\n> >\n> > Thanks!\n> >\n> > > Thanks,\n> > > Cristian", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C4B94A0526;\n\tWed, 22 Jul 2020 04:16:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 77E441BFBB;\n\tWed, 22 Jul 2020 04:16:35 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id CFA95199BC;\n Wed, 22 Jul 2020 04:16:32 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 19:16:31 -0700", "from fmsmsx106.amr.corp.intel.com ([10.18.124.204])\n by orsmga007.jf.intel.com with ESMTP; 21 Jul 2020 19:16:31 -0700", "from fmsmsx612.amr.corp.intel.com (10.18.126.92) by\n FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS)\n id 14.3.439.0; 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