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GET /api/patches/73568/?format=api
https://patches.dpdk.org/api/patches/73568/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200709014426.13641-1-ting.xu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200709014426.13641-1-ting.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200709014426.13641-1-ting.xu@intel.com", "date": "2020-07-09T01:44:26", "name": "[v3] lib/table: fix cache alignment issue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1d0e3258bb82fcab819fda5a300b1badc6ce5e37", "submitter": { "id": 1363, "url": "https://patches.dpdk.org/api/people/1363/?format=api", "name": "Xu, Ting", "email": "ting.xu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200709014426.13641-1-ting.xu@intel.com/mbox/", "series": [ { "id": 10903, "url": "https://patches.dpdk.org/api/series/10903/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10903", "date": "2020-07-09T01:44:26", "name": "[v3] lib/table: fix cache alignment issue", "version": 3, "mbox": "https://patches.dpdk.org/series/10903/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/73568/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/73568/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A9D4EA0526;\n\tThu, 9 Jul 2020 03:40:39 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 854B01DBE7;\n\tThu, 9 Jul 2020 03:40:39 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 206B51D9DA;\n Thu, 9 Jul 2020 03:40:37 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Jul 2020 18:40:37 -0700", "from dpdk-xuting-second.sh.intel.com ([10.67.116.154])\n by orsmga006.jf.intel.com with ESMTP; 08 Jul 2020 18:40:35 -0700" ], "IronPort-SDR": [ "\n SKTVl06HIXSgyoJCT+USUi3Pay13pUrSvDm2KAo6xfPYreT/5spAiIahbZlbT61E6hJciftmxH\n e55cndX1zzpw==", "\n I9ZNUL4O/RWmZw5lfsZ7FmTsOVnZ4REcoMjyoxb9VtWAUeXhuIZUbiogfuQxJnfnfw0z4R1BeL\n T/huWS95LkTQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9676\"; a=\"149416612\"", "E=Sophos;i=\"5.75,330,1589266800\"; d=\"scan'208\";a=\"149416612\"", "E=Sophos;i=\"5.75,330,1589266800\"; d=\"scan'208\";a=\"283977878\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ting Xu <ting.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com, Ting Xu <ting.xu@intel.com>,\n stable@dpdk.org", "Date": "Thu, 9 Jul 2020 09:44:26 +0800", "Message-Id": "<20200709014426.13641-1-ting.xu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "Subject": "[dpdk-dev] [PATCH v3] lib/table: fix cache alignment issue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When create softnic hash table with 16 keys, it failed on 32bit\nenvironment because of the structure rte_bucket_4_16 alignment\nissue. Add __rte_cache_aligned to ensure correct cache align.\n\nFixes: 8aa327214c (\"table: hash\")\nCc: stable@dpdk.org\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\n\n---\nv2->v3: Rebase\nv1->v2: Correct patch time\n---\n lib/librte_table/rte_table_hash_key16.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c\nindex 2cca1c924..5e1665c15 100644\n--- a/lib/librte_table/rte_table_hash_key16.c\n+++ b/lib/librte_table/rte_table_hash_key16.c\n@@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n \tuint64_t key[4][2];\n \n \t/* Cache line 2 */\n-\tuint8_t data[0];\n+\tuint8_t data[0] __rte_cache_aligned;\n };\n \n struct rte_table_hash {\n", "prefixes": [ "v3" ] }{ "id": 73568, "url": "