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{
    "id": 73567,
    "url": "https://patches.dpdk.org/api/patches/73567/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200709014334.13543-1-ting.xu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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    "msgid": "<20200709014334.13543-1-ting.xu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200709014334.13543-1-ting.xu@intel.com",
    "date": "2020-07-09T01:43:34",
    "name": "[v1] lib/table: fix cache alignment issue",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "1d0e3258bb82fcab819fda5a300b1badc6ce5e37",
    "submitter": {
        "id": 1363,
        "url": "https://patches.dpdk.org/api/people/1363/?format=api",
        "name": "Xu, Ting",
        "email": "ting.xu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200709014334.13543-1-ting.xu@intel.com/mbox/",
    "series": [
        {
            "id": 10902,
            "url": "https://patches.dpdk.org/api/series/10902/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10902",
            "date": "2020-07-09T01:43:34",
            "name": "[v1] lib/table: fix cache alignment issue",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/10902/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73567/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/73567/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
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        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A971A0526;\n\tThu,  9 Jul 2020 03:39:51 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AE5CC1DA57;\n\tThu,  9 Jul 2020 03:39:50 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id EDECD1D9DA;\n Thu,  9 Jul 2020 03:39:47 +0200 (CEST)",
            "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Jul 2020 18:39:46 -0700",
            "from dpdk-xuting-second.sh.intel.com ([10.67.116.154])\n by orsmga006.jf.intel.com with ESMTP; 08 Jul 2020 18:39:44 -0700"
        ],
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        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Ting Xu <ting.xu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com, Ting Xu <ting.xu@intel.com>,\n stable@dpdk.org",
        "Date": "Thu,  9 Jul 2020 09:43:34 +0800",
        "Message-Id": "<20200709014334.13543-1-ting.xu@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "Subject": "[dpdk-dev] [PATCH v1] lib/table: fix cache alignment issue",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When create softnic hash table with 16 keys, it failed on 32bit\nenvironment because of the structure rte_bucket_4_16 alignment\nissue. Add __rte_cache_aligned to ensure correct cache align.\n\nFixes: 8aa327214c (\"table: hash\")\nCc: stable@dpdk.org\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\n---\n lib/librte_table/rte_table_hash_key16.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)",
    "diff": "diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c\nindex 2cca1c924..5e1665c15 100644\n--- a/lib/librte_table/rte_table_hash_key16.c\n+++ b/lib/librte_table/rte_table_hash_key16.c\n@@ -44,7 +44,7 @@ struct rte_bucket_4_16 {\n \tuint64_t key[4][2];\n \n \t/* Cache line 2 */\n-\tuint8_t data[0];\n+\tuint8_t data[0] __rte_cache_aligned;\n };\n \n struct rte_table_hash {\n",
    "prefixes": [
        "v1"
    ]
}