List comments

GET /api/patches/73566/comments/
HTTP 200 OK
Allow: GET, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

[
    {
        "id": 115605,
        "web_url": "https://patches.dpdk.org/comment/115605/",
        "msgid": "<CALBAE1N4mM4BNDzWv1hu7NOYRObzt=VYOPCf_=4=wNz15KHyLg@mail.gmail.com>",
        "date": "2020-07-09T10:11:15",
        "subject": "Re: [dpdk-dev] [PATCH v5 4/4] net/qede: add support for get\n\tregister operation",
        "submitter": {
            "id": 1270,
            "url": "https://patches.dpdk.org/api/people/1270/",
            "name": "Jerin Jacob",
            "email": "jerinjacobk@gmail.com"
        },
        "content": "On Thu, Jul 9, 2020 at 4:22 AM Rasesh Mody <rmody@marvell.com> wrote:\n>\n> Add support for .get_reg eth_dev ops which will be used to collect the\n> firmware debug data.\n>\n> PMD on detecting on some HW errors will collect the FW/HW Dump to a\n> buffer and then it will save it to a file implemented in\n> qede_save_fw_dump().\n>\n> Dump file location and name:\n> Location: <RTE_SDK> or DPDK root\n> Name: qede_pmd_dump_mm-dd-yy_hh-mm-ss.bin\n>\n> DPDK applications can initiate a debug data collection by invoking DPDK\n> library’s rte_eth_dev_get_reg_info() API. This API invokes .get_reg()\n> interface in the PMD.\n>\n> PMD implementation of .get_reg() collects the FW/HW Dump, saves it to\n> data field of rte_dev_reg_info and passes it to the application. It’s\n> the responsibility of the application to save the FW/HW Dump to a file.\n> We recommendation using the file name format used by qede_save_fw_dump().\n>\n> Signed-off-by: Rasesh Mody <rmody@marvell.com>\n> Signed-off-by: Igor Russkikh <irusskikh@marvell.com>\n\n\nSeries applied to dpdk-next-net-mrvl/master. Thanks.\n\n>  doc/guides/nics/features/qede.ini |   1 +\n>  drivers/net/qede/Makefile         |   1 +\n>  drivers/net/qede/base/bcm_osal.c  |  25 +++\n>  drivers/net/qede/base/bcm_osal.h  |   5 +\n>  drivers/net/qede/meson.build      |   1 +\n>  drivers/net/qede/qede_ethdev.c    |   1 +\n>  drivers/net/qede/qede_ethdev.h    |  25 +++\n>  drivers/net/qede/qede_regs.c      | 271 ++++++++++++++++++++++++++++++\n>  8 files changed, 330 insertions(+)\n>  create mode 100644 drivers/net/qede/qede_regs.c\n>\n> diff --git a/doc/guides/nics/features/qede.ini b/doc/guides/nics/features/qede.ini\n> index 20c90e626..f8716523e 100644\n> --- a/doc/guides/nics/features/qede.ini\n> +++ b/doc/guides/nics/features/qede.ini\n> @@ -31,6 +31,7 @@ Packet type parsing  = Y\n>  Basic stats          = Y\n>  Extended stats       = Y\n>  Stats per queue      = Y\n> +Registers dump       = Y\n>  Multiprocess aware   = Y\n>  Linux UIO            = Y\n>  Linux VFIO           = Y\n> diff --git a/drivers/net/qede/Makefile b/drivers/net/qede/Makefile\n> index 3b00338ff..0e8a67b0d 100644\n> --- a/drivers/net/qede/Makefile\n> +++ b/drivers/net/qede/Makefile\n> @@ -104,5 +104,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_main.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_rxtx.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_filter.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_debug.c\n> +SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_regs.c\n>\n>  include $(RTE_SDK)/mk/rte.lib.mk\n> diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\n> index 45557fe3c..65837b53d 100644\n> --- a/drivers/net/qede/base/bcm_osal.c\n> +++ b/drivers/net/qede/base/bcm_osal.c\n> @@ -246,6 +246,28 @@ qede_get_mcp_proto_stats(struct ecore_dev *edev,\n>         }\n>  }\n>\n> +static void qede_hw_err_handler(void *dev, enum ecore_hw_err_type err_type)\n> +{\n> +       struct ecore_dev *edev = dev;\n> +\n> +       switch (err_type) {\n> +       case ECORE_HW_ERR_FAN_FAIL:\n> +               break;\n> +\n> +       case ECORE_HW_ERR_MFW_RESP_FAIL:\n> +       case ECORE_HW_ERR_HW_ATTN:\n> +       case ECORE_HW_ERR_DMAE_FAIL:\n> +       case ECORE_HW_ERR_RAMROD_FAIL:\n> +       case ECORE_HW_ERR_FW_ASSERT:\n> +               OSAL_SAVE_FW_DUMP(0); /* Using port 0 as default port_id */\n> +               break;\n> +\n> +       default:\n> +               DP_NOTICE(edev, false, \"Unknown HW error [%d]\\n\", err_type);\n> +               return;\n> +       }\n> +}\n> +\n>  void\n>  qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)\n>  {\n> @@ -275,6 +297,9 @@ qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)\n>         }\n>\n>         DP_ERR(p_hwfn, \"HW error occurred [%s]\\n\", err_str);\n> +\n> +       qede_hw_err_handler(p_hwfn->p_dev, err_type);\n> +\n>         ecore_int_attn_clr_enable(p_hwfn->p_dev, true);\n>  }\n>\n> diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\n> index b4b94231b..5d4df5907 100644\n> --- a/drivers/net/qede/base/bcm_osal.h\n> +++ b/drivers/net/qede/base/bcm_osal.h\n> @@ -371,6 +371,11 @@ void qede_hw_err_notify(struct ecore_hwfn *p_hwfn,\n>\n>  /* TODO: */\n>  #define OSAL_SCHEDULE_RECOVERY_HANDLER(hwfn) nothing\n> +\n> +int qede_save_fw_dump(uint8_t port_id);\n> +\n> +#define OSAL_SAVE_FW_DUMP(port_id) qede_save_fw_dump(port_id)\n> +\n>  #define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) \\\n>         qede_hw_err_notify(hwfn, err_type)\n>\n> diff --git a/drivers/net/qede/meson.build b/drivers/net/qede/meson.build\n> index 50c9fad7e..05c9bff73 100644\n> --- a/drivers/net/qede/meson.build\n> +++ b/drivers/net/qede/meson.build\n> @@ -10,6 +10,7 @@ sources = files(\n>         'qede_main.c',\n>         'qede_rxtx.c',\n>         'qede_debug.c',\n> +       'qede_regs.c',\n>  )\n>\n>  if cc.has_argument('-Wno-format-nonliteral')\n> diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\n> index b5d6c7c43..e5a2581dd 100644\n> --- a/drivers/net/qede/qede_ethdev.c\n> +++ b/drivers/net/qede/qede_ethdev.c\n> @@ -2426,6 +2426,7 @@ static const struct eth_dev_ops qede_eth_dev_ops = {\n>         .udp_tunnel_port_add = qede_udp_dst_port_add,\n>         .udp_tunnel_port_del = qede_udp_dst_port_del,\n>         .fw_version_get = qede_fw_version_get,\n> +       .get_reg = qede_get_regs,\n>  };\n>\n>  static const struct eth_dev_ops qede_eth_vf_dev_ops = {\n> diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h\n> index b988a73f2..76c5dae3b 100644\n> --- a/drivers/net/qede/qede_ethdev.h\n> +++ b/drivers/net/qede/qede_ethdev.h\n> @@ -214,6 +214,8 @@ struct qede_tunn_params {\n>         uint16_t udp_port;\n>  };\n>\n> +#define QEDE_FW_DUMP_FILE_SIZE 128\n> +\n>  /*\n>   *  Structure to store private data for each port.\n>   */\n> @@ -252,6 +254,7 @@ struct qede_dev {\n>         char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];\n>         bool vport_started;\n>         int vlan_offload_mask;\n> +       char dump_file[QEDE_FW_DUMP_FILE_SIZE];\n>         void *ethdev;\n>  };\n>\n> @@ -313,4 +316,26 @@ void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);\n>  int qede_ucast_filter(struct rte_eth_dev *eth_dev,\n>                       struct ecore_filter_ucast *ucast,\n>                       bool add);\n> +\n> +#define REGDUMP_HEADER_SIZE sizeof(u32)\n> +#define REGDUMP_HEADER_FEATURE_SHIFT 24\n> +#define REGDUMP_HEADER_ENGINE_SHIFT 31\n> +#define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30\n> +\n> +enum debug_print_features {\n> +       OLD_MODE = 0,\n> +       IDLE_CHK = 1,\n> +       GRC_DUMP = 2,\n> +       MCP_TRACE = 3,\n> +       REG_FIFO = 4,\n> +       PROTECTION_OVERRIDE = 5,\n> +       IGU_FIFO = 6,\n> +       PHY = 7,\n> +       FW_ASSERTS = 8,\n> +};\n> +\n> +int qede_get_regs_len(struct qede_dev *qdev);\n> +int qede_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs);\n> +void qede_config_rx_mode(struct rte_eth_dev *eth_dev);\n> +void qed_dbg_dump(struct rte_eth_dev *eth_dev);\n>  #endif /* _QEDE_ETHDEV_H_ */\n> diff --git a/drivers/net/qede/qede_regs.c b/drivers/net/qede/qede_regs.c\n> new file mode 100644\n> index 000000000..73760bdfd\n> --- /dev/null\n> +++ b/drivers/net/qede/qede_regs.c\n> @@ -0,0 +1,271 @@\n> +/* SPDX-License-Identifier: BSD-3-Clause\n> + * Copyright (c) 2020 Marvell Semiconductor Inc.\n> + * All rights reserved.\n> + * www.marvell.com\n> + */\n> +\n> +#include <stdio.h>\n> +#include <stdlib.h>\n> +#include <fcntl.h>\n> +#include <time.h>\n> +#include <rte_ethdev.h>\n> +#include \"base/bcm_osal.h\"\n> +#include \"qede_ethdev.h\"\n> +\n> +int\n> +qede_get_regs_len(struct qede_dev *qdev)\n> +{\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       int cur_engine, num_of_hwfns, regs_len = 0;\n> +       uint8_t org_engine;\n> +\n> +       if (IS_VF(edev))\n> +               return 0;\n> +\n> +       if (qdev->ops && qdev->ops->common) {\n> +               num_of_hwfns = qdev->dev_info.common.num_hwfns;\n> +               org_engine = qdev->ops->common->dbg_get_debug_engine(edev);\n> +               for (cur_engine = 0; cur_engine < num_of_hwfns; cur_engine++) {\n> +                       /* compute required buffer size for idle_chks and\n> +                        * grcDump for each hw function\n> +                        */\n> +                       DP_NOTICE(edev, false,\n> +                               \"Calculating idle_chk and grcdump register length for current engine\\n\");\n> +                       qdev->ops->common->dbg_set_debug_engine(edev,\n> +                                                               cur_engine);\n> +                       regs_len += REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_idle_chk_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_idle_chk_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_grc_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_reg_fifo_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_protection_override_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_igu_fifo_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_fw_asserts_size(edev);\n> +               }\n> +               /* compute required buffer size for mcp trace and add it to the\n> +                * total required buffer size\n> +                */\n> +               regs_len += REGDUMP_HEADER_SIZE +\n> +                           qdev->ops->common->dbg_mcp_trace_size(edev);\n> +\n> +               qdev->ops->common->dbg_set_debug_engine(edev, org_engine);\n> +       }\n> +       DP_NOTICE(edev, false, \"Total length = %u\\n\", regs_len);\n> +\n> +       return regs_len;\n> +}\n> +\n> +static uint32_t\n> +qede_calc_regdump_header(enum debug_print_features feature, int engine,\n> +                        uint32_t feature_size, uint8_t omit_engine)\n> +{\n> +       /* insert the engine, feature and mode inside the header and\n> +        * combine it with feature size\n> +        */\n> +       return (feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) |\n> +               (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) |\n> +               (engine << REGDUMP_HEADER_ENGINE_SHIFT));\n> +}\n> +\n> +int qede_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n> +{\n> +       struct qede_dev *qdev = eth_dev->data->dev_private;\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       uint32_t *buffer = regs->data;\n> +       int cur_engine, num_of_hwfns;\n> +       /* '1' tells the parser to omit the engine number in the output files */\n> +       uint8_t omit_engine = 0;\n> +       uint8_t org_engine;\n> +       uint32_t feature_size;\n> +       uint32_t offset = 0;\n> +\n> +       if (IS_VF(edev))\n> +               return -ENOTSUP;\n> +\n> +       if (buffer == NULL) {\n> +               regs->length = qede_get_regs_len(qdev);\n> +               regs->width =  sizeof(uint32_t);\n> +               DP_INFO(edev, \"Length %u\\n\", regs->length);\n> +               return 0;\n> +       }\n> +\n> +       memset(buffer, 0, regs->length);\n> +       num_of_hwfns = qdev->dev_info.common.num_hwfns;\n> +       if (num_of_hwfns == 1)\n> +               omit_engine = 1;\n> +\n> +       OSAL_MUTEX_ACQUIRE(&edev->dbg_lock);\n> +\n> +       org_engine = qdev->ops->common->dbg_get_debug_engine(edev);\n> +       for (cur_engine = 0; cur_engine < num_of_hwfns; cur_engine++) {\n> +               /* collect idle_chks and grcDump for each hw function */\n> +               DP_NOTICE(edev, false, \"obtaining idle_chk and grcdump for current engine\\n\");\n> +               qdev->ops->common->dbg_set_debug_engine(edev, cur_engine);\n> +\n> +               /* first idle_chk */\n> +               qdev->ops->common->dbg_idle_chk(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IDLE_CHK, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Idle Check1 feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* second idle_chk */\n> +               qdev->ops->common->dbg_idle_chk(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IDLE_CHK, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Idle Check2 feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* reg_fifo dump */\n> +               qdev->ops->common->dbg_reg_fifo(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(REG_FIFO, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Reg fifo feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* igu_fifo dump */\n> +               qdev->ops->common->dbg_igu_fifo(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IGU_FIFO, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"IGU fifo feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* protection_override dump */\n> +               qdev->ops->common->dbg_protection_override(edev,\n> +                                                          (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                      qede_calc_regdump_header(PROTECTION_OVERRIDE, cur_engine,\n> +                                               feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Protection override feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* fw_asserts dump */\n> +               qdev->ops->common->dbg_fw_asserts(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(FW_ASSERTS, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"FW assert feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* grc dump */\n> +               qdev->ops->common->dbg_grc(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(GRC_DUMP, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"GRC dump feature_size %u\\n\",\n> +                         feature_size);\n> +       }\n> +\n> +       /* mcp_trace */\n> +       qdev->ops->common->dbg_mcp_trace(edev, (uint8_t *)buffer +\n> +               offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +       *(uint32_t *)((uint8_t *)buffer + offset) =\n> +               qede_calc_regdump_header(MCP_TRACE, cur_engine, feature_size,\n> +                                        omit_engine);\n> +       offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +       DP_NOTICE(edev, false, \"MCP trace feature_size %u\\n\", feature_size);\n> +\n> +       qdev->ops->common->dbg_set_debug_engine(edev, org_engine);\n> +\n> +       OSAL_MUTEX_RELEASE(&edev->dbg_lock);\n> +\n> +       return 0;\n> +}\n> +\n> +static void\n> +qede_set_fw_dump_file_name(struct qede_dev *qdev)\n> +{\n> +       time_t ltime;\n> +       struct tm *tm;\n> +\n> +       ltime = time(NULL);\n> +       tm = localtime(&ltime);\n> +       snprintf(qdev->dump_file, QEDE_FW_DUMP_FILE_SIZE,\n> +                \"qede_pmd_dump_%02d-%02d-%02d_%02d-%02d-%02d.bin\",\n> +                tm->tm_mon + 1, (int)tm->tm_mday, 1900 + tm->tm_year,\n> +                tm->tm_hour, tm->tm_min, tm->tm_sec);\n> +}\n> +\n> +static int\n> +qede_write_fwdump(const char *dump_file, void *dump, size_t len)\n> +{\n> +       int err = 0;\n> +       FILE *f;\n> +       size_t bytes;\n> +\n> +       f = fopen(dump_file, \"wb+\");\n> +\n> +       if (!f) {\n> +               fprintf(stderr, \"Can't open file %s: %s\\n\",\n> +                       dump_file, strerror(errno));\n> +               return 1;\n> +       }\n> +       bytes = fwrite(dump, 1, len, f);\n> +       if (bytes != len) {\n> +               fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n> +                       bytes, len);\n> +               err = 1;\n> +       }\n> +\n> +       if (fclose(f)) {\n> +               fprintf(stderr, \"Can't close file %s: %s\\n\",\n> +                       dump_file, strerror(errno));\n> +               err = 1;\n> +       }\n> +\n> +       return err;\n> +}\n> +\n> +int\n> +qede_save_fw_dump(uint8_t port_id)\n> +{\n> +       struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];\n> +       struct rte_dev_reg_info regs;\n> +       struct qede_dev *qdev = eth_dev->data->dev_private;\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       int rc = 0;\n> +\n> +       if (!rte_eth_dev_is_valid_port(port_id)) {\n> +               DP_ERR(edev, \"port %u invalid port ID\", port_id);\n> +               return -ENODEV;\n> +       }\n> +\n> +       memset(&regs, 0, sizeof(regs));\n> +       regs.length = qede_get_regs_len(qdev);\n> +       regs.data = OSAL_ZALLOC(eth_dev, GFP_KERNEL, regs.length);\n> +       if (regs.data) {\n> +               qede_get_regs(eth_dev, &regs);\n> +               qede_set_fw_dump_file_name(qdev);\n> +               rc = qede_write_fwdump(qdev->dump_file, regs.data, regs.length);\n> +               if (!rc)\n> +                       DP_NOTICE(edev, false, \"FW dump written to %s file\\n\",\n> +                                 qdev->dump_file);\n> +               OSAL_FREE(edev, regs.data);\n> +       }\n> +\n> +       return rc;\n> +}\n> --\n> 2.18.0\n>",
        "headers": {
            "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
            "Return-Path": "<dev-bounces@dpdk.org>",
            "To": "Rasesh Mody <rmody@marvell.com>",
            "X-Google-Smtp-Source": "\n ABdhPJwuI19xc7VW23njXbRTXOHOe/zo5kUO35DnaLSNKjHYbJFvzSc8yhHO8aIucY3b5lhLP4CM1SJOMhaPfTidTvs=",
            "X-Gm-Message-State": "AOAM530dLhL6NoIctzVJFfmiupcEgTAv8vdoeBYb9naBUrbJsQwGO4iH\n 3S6jAOp1VkHLN7jBIMdg/Hm4znzX459mxiBBjy4=",
            "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=mime-version:references:in-reply-to:from:date:message-id:subject:to\n :cc:content-transfer-encoding;\n bh=thWShymiksrw3AVznXGATD08LyVhMwoPz85ua2EcuRE=;\n b=CBrr900PzjrHM/h1XtRIq91lYnWe8MMzqTOpImoEPWF5E1e1vdjf4sY9nSVbwex3xT\n 3hjWbu52XA3UtFDXj0EKY7RmLnWOTHso1bQRVhq81j7AYMoVoDrcw48LBNinXnAMJyAz\n e7nHLDv94LXnDdJydcpvSVpTTI75rOBamwuhl6VlWiAhLsJhr2bRZVmwMRWSbS538DPo\n A7QOhxUajYaqz0RNN8vgvI5AZOc17FVoEskKpHNztsbSxBEp7xH1R25Tu7Nr+I09JpXq\n 7/BwoWaNEQDVmu98xHsTacVhf6wVeCbIb+95cF1IdZd5/A6dzTSmshFGY0cQzbHIyHCh\n HRRQ==",
            "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
            "Message-ID": "\n <CALBAE1N4mM4BNDzWv1hu7NOYRObzt=VYOPCf_=4=wNz15KHyLg@mail.gmail.com>",
            "X-BeenThere": "dev@dpdk.org",
            "Received": [
                "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AC0D3A0529;\n\tThu,  9 Jul 2020 12:11:34 +0200 (CEST)",
                "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 87ABB1DA7B;\n\tThu,  9 Jul 2020 12:11:34 +0200 (CEST)",
                "from mail-il1-f196.google.com (mail-il1-f196.google.com\n [209.85.166.196]) by dpdk.org (Postfix) with ESMTP id 22DD41DA64\n for <dev@dpdk.org>; Thu,  9 Jul 2020 12:11:33 +0200 (CEST)",
                "by mail-il1-f196.google.com with SMTP id a6so1504840ilq.13\n for <dev@dpdk.org>; Thu, 09 Jul 2020 03:11:33 -0700 (PDT)"
            ],
            "Subject": "Re: [dpdk-dev] [PATCH v5 4/4] net/qede: add support for get\n\tregister operation",
            "Cc": "Jerin Jacob <jerinj@marvell.com>, Ferruh Yigit <ferruh.yigit@intel.com>,\n dpdk-dev <dev@dpdk.org>,\n GR-Everest-DPDK-Dev <GR-Everest-DPDK-Dev@marvell.com>,\n Igor Russkikh <irusskikh@marvell.com>",
            "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
            "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
            "List-Post": "<mailto:dev@dpdk.org>",
            "In-Reply-To": "<20200708225054.19665-5-rmody@marvell.com>",
            "Precedence": "list",
            "From": "Jerin Jacob <jerinjacobk@gmail.com>",
            "X-Received": "by 2002:a92:d206:: with SMTP id y6mr25156532ily.162.1594289492167;\n Thu, 09 Jul 2020 03:11:32 -0700 (PDT)",
            "Content-Transfer-Encoding": "quoted-printable",
            "MIME-Version": "1.0",
            "References": "<20200707211617.4408-1-rmody@marvell.com>\n <20200708225054.19665-5-rmody@marvell.com>",
            "X-Original-To": "patchwork@inbox.dpdk.org",
            "Sender": "\"dev\" <dev-bounces@dpdk.org>",
            "Errors-To": "dev-bounces@dpdk.org",
            "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
            "Content-Type": "text/plain; charset=\"UTF-8\"",
            "Delivered-To": "patchwork@inbox.dpdk.org",
            "Date": "Thu, 9 Jul 2020 15:41:15 +0530",
            "X-Mailman-Version": "2.1.15",
            "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:mime-version:references:in-reply-to:from:date\n :message-id:subject:to:cc:content-transfer-encoding;\n bh=thWShymiksrw3AVznXGATD08LyVhMwoPz85ua2EcuRE=;\n b=e2KN2YrBp/+5C8ovhBPRrsTiV4v+fkUu9P8Yq27menvZVeyWIV5PhD1tqZ7vNMQ3bl\n T0kstlcCDUigDXfX36nua2x1lS1JK/g8lV8m5RQBXhMHqQ6hpe0rr3EzD5+kJAey96i/\n 54SW+hUcy9sr7p78kktTDNiWJYZQzR6DQkYXUwhKtIM/wiNiU7zlCKv0TyGEPme+KecN\n OxZJyQEb0WlPEuppEj1lNxtv//LDOR+way66YIUZ4AXft5sqiNkVe0CLPkwRby42F27s\n Ie2Ozrp8Z5LFZPgkX4tP0tk94UmS6kpL01FcJ68x9ed4pCoe5wXaDxiCUhQdXOuOWG8a\n /kAg=="
        }
    },
    {
        "id": 115650,
        "web_url": "https://patches.dpdk.org/comment/115650/",
        "msgid": "<2455e6fb-4e2a-4531-90dc-5b9b802d8370@intel.com>",
        "date": "2020-07-09T16:32:42",
        "subject": "Re: [dpdk-dev] [PATCH v5 4/4] net/qede: add support for get\n\tregister operation",
        "submitter": {
            "id": 324,
            "url": "https://patches.dpdk.org/api/people/324/",
            "name": "Ferruh Yigit",
            "email": "ferruh.yigit@intel.com"
        },
        "content": "On 7/8/2020 11:50 PM, Rasesh Mody wrote:\n> Add support for .get_reg eth_dev ops which will be used to collect the\n> firmware debug data.\n> \n> PMD on detecting on some HW errors will collect the FW/HW Dump to a\n> buffer and then it will save it to a file implemented in\n> qede_save_fw_dump().\n> \n> Dump file location and name:\n> Location: <RTE_SDK> or DPDK root\n> Name: qede_pmd_dump_mm-dd-yy_hh-mm-ss.bin\n> \n> DPDK applications can initiate a debug data collection by invoking DPDK\n> library’s rte_eth_dev_get_reg_info() API. This API invokes .get_reg()\n> interface in the PMD.\n> \n> PMD implementation of .get_reg() collects the FW/HW Dump, saves it to\n> data field of rte_dev_reg_info and passes it to the application. It’s\n> the responsibility of the application to save the FW/HW Dump to a file.\n> We recommendation using the file name format used by qede_save_fw_dump().\n> \n> Signed-off-by: Rasesh Mody <rmody@marvell.com>\n> Signed-off-by: Igor Russkikh \n\n<...>\n\n> +static int\n> +qede_write_fwdump(const char *dump_file, void *dump, size_t len)\n> +{\n> +\tint err = 0;\n> +\tFILE *f;\n> +\tsize_t bytes;\n> +\n> +\tf = fopen(dump_file, \"wb+\");\n> +\n> +\tif (!f) {\n> +\t\tfprintf(stderr, \"Can't open file %s: %s\\n\",\n> +\t\t\tdump_file, strerror(errno));\n> +\t\treturn 1;\n> +\t}\n> +\tbytes = fwrite(dump, 1, len, f);\n> +\tif (bytes != len) {\n> +\t\tfprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n> +\t\t\tbytes, len);\n\nTravis is giving build error on this for 32 bits [1], fixing while merging by\nreplacing '%ld' -> '%zd', please double check in next-net.\n\n[1]\n../drivers/net/qede/qede_regs.c: In function ‘qede_write_fwdump’:\n../drivers/net/qede/qede_regs.c:229:59: error: format ‘%ld’ expects argument of\ntype ‘long int’, but argument 3 has type ‘size_t {aka unsigned int}’\n[-Werror=format=]\n   fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n                                                         ~~^\n                                                         %d\n../drivers/net/qede/qede_regs.c:229:67: error: format ‘%ld’ expects argument of\ntype ‘long int’, but argument 4 has type ‘size_t {aka unsigned int}’\n[-Werror=format=]\n   fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n                                                                 ~~^\n                                                                 %d",
        "headers": {
            "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
            "Return-Path": "<dev-bounces@dpdk.org>",
            "Content-Language": "en-US",
            "IronPort-SDR": [
                "\n tqP2NNrz/fV5/tyKgCOIY0gmlHL/ePTa4i0tMC7HW0W248CLy19vUZMX/Gqu549xTdfbYhIFil\n j6RJXk9Ii+Jg==",
                "\n gMDQCqQ/55J2iXwk04Fg7OvOkT+ljUZIEdOr6IPHxWLmunlsaeWQ2JTVSu0smrKsYNk35AOtT1\n j0FDcERxvj1A=="
            ],
            "To": "Rasesh Mody <rmody@marvell.com>, jerinj@marvell.com",
            "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
            "Message-ID": "<2455e6fb-4e2a-4531-90dc-5b9b802d8370@intel.com>",
            "Subject": "Re: [dpdk-dev] [PATCH v5 4/4] net/qede: add support for get\n\tregister operation",
            "X-BeenThere": "dev@dpdk.org",
            "X-Amp-File-Uploaded": "False",
            "Received": [
                "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5042BA0529;\n\tThu,  9 Jul 2020 18:32:50 +0200 (CEST)",
                "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0AFB51E913;\n\tThu,  9 Jul 2020 18:32:49 +0200 (CEST)",
                "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id CB0421E8E0\n for <dev@dpdk.org>; Thu,  9 Jul 2020 18:32:46 +0200 (CEST)",
                "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jul 2020 09:32:44 -0700",
                "from fyigit-mobl.ger.corp.intel.com (HELO [10.213.206.164])\n ([10.213.206.164])\n by orsmga004.jf.intel.com with ESMTP; 09 Jul 2020 09:32:43 -0700"
            ],
            "In-Reply-To": "<20200708225054.19665-5-rmody@marvell.com>",
            "Autocrypt": "addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata=\n mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy\n qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ\n +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9\n GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb\n +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF\n YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy\n ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX\n CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1\n 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz\n cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln\n aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJsBBMBCgBWAhsDAh4BAheABQsJCAcDBRUK\n CQgLBRYCAwEABQkKqZZ8FiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl6ha3sXGHZrczovL2tl\n eXMub3BlbnBncC5vcmcACgkQ+TPrQ98TYR8uLA//QwltuFliUWe60xwmu9sY38c1DXvX67wk\n UryQ1WijVdIoj4H8cf/s2KtyIBjc89R254KMEfJDao/LrXqJ69KyGKXFhFPlF3VmFLsN4XiT\n PSfxkx8s6kHVaB3O183p4xAqnnl/ql8nJ5ph9HuwdL8CyO5/7dC/MjZ/mc4NGq5O9zk3YRGO\n lvdZAp5HW9VKW4iynvy7rl3tKyEqaAE62MbGyfJDH3C/nV/4+mPc8Av5rRH2hV+DBQourwuC\n ci6noiDP6GCNQqTh1FHYvXaN4GPMHD9DX6LtT8Fc5mL/V9i9kEVikPohlI0WJqhE+vQHFzR2\n 1q5nznE+pweYsBi3LXIMYpmha9oJh03dJOdKAEhkfBr6n8BWkWQMMiwfdzg20JX0o7a/iF8H\n 4dshBs+dXdIKzPfJhMjHxLDFNPNH8zRQkB02JceY9ESEah3wAbzTwz+e/9qQ5OyDTQjKkVOo\n cxC2U7CqeNt0JZi0tmuzIWrfxjAUulVhBmnceqyMOzGpSCQIkvalb6+eXsC9V1DZ4zsHZ2Mx\n Hi+7pCksdraXUhKdg5bOVCt8XFmx1MX4AoV3GWy6mZ4eMMvJN2hjXcrreQgG25BdCdcxKgqp\n e9cMbCtF+RZax8U6LkAWueJJ1QXrav1Jk5SnG8/5xANQoBQKGz+yFiWcgEs9Tpxth15o2v59\n gXK5Ag0EV9ZMvgEQAKc0Db17xNqtSwEvmfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ES\n YpV8QWj0xK4YM0dLxnDU2IYxjEshSB1TqAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4Ai\n bPtrHuIXWQOBECcVZTTOdZYGAzaYzxiAONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxD\n UQljeNvKYt1lZE/gAUUxNLWsYyTT+22/vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/\n 3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35piVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVj\n sM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQI3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdc\n q9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYHfVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH7\n 1PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZqw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFB\n VOQOxCvwRG2QCgcJ/UTn5vlivul+cThi6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI\n 8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJlRr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYC\n GwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNhHwUCXqFrngUJCKxSYAAKCRD5M+tD3xNhH3YWD/9b\n cUiWaHJasX+OpiuZ1Li5GG3m9aw4lR/k2lET0UPRer2Jy1JsL+uqzdkxGvPqzFTBXgx/6Byz\n EMa2mt6R9BCyR286s3lxVS5Bgr5JGB3EkpPcoJT3A7QOYMV95jBiiJTy78Qdzi5LrIu4tW6H\n o0MWUjpjdbR01cnj6EagKrDx9kAsqQTfvz4ff5JIFyKSKEHQMaz1YGHyCWhsTwqONhs0G7V2\n 0taQS1bGiaWND0dIBJ/u0pU998XZhmMzn765H+/MqXsyDXwoHv1rcaX/kcZIcN3sLUVcbdxA\n WHXOktGTQemQfEpCNuf2jeeJlp8sHmAQmV3dLS1R49h0q7hH4qOPEIvXjQebJGs5W7s2vxbA\n 5u5nLujmMkkfg1XHsds0u7Zdp2n200VC4GQf8vsUp6CSMgjedHeF9zKv1W4lYXpHp576ZV7T\n GgsEsvveAE1xvHnpV9d7ZehPuZfYlP4qgo2iutA1c0AXZLn5LPcDBgZ+KQZTzm05RU1gkx7n\n gL9CdTzVrYFy7Y5R+TrE9HFUnsaXaGsJwOB/emByGPQEKrupz8CZFi9pkqPuAPwjN6Wonokv\n ChAewHXPUadcJmCTj78Oeg9uXR6yjpxyFjx3vdijQIYgi5TEGpeTQBymLANOYxYWYOjXk+ae\n dYuOYKR9nbPv+2zK9pwwQ2NXbUBystaGyQ==",
            "X-Amp-Result": "SKIPPED(no attachment in message)",
            "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
            "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
            "List-Post": "<mailto:dev@dpdk.org>",
            "Cc": "dev@dpdk.org, GR-Everest-DPDK-Dev@marvell.com,\n Igor Russkikh <irusskikh@marvell.com>",
            "Precedence": "list",
            "X-ExtLoop1": "1",
            "From": "Ferruh Yigit <ferruh.yigit@intel.com>",
            "Content-Transfer-Encoding": "8bit",
            "MIME-Version": "1.0",
            "X-IronPort-AV": [
                "E=McAfee;i=\"6000,8403,9677\"; a=\"128104117\"",
                "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"128104117\"",
                "E=Sophos;i=\"5.75,331,1589266800\"; d=\"scan'208\";a=\"428271294\""
            ],
            "References": "<20200707211617.4408-1-rmody@marvell.com>\n <20200708225054.19665-5-rmody@marvell.com>",
            "X-Original-To": "patchwork@inbox.dpdk.org",
            "Sender": "\"dev\" <dev-bounces@dpdk.org>",
            "Errors-To": "dev-bounces@dpdk.org",
            "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
            "Content-Type": "text/plain; charset=utf-8",
            "Delivered-To": "patchwork@inbox.dpdk.org",
            "Date": "Thu, 9 Jul 2020 17:32:42 +0100",
            "X-Mailman-Version": "2.1.15"
        }
    },
    {
        "id": 115658,
        "web_url": "https://patches.dpdk.org/comment/115658/",
        "msgid": "<BYAPR18MB28383214242F88858501376CB5640@BYAPR18MB2838.namprd18.prod.outlook.com>",
        "date": "2020-07-09T23:30:08",
        "subject": "Re: [dpdk-dev] [EXT] Re: [PATCH v5 4/4] net/qede: add support for\n get register operation",
        "submitter": {
            "id": 1211,
            "url": "https://patches.dpdk.org/api/people/1211/",
            "name": "Rasesh Mody",
            "email": "rmody@marvell.com"
        },
        "content": ">From: Ferruh Yigit <ferruh.yigit@intel.com>\n>Sent: Thursday, July 09, 2020 9:33 AM\n>\n>On 7/8/2020 11:50 PM, Rasesh Mody wrote:\n>> Add support for .get_reg eth_dev ops which will be used to collect the\n>> firmware debug data.\n>>\n>> PMD on detecting on some HW errors will collect the FW/HW Dump to a\n>> buffer and then it will save it to a file implemented in\n>> qede_save_fw_dump().\n>>\n>> Dump file location and name:\n>> Location: <RTE_SDK> or DPDK root\n>> Name: qede_pmd_dump_mm-dd-yy_hh-mm-ss.bin\n>>\n>> DPDK applications can initiate a debug data collection by invoking\n>> DPDK library’s rte_eth_dev_get_reg_info() API. This API invokes\n>> .get_reg() interface in the PMD.\n>>\n>> PMD implementation of .get_reg() collects the FW/HW Dump, saves it to\n>> data field of rte_dev_reg_info and passes it to the application. It’s\n>> the responsibility of the application to save the FW/HW Dump to a file.\n>> We recommendation using the file name format used by\n>qede_save_fw_dump().\n>>\n>> Signed-off-by: Rasesh Mody <rmody@marvell.com>\n>> Signed-off-by: Igor Russkikh \n>\n><...>\n>\n>> +static int\n>> +qede_write_fwdump(const char *dump_file, void *dump, size_t len) {\n>> +\tint err = 0;\n>> +\tFILE *f;\n>> +\tsize_t bytes;\n>> +\n>> +\tf = fopen(dump_file, \"wb+\");\n>> +\n>> +\tif (!f) {\n>> +\t\tfprintf(stderr, \"Can't open file %s: %s\\n\",\n>> +\t\t\tdump_file, strerror(errno));\n>> +\t\treturn 1;\n>> +\t}\n>> +\tbytes = fwrite(dump, 1, len, f);\n>> +\tif (bytes != len) {\n>> +\t\tfprintf(stderr, \"Can not write all of dump data bytes=%ld\n>len=%ld\\n\",\n>> +\t\t\tbytes, len);\n>\n>Travis is giving build error on this for 32 bits [1], fixing while merging by\n>replacing '%ld' -> '%zd', please double check in next-net.\n>\n\nThanks Ferruh, change looks good.\n\n>[1]\n>../drivers/net/qede/qede_regs.c: In function ‘qede_write_fwdump’:\n>../drivers/net/qede/qede_regs.c:229:59: error: format ‘%ld’ expects\n>argument of type ‘long int’, but argument 3 has type ‘size_t {aka unsigned\n>int}’\n>[-Werror=format=]\n>   fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n>                                                         ~~^\n>                                                         %d\n>../drivers/net/qede/qede_regs.c:229:67: error: format ‘%ld’ expects\n>argument of type ‘long int’, but argument 4 has type ‘size_t {aka unsigned\n>int}’\n>[-Werror=format=]\n>   fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n>                                                                 ~~^\n>                                                                 %d",
        "headers": {
            "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED",
            "Return-Path": "<dev-bounces@dpdk.org>",
            "x-ms-office365-filtering-correlation-id": "85181356-e75e-41a1-4096-08d82460046c",
            "x-forefront-prvs": "04599F3534",
            "X-BeenThere": "dev@dpdk.org",
            "x-ms-exchange-antispam-messagedata": "\n uFgIurWSxyoCG/9psIGnpymCASNUrrE32WQaLzqVc71YYvF3KbXFlPiK7kh/PC/lhiF/T3Tp9dk2JnOkLzPUGYUeXLRwh6HtRafrkdBl9xGKPNrG+S6HjqcS0vSqhrNVkDfNfizM2GSp2g7abkpeKpzHbsmzFkWgu6byfQSTGMTr+mLbywDpuZZOsNVJTkmtbi0IMQvnD0duoiX8lp161ACioCfZ8T3EvkGzTuNJqBs9auSfJ/zTFd8b9hP7HZCzVyctTdMELN3Pb1VYDAzTFETf2Dpdx34w57JZa/FqTbFnP31LSdfqwlIsFZpYg6fowcsnYcCr+I0h0vqQN4H7pZPV2XNewyV4HA1VByL+3vB62/GHxIYhQ/oGt84kyIBpERGGBeRLmxJEXw+zdxmX+TDlbDttKwoffFGqUsQguPnY4M8UcjTNKLkRX7JovL/RLmmKwh4t3o3QjhhWKguV7CZV2T8eNvSKKQTv+0+/nhk=",
            "X-MS-Exchange-CrossTenant-originalarrivaltime": "09 Jul 2020 23:30:08.0879 (UTC)",
            "Message-ID": "\n <BYAPR18MB28383214242F88858501376CB5640@BYAPR18MB2838.namprd18.prod.outlook.com>",
            "x-ms-oob-tlc-oobclassifiers": "OLM:2201;",
            "x-originating-ip": "[71.202.22.43]",
            "Received": [
                "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E8207A052A;\n\tFri, 10 Jul 2020 01:30:14 +0200 (CEST)",
                "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1BB2B1DAC3;\n\tFri, 10 Jul 2020 01:30:14 +0200 (CEST)",
                "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 2ABBE1DAC3\n for <dev@dpdk.org>; Fri, 10 Jul 2020 01:30:12 +0200 (CEST)",
                "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 069NJjfJ014901; Thu, 9 Jul 2020 16:30:11 -0700",
                "from sc-exch04.marvell.com ([199.233.58.184])\n by mx0b-0016f401.pphosted.com with ESMTP id 325jyv5rx5-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 09 Jul 2020 16:30:10 -0700",
                "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 9 Jul\n 2020 16:30:10 -0700",
                "from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.170)\n by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2 via Frontend Transport; Thu, 9 Jul 2020 16:30:09 -0700",
                "from BYAPR18MB2838.namprd18.prod.outlook.com (2603:10b6:a03:10a::18)\n by BYAPR18MB2773.namprd18.prod.outlook.com (2603:10b6:a03:106::32)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3153.20; Thu, 9 Jul\n 2020 23:30:08 +0000",
                "from BYAPR18MB2838.namprd18.prod.outlook.com\n ([fe80::e0bf:5227:7fd0:8eb8]) by BYAPR18MB2838.namprd18.prod.outlook.com\n ([fe80::e0bf:5227:7fd0:8eb8%4]) with mapi id 15.20.3174.022; Thu, 9 Jul 2020\n 23:30:08 +0000"
            ],
            "X-MS-Exchange-CrossTenant-userprincipalname": "\n sAdvua8DAM6yVaWGecCWycnrasgrXzDGMmgLC9zeZtcI5tt6EqyqPDFGbMlaKdLEjmp6ZmKf1xKll1ayiU6r3Q==",
            "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
            "user-agent": "Microsoft-MacOutlook/16.37.20051002",
            "List-Post": "<mailto:dev@dpdk.org>",
            "x-forefront-antispam-report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:BYAPR18MB2838.namprd18.prod.outlook.com; PTR:; CAT:NONE;\n SFTY:;\n SFS:(4636009)(396003)(376002)(346002)(39860400002)(366004)(136003)(107886003)(316002)(110136005)(9686003)(71200400001)(2906002)(5660300002)(33656002)(55016002)(54906003)(26005)(7696005)(8676002)(4326008)(66946007)(186003)(86362001)(6636002)(52536014)(478600001)(64756008)(66446008)(83380400001)(66556008)(76116006)(66476007)(8936002)(6506007);\n DIR:OUT; SFP:1101;",
            "X-MS-Exchange-CrossTenant-AuthAs": "Internal",
            "X-MS-Has-Attach": "",
            "MIME-Version": "1.0",
            "References": "<20200707211617.4408-1-rmody@marvell.com>\n <20200708225054.19665-5-rmody@marvell.com>\n <2455e6fb-4e2a-4531-90dc-5b9b802d8370@intel.com>",
            "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0",
            "Content-ID": "<A3145F1C94D60E4E817715B769E8E3EB@namprd18.prod.outlook.com>",
            "x-ms-traffictypediagnostic": "BYAPR18MB2773:",
            "Content-Type": "text/plain; charset=\"utf-8\"",
            "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 85181356-e75e-41a1-4096-08d82460046c",
            "X-MS-Exchange-CrossTenant-AuthSource": "BYAPR18MB2838.namprd18.prod.outlook.com",
            "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
            "Accept-Language": "en-US",
            "To": "Ferruh Yigit <ferruh.yigit@intel.com>, Jerin Jacob Kollanukkaran\n <jerinj@marvell.com>",
            "Content-Language": "en-US",
            "x-ms-exchange-senderadcheck": "1",
            "Thread-Topic": "[EXT] Re: [PATCH v5 4/4] net/qede: add support for get register\n operation",
            "x-microsoft-antispam-prvs": "\n <BYAPR18MB2773B3D8B7FE93309704D1BEB5640@BYAPR18MB2773.namprd18.prod.outlook.com>",
            "DKIM-Signature": [
                "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : references : content-type : content-id :\n content-transfer-encoding : mime-version; s=pfpt0818;\n bh=PicA8yb0Z482mzSBKcFYFuNpXxaNIOjCbucuy5ZZJlc=;\n b=GrLfyZxb4xWAy/cuDdhPCv16emihcJ6Fgn/kJGnRXc4ingHkojfnaKXas7nKDqbDQRpv\n KUdTNasL3bFzgNe6l9/uga/MAVEqmZuhOB2RW1a9wwjqtrg4in9Opg0+yvat5r23RuSE\n 5E1MiPefo5qsSx5WEglGVH0nFLFkLffPjeVnKBhg+KEGXbcBCnYxV8mF50kA1aa6+77j\n Ug4cQ4QZjohT5eZ1A/KsOSf+D5HalF1i3HMBpSJ3K52DgHv7XaJNIbRJ3MvaYseIKktX\n jvJJYR3F5xVdzH5T0S21phFj50a1PfdjjTO9bAvawj7iXAiZd+wQShbv9vugadBgDFbv ug==",
                "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=marvell.onmicrosoft.com; s=selector1-marvell-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=PicA8yb0Z482mzSBKcFYFuNpXxaNIOjCbucuy5ZZJlc=;\n b=jOhY05JZLHTtfRlLW6BdINDa9Wx+FB0J+S1Tmzn/P40Is0XSfsQUVefKRutrPZkKqY04O7gofX64Y/CaJkkHY+32tncC75IdsqHn6FponU4tBI08J6SuQ4um7GkklqVO3vthmJDkDA/3AXdiY3AH29gmO1i5MWSK6xyQ66ClAMI="
            ],
            "Thread-Index": "AQHWVXpoDaPcmt56JUCNvRGMLdgG1Kj/ci0AgABtk5A=",
            "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
            "Delivered-To": "patchwork@inbox.dpdk.org",
            "X-Mailman-Version": "2.1.15",
            "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=YsKgQUrJ+aWkQvy+O332KUtIGBj4KnMDM5qXfb3MU71kAFBpsVE5MBEQ5ZP+l996JzFwz8ImL9w20ufM1/mCjZvDRlk6whQzjh8F/L7iDcBpM//RHO5MeZDzfIkVtMtlJ3HzWwZlcSycqYNoyGYRzItBMKgqnoJ44tq8oYkoSKrPyWRnfKMvGCF81w+M+hz43eaOb0pPNIgz/8yZ6UYLH2iKrhAWCU504l6vp47j9AtzweL4PfkJkATYpKG/aw9DgJGoDpqPZOEOJcu0a3DriyYXl/kA7EOKjh13HlQpmxwXIHihkVjcxxNcZjFSQz2xe6wOrS9nsl4nmpOO8Dv52w==",
            "Subject": "Re: [dpdk-dev] [EXT] Re: [PATCH v5 4/4] net/qede: add support for\n get register operation",
            "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
            "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR18MB2773",
            "X-OriginatorOrg": "marvell.com",
            "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted",
            "X-MS-TNEF-Correlator": "",
            "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-09_11:2020-07-09,\n 2020-07-09 signatures=0",
            "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com;\n dkim=pass header.d=marvell.com; arc=none",
            "Date": "Thu, 9 Jul 2020 23:30:08 +0000",
            "Precedence": "list",
            "From": "Rasesh Mody <rmody@marvell.com>",
            "Content-Transfer-Encoding": "base64",
            "authentication-results": "intel.com; dkim=none (message not signed)\n header.d=none;intel.com; dmarc=none action=none header.from=marvell.com;",
            "x-microsoft-antispam": "BCL:0;",
            "X-Original-To": "patchwork@inbox.dpdk.org",
            "x-ms-exchange-transport-forked": "True",
            "Errors-To": "dev-bounces@dpdk.org",
            "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
            "CC": "\"dev@dpdk.org\" <dev@dpdk.org>, GR-Everest-DPDK-Dev\n <GR-Everest-DPDK-Dev@marvell.com>, Igor Russkikh <irusskikh@marvell.com>",
            "Sender": "\"dev\" <dev-bounces@dpdk.org>",
            "x-microsoft-antispam-message-info": "\n MmecssGhjMQrCKf993IxnohyVUVgueGmOYvsA9UHR4VCRuVxWDhSzyOdpvmZWnmcHOSuJtCqRyObRYOP6lEoqm20b9rG0sUwH8G1uma3wHGuQ3zAdQslkXCyxIoKUrCQ3qdG7A10Rl/zKAV9df5je0wdQMZyB3XpwTGfNBBWfR/SFjvm668EQ2t6fMFtfQX1oAoC5X9mkvLmK8lERng/ZjihwJMGs6Pi9UeL4ajO8GCwdP9H1fI9xuxQ5CuCdoZC00JufjNYw23eo2MLQ5hSjmBEQTQaN7J7T3Bd0kEQU4tX1VPluYo68NrxUuvhYfAcPx2qbNgdpIj5cJYxHuSUrQ==",
            "x-ms-publictraffictype": "Email",
            "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=PicA8yb0Z482mzSBKcFYFuNpXxaNIOjCbucuy5ZZJlc=;\n b=SqIe7dTf/d8deIIjWEmqfBb4wumX8W5h9qFFN70bgU69aCI04femErk9I3kVza6BkobOep11PKebDQKOsKvNX3y6gbHp8+/1H4ZniOWGPZ/Hywu4B7DNoCCStVVz9YKhdYf7PGZyY3kij1b1P5W5Ybz2A16jq0p88Cqa1WooheiW1jwOxTGP/qqNQQmRkbEXIr/Giq1H8RptjjL4FtoK76iCzfG8iVJPp/9+Qq91tRHRv+/j2jW6Fx2sIYnUGnLjnDjfwRB97IrwIrtmd/+EG/3K/4VxZsx3ZycImLURdlHu8KvZKueDgGWR+642rtmhAnBw1PBulUWdTfhrue16Dg=="
        }
    }
]