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{
    "id": 73558,
    "url": "https://patches.dpdk.org/api/patches/73558/",
    "web_url": "https://patches.dpdk.org/patch/73558/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200708213946.30108-3-andreyv@mellanox.com>",
    "date": "2020-07-08T21:39:41",
    "name": "[v2,2/6] common/mlx5: modify advanced Rx object via DevX",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "d6e2f887573ef51e569ea8d99d7f7d3e12e27ae9",
    "submitter": {
        "id": 1809,
        "url": "https://patches.dpdk.org/api/people/1809/",
        "name": "Andrey Vesnovaty",
        "email": "andreyv@mellanox.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@intel.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73558/mbox/",
    "series": [
        {
            "id": 10899,
            "url": "https://patches.dpdk.org/api/series/10899/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10899",
            "date": "2020-07-08T21:39:39",
            "name": "add flow shared action API + PMD",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/10899/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73558/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73558/checks/",
    "tags": {},
    "headers": {
        "X-Mailman-Version": "2.1.15",
        "Date": "Thu,  9 Jul 2020 00:39:41 +0300",
        "In-Reply-To": "<20200708213946.30108-1-andreyv@mellanox.com>",
        "Errors-To": "dev-bounces@dpdk.org",
        "X-Mailer": "git-send-email 2.26.2",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8E5F2A0526;\n\tWed,  8 Jul 2020 23:40:31 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5C2691E53D;\n\tWed,  8 Jul 2020 23:40:05 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id DD8E91E493\n for <dev@dpdk.org>; Wed,  8 Jul 2020 23:39:57 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n andreyv@mellanox.com) with SMTP; 9 Jul 2020 00:39:54 +0300",
            "from r-arch-host11.mtr.labs.mlnx. (r-arch-host11.mtr.labs.mlnx\n [10.213.43.60])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 068LdrB3032740;\n Thu, 9 Jul 2020 00:39:53 +0300"
        ],
        "References": "<20200702120511.16315-1-andreyv@mellanox.com>\n <20200708213946.30108-1-andreyv@mellanox.com>",
        "MIME-Version": "1.0",
        "Message-Id": "<20200708213946.30108-3-andreyv@mellanox.com>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "From": "Andrey Vesnovaty <andreyv@mellanox.com>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "To": "dev@dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-BeenThere": "dev@dpdk.org",
        "Content-Transfer-Encoding": "8bit",
        "Cc": "jer@marvell.com, jerinjacobk@gmail.com, thomas@monjalon.net,\n ferruh.yigit@intel.com, stephen@networkplumber.org,\n bruce.richardson@intel.com, orika@mellanox.com,\n viacheslavo@mellanox.com, andrey.vesnovaty@gmail.com,\n Matan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>,\n Ray Kinsella <mdr@ashroe.eu>, Neil Horman <nhorman@tuxdriver.com>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Subject": "[dpdk-dev] [PATCH v2 2/6] common/mlx5: modify advanced Rx object\n\tvia DevX"
    },
    "content": "Implement mlx5_devx_cmd_modify_tir() to modify TIR object using DevX\nAPI.\nAdd related structs in mlx5_prm.h.\n\nSigned-off-by: Andrey Vesnovaty <andreyv@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c          | 84 +++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h          | 10 +++\n drivers/common/mlx5/mlx5_prm.h                | 29 +++++++\n .../common/mlx5/rte_common_mlx5_version.map   |  1 +\n 4 files changed, 124 insertions(+)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 2179a83983..2a7098ec6d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -825,6 +825,90 @@ mlx5_devx_cmd_create_tir(void *ctx,\n \treturn tir;\n }\n \n+/**\n+ * Modify TIR using DevX API.\n+ *\n+ * @param[in] tir\n+ *   Pointer to TIR DevX object structure.\n+ * @param [in] modify_tir_attr\n+ *   Pointer to TIR modification attributes structure.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,\n+\t\t\t struct mlx5_devx_modify_tir_attr *modify_tir_attr)\n+{\n+\tstruct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;\n+\tuint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};\n+\tvoid *tir_ctx;\n+\tint ret;\n+\n+\tMLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);\n+\tMLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);\n+\tMLX5_SET64(modify_tir_in, in, modify_bitmask,\n+\t\tmodify_tir_attr->modify_bitmask);\n+\n+\ttir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);\n+\tif (modify_tir_attr->modify_bitmask &\n+\t\t\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {\n+\t\tMLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,\n+\t\t\t tir_attr->lro_timeout_period_usecs);\n+\t\tMLX5_SET(tirc, tir_ctx, lro_enable_mask,\n+\t\t\t tir_attr->lro_enable_mask);\n+\t\tMLX5_SET(tirc, tir_ctx, lro_max_msg_sz,\n+\t\t\t tir_attr->lro_max_msg_sz);\n+\t}\n+\tif (modify_tir_attr->modify_bitmask &\n+\t\t\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)\n+\t\tMLX5_SET(tirc, tir_ctx, indirect_table,\n+\t\t\t tir_attr->indirect_table);\n+\tif (modify_tir_attr->modify_bitmask &\n+\t\t\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {\n+\t\tint i;\n+\t\tvoid *outer, *inner;\n+\t\tMLX5_SET(tirc, tir_ctx, rx_hash_symmetric,\n+\t\t\ttir_attr->rx_hash_symmetric);\n+\t\tMLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);\n+\t\tfor (i = 0; i < 10; i++) {\n+\t\t\tMLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],\n+\t\t\t\t tir_attr->rx_hash_toeplitz_key[i]);\n+\t\t}\n+\t\touter = MLX5_ADDR_OF(tirc, tir_ctx,\n+\t\t\t\t     rx_hash_field_selector_outer);\n+\t\tMLX5_SET(rx_hash_field_select, outer, l3_prot_type,\n+\t\t\t tir_attr->rx_hash_field_selector_outer.l3_prot_type);\n+\t\tMLX5_SET(rx_hash_field_select, outer, l4_prot_type,\n+\t\t\t tir_attr->rx_hash_field_selector_outer.l4_prot_type);\n+\t\tMLX5_SET\n+\t\t(rx_hash_field_select, outer, selected_fields,\n+\t\t tir_attr->rx_hash_field_selector_outer.selected_fields);\n+\t\tinner = MLX5_ADDR_OF(tirc, tir_ctx,\n+\t\t\t\t     rx_hash_field_selector_inner);\n+\t\tMLX5_SET(rx_hash_field_select, inner, l3_prot_type,\n+\t\t\t tir_attr->rx_hash_field_selector_inner.l3_prot_type);\n+\t\tMLX5_SET(rx_hash_field_select, inner, l4_prot_type,\n+\t\t\t tir_attr->rx_hash_field_selector_inner.l4_prot_type);\n+\t\tMLX5_SET\n+\t\t(rx_hash_field_select, inner, selected_fields,\n+\t\t tir_attr->rx_hash_field_selector_inner.selected_fields);\n+\t}\n+\tif (modify_tir_attr->modify_bitmask &\n+\t    MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {\n+\t\tMLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);\n+\t}\n+\tret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to modify TIR using DevX\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\treturn ret;\n+}\n+\n /**\n  * Create RQT using DevX API.\n  *\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 25704efc1f..9b07b39e66 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -178,6 +178,13 @@ struct mlx5_devx_tir_attr {\n \tstruct mlx5_rx_hash_field_select rx_hash_field_selector_inner;\n };\n \n+/* TIR attributes structure, used by TIR modify */\n+struct mlx5_devx_modify_tir_attr {\n+\tuint32_t tirn:24;\n+\tuint64_t modify_bitmask;\n+\tstruct mlx5_devx_tir_attr tir;\n+};\n+\n /* RQT attributes structure, used by RQT operations. */\n struct mlx5_devx_rqt_attr {\n \tuint8_t rq_type;\n@@ -372,6 +379,9 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,\n __rte_internal\n int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,\n \t\t\t     struct mlx5_devx_rqt_attr *rqt_attr);\n+__rte_internal\n+int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,\n+\t\t\t     struct mlx5_devx_modify_tir_attr *tir_attr);\n \n /**\n  * Create virtio queue counters object DevX API.\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c63795fc84..029767ea34 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -746,6 +746,7 @@ enum {\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n \tMLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,\n \tMLX5_CMD_OP_CREATE_TIR = 0x900,\n+\tMLX5_CMD_OP_MODIFY_TIR = 0x901,\n \tMLX5_CMD_OP_CREATE_SQ = 0X904,\n \tMLX5_CMD_OP_MODIFY_SQ = 0X905,\n \tMLX5_CMD_OP_CREATE_RQ = 0x908,\n@@ -1753,6 +1754,34 @@ struct mlx5_ifc_create_tir_in_bits {\n \tstruct mlx5_ifc_tirc_bits ctx;\n };\n \n+enum {\n+\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,\n+\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,\n+\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,\n+\t/* bit 3 - tunneled_offload_en modify not supported */\n+\tMLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,\n+};\n+\n+struct mlx5_ifc_modify_tir_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_modify_tir_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 tirn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 modify_bitmask[0x40];\n+\tu8 reserved_at_c0[0x40];\n+\tstruct mlx5_ifc_tirc_bits ctx;\n+};\n+\n enum {\n \tMLX5_INLINE_Q_TYPE_RQ = 0x0,\n \tMLX5_INLINE_Q_TYPE_VIRTQ = 0x1,\ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex ae57ebdba5..0bfedab32f 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -29,6 +29,7 @@ INTERNAL {\n \tmlx5_devx_cmd_modify_rq;\n \tmlx5_devx_cmd_modify_rqt;\n \tmlx5_devx_cmd_modify_sq;\n+\tmlx5_devx_cmd_modify_tir;\n \tmlx5_devx_cmd_modify_virtq;\n \tmlx5_devx_cmd_qp_query_tis_td;\n \tmlx5_devx_cmd_query_hca_attr;\n",
    "prefixes": [
        "v2",
        "2/6"
    ]
}