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{
    "id": 73554,
    "url": "https://patches.dpdk.org/api/patches/73554/",
    "web_url": "https://patches.dpdk.org/patch/73554/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200708213946.30108-4-andreyv@mellanox.com>",
    "date": "2020-07-08T21:39:42",
    "name": "[v2,3/6] net/mlx5: modify hash Rx queue objects",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "3f38955343297c8a3704994012af199b40e9137c",
    "submitter": {
        "id": 1809,
        "url": "https://patches.dpdk.org/api/people/1809/",
        "name": "Andrey Vesnovaty",
        "email": "andreyv@mellanox.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@intel.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73554/mbox/",
    "series": [
        {
            "id": 10777,
            "url": "https://patches.dpdk.org/api/series/10777/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10777",
            "date": "2020-07-02T12:05:10",
            "name": "add flow shared action API",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/10777/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73554/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73554/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Message-Id": "<20200708213946.30108-4-andreyv@mellanox.com>",
        "X-Mailer": "git-send-email 2.26.2",
        "To": "dev@dpdk.org",
        "Cc": "jer@marvell.com, jerinjacobk@gmail.com, thomas@monjalon.net,\n ferruh.yigit@intel.com, stephen@networkplumber.org,\n bruce.richardson@intel.com, orika@mellanox.com,\n viacheslavo@mellanox.com, andrey.vesnovaty@gmail.com,\n Matan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 756B2A0526;\n\tWed,  8 Jul 2020 23:39:59 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DC6821DFED;\n\tWed,  8 Jul 2020 23:39:58 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id CEE1D1DFEF\n for <dev@dpdk.org>; Wed,  8 Jul 2020 23:39:57 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n andreyv@mellanox.com) with SMTP; 9 Jul 2020 00:39:54 +0300",
            "from r-arch-host11.mtr.labs.mlnx. (r-arch-host11.mtr.labs.mlnx\n [10.213.43.60])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 068LdrB4032740;\n Thu, 9 Jul 2020 00:39:54 +0300"
        ],
        "Subject": "[dpdk-dev] [PATCH v2 3/6] net/mlx5: modify hash Rx queue objects",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "In-Reply-To": "<20200708213946.30108-1-andreyv@mellanox.com>",
        "Precedence": "list",
        "From": "Andrey Vesnovaty <andreyv@mellanox.com>",
        "Content-Transfer-Encoding": "8bit",
        "MIME-Version": "1.0",
        "References": "<20200702120511.16315-1-andreyv@mellanox.com>\n <20200708213946.30108-1-andreyv@mellanox.com>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Errors-To": "dev-bounces@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Date": "Thu,  9 Jul 2020 00:39:42 +0300",
        "X-Mailman-Version": "2.1.15",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>"
    },
    "content": "Implement mlx5_hrxq_modify() to modify hash RX queue object.\nThis commit relays on capability to modify TIR object via DevX.\n\nSigned-off-by: Andrey Vesnovaty <andreyv@mellanox.com>\n---\n drivers/net/mlx5/mlx5_rxq.c  | 300 ++++++++++++++++++++++++++++-------\n drivers/net/mlx5/mlx5_rxtx.h |   4 +\n 2 files changed, 243 insertions(+), 61 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b436f06107..80c402c4b7 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2274,6 +2274,29 @@ mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n \treturn NULL;\n }\n \n+/**\n+ * Match queues listed in arguments to queues contained in indirection table\n+ * object.\n+ *\n+ * @param ind_tbl\n+ *   Pointer to indirection table to match.\n+ * @param queues\n+ *   Queues to match to ques in indirection table.\n+ * @param queues_n\n+ *   Number of queues in the array.\n+ *\n+ * @return\n+ *   1 if all queues in indirection table match 0 othrwise.\n+ */\n+static int\n+mlx5_ind_table_obj_match_queues(const struct mlx5_ind_table_obj *ind_tbl,\n+\t\t       const uint16_t *queues, uint32_t queues_n)\n+{\n+\t\treturn (ind_tbl->queues_n == queues_n) &&\n+\t\t    (!memcmp(ind_tbl->queues, queues,\n+\t\t\t    ind_tbl->queues_n * sizeof(ind_tbl->queues[0])));\n+}\n+\n /**\n  * Get an indirection table.\n  *\n@@ -2370,6 +2393,102 @@ mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+/*\n+ * Set TIR attribute struct with relevant input values.\n+ *\n+ * @param[in] dev\n+ *   Pointer to Ethernet device.\n+ * @param[in] rss_key\n+ *   RSS key for the Rx hash queue.\n+ * @param[in] rss_key_len\n+ *   RSS key length.\n+ * @param[in] hash_fields\n+ *   Verbs protocol hash field to make the RSS on.\n+ * @param[in] queues\n+ *   Queues entering in hash queue. In case of empty hash_fields only the\n+ *   first queue index will be taken for the indirection table.\n+ * @param[in] queues_n\n+ *   Number of queues.\n+ * @param[in] tunnel\n+ *   Tunnel type.\n+ * @param[out] tir_attr\n+ *   Parameters structure for TIR creation/modification.\n+ *\n+ * @return\n+ *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.\n+ */\n+static void\n+mlx5_devx_tir_attr_set(struct rte_eth_dev *dev,\n+\t      const uint8_t *rss_key, uint32_t rss_key_len,\n+\t      uint64_t hash_fields,\n+\t      const uint16_t *queues, uint32_t queues_n,\n+\t      int tunnel,\n+\t      enum mlx5_rxq_obj_type rxq_obj_type, int ind_tbl_id,\n+\t      struct mlx5_devx_tir_attr *tir_attr)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint32_t i;\n+\tuint32_t lro = 1;\n+\n+\t/* Enable TIR LRO only if all the queues were configured for. */\n+\tfor (i = 0; i < queues_n; ++i) {\n+\t\tif (!(*priv->rxqs)[queues[i]]->lro) {\n+\t\t\tlro = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tmemset(tir_attr, 0, sizeof(*tir_attr));\n+\ttir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;\n+\ttir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;\n+\ttir_attr->tunneled_offload_en = !!tunnel;\n+\t/* If needed, translate hash_fields bitmap to PRM format. */\n+\tif (hash_fields) {\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n+\t\t\t\thash_fields & IBV_RX_HASH_INNER ?\n+\t\t\t\t&tir_attr->rx_hash_field_selector_inner :\n+\t\t\t\t&tir_attr->rx_hash_field_selector_outer;\n+#else\n+\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n+\t\t\t\t&tir_attr->rx_hash_field_selector_outer;\n+#endif\n+\n+\t\t/* 1 bit: 0: IPv4, 1: IPv6. */\n+\t\trx_hash_field_select->l3_prot_type =\n+\t\t\t!!(hash_fields & MLX5_IPV6_IBV_RX_HASH);\n+\t\t/* 1 bit: 0: TCP, 1: UDP. */\n+\t\trx_hash_field_select->l4_prot_type =\n+\t\t\t!!(hash_fields & MLX5_UDP_IBV_RX_HASH);\n+\t\t/* Bitmask which sets which fields to use in RX Hash. */\n+\t\trx_hash_field_select->selected_fields =\n+\t\t((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<\n+\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |\n+\t\t(!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<\n+\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |\n+\t\t(!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<\n+\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |\n+\t\t(!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<\n+\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;\n+\t}\n+\tif (rxq_obj_type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)\n+\t\ttir_attr->transport_domain = priv->sh->td->id;\n+\telse\n+\t\ttir_attr->transport_domain = priv->sh->tdn;\n+\tmemcpy(tir_attr->rx_hash_toeplitz_key, rss_key, rss_key_len);\n+\ttir_attr->indirect_table = ind_tbl_id;\n+\tif (dev->data->dev_conf.lpbk_mode)\n+\t\ttir_attr->self_lb_block =\n+\t\t\t\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n+\tif (lro) {\n+\t\ttir_attr->lro_timeout_period_usecs =\n+\t\t\t\tpriv->config.lro.timeout;\n+\t\ttir_attr->lro_max_msg_sz = priv->max_lro_msg_size;\n+\t\ttir_attr->lro_enable_mask =\n+\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |\n+\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;\n+\t}\n+}\n+\n /**\n  * Create an Rx Hash queue.\n  *\n@@ -2493,67 +2612,11 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,\n \t\t}\n \t} else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */\n \t\tstruct mlx5_devx_tir_attr tir_attr;\n-\t\tuint32_t i;\n-\t\tuint32_t lro = 1;\n-\n-\t\t/* Enable TIR LRO only if all the queues were configured for. */\n-\t\tfor (i = 0; i < queues_n; ++i) {\n-\t\t\tif (!(*priv->rxqs)[queues[i]]->lro) {\n-\t\t\t\tlro = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t\tmemset(&tir_attr, 0, sizeof(tir_attr));\n-\t\ttir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;\n-\t\ttir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;\n-\t\ttir_attr.tunneled_offload_en = !!tunnel;\n-\t\t/* If needed, translate hash_fields bitmap to PRM format. */\n-\t\tif (hash_fields) {\n-#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n-\t\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n-\t\t\t\t\thash_fields & IBV_RX_HASH_INNER ?\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_inner :\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_outer;\n-#else\n-\t\t\tstruct mlx5_rx_hash_field_select *rx_hash_field_select =\n-\t\t\t\t\t&tir_attr.rx_hash_field_selector_outer;\n-#endif\n-\n-\t\t\t/* 1 bit: 0: IPv4, 1: IPv6. */\n-\t\t\trx_hash_field_select->l3_prot_type =\n-\t\t\t\t!!(hash_fields & MLX5_IPV6_IBV_RX_HASH);\n-\t\t\t/* 1 bit: 0: TCP, 1: UDP. */\n-\t\t\trx_hash_field_select->l4_prot_type =\n-\t\t\t\t!!(hash_fields & MLX5_UDP_IBV_RX_HASH);\n-\t\t\t/* Bitmask which sets which fields to use in RX Hash. */\n-\t\t\trx_hash_field_select->selected_fields =\n-\t\t\t((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |\n-\t\t\t(!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |\n-\t\t\t(!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |\n-\t\t\t(!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<\n-\t\t\t MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;\n-\t\t}\n-\t\tif (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)\n-\t\t\ttir_attr.transport_domain = priv->sh->td->id;\n-\t\telse\n-\t\t\ttir_attr.transport_domain = priv->sh->tdn;\n-\t\tmemcpy(tir_attr.rx_hash_toeplitz_key, rss_key,\n-\t\t       MLX5_RSS_HASH_KEY_LEN);\n-\t\ttir_attr.indirect_table = ind_tbl->rqt->id;\n-\t\tif (dev->data->dev_conf.lpbk_mode)\n-\t\t\ttir_attr.self_lb_block =\n-\t\t\t\t\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n-\t\tif (lro) {\n-\t\t\ttir_attr.lro_timeout_period_usecs =\n-\t\t\t\t\tpriv->config.lro.timeout;\n-\t\t\ttir_attr.lro_max_msg_sz = priv->max_lro_msg_size;\n-\t\t\ttir_attr.lro_enable_mask =\n-\t\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |\n-\t\t\t\t\tMLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;\n-\t\t}\n+\t\tmlx5_devx_tir_attr_set\n+\t\t\t(dev, rss_key, rss_key_len, hash_fields,\n+\t\t\t queues, queues_n, tunnel,\n+\t\t\t rxq_ctrl->obj->type, ind_tbl->rqt->id,\n+\t\t\t &tir_attr);\n \t\ttir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);\n \t\tif (!tir) {\n \t\t\tDRV_LOG(ERR, \"port %u cannot create DevX TIR\",\n@@ -2616,6 +2679,7 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,\n  *   Queues entering in hash queue. In case of empty hash_fields only the\n  *   first queue index will be taken for the indirection table.\n  * @param queues_n\n+ *\n  *   Number of queues.\n  *\n  * @return\n@@ -2655,6 +2719,120 @@ mlx5_hrxq_get(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Modify an Rx Hash queue configuration.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param hrxq\n+ *   Index to Hash Rx queue to modify.\n+ * @param rss_key\n+ *   RSS key for the Rx hash queue.\n+ * @param rss_key_len\n+ *   RSS key length.\n+ * @param hash_fields\n+ *   Verbs protocol hash field to make the RSS on.\n+ * @param queues\n+ *   Queues entering in hash queue. In case of empty hash_fields only the\n+ *   first queue index will be taken for the indirection table.\n+ * @param queues_n\n+ *   Number of queues.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,\n+\t\t const uint8_t *rss_key, uint32_t rss_key_len,\n+\t\t uint64_t hash_fields,\n+\t\t const uint16_t *queues, uint32_t queues_n)\n+{\n+\tint err;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n+\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_devx_modify_tir_attr modify_tir = {0};\n+\tstruct mlx5_ind_table_obj *ind_tbl = NULL;\n+\tenum mlx5_ind_tbl_type rxq_obj_type =\n+\t\t\trxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?\n+\t\t\tMLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;\n+\tstruct mlx5_hrxq *hrxq =\n+\t\tmlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\n+\tif (!hrxq) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* validations */\n+\tif (hrxq->ind_table->type != MLX5_IND_TBL_TYPE_DEVX ||\n+\t\t\trxq_obj_type != MLX5_IND_TBL_TYPE_DEVX) {\n+\t\t/*  shared action supported by devx interface only */\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (hrxq->rss_key_len != rss_key_len) {\n+\t\t/* rss_key_len is fixed size 40 byte & not supposed to change */\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tqueues_n = hash_fields ? queues_n : 1;\n+\tif (mlx5_ind_table_obj_match_queues(hrxq->ind_table,\n+\t\t\t\t\t    queues, queues_n)) {\n+\t\tind_tbl = hrxq->ind_table;\n+\t} else {\n+\t\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n+\t\tif (!ind_tbl)\n+\t\t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n,\n+\t\t\t\t\t\t\t rxq_obj_type);\n+\t}\n+\tif (!ind_tbl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\t/*\n+\t * untested for modification fields:\n+\t * - rx_hash_symmetric not set in hrxq_new(),\n+\t * - rx_hash_fn set hard-coded in hrxq_new(),\n+\t * - lro_xxx not set after rxq setup\n+\t */\n+\tmodify_tir.modify_bitmask |=\n+\t\t(MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE &\n+\t\t!!(ind_tbl != hrxq->ind_table));\n+\tmodify_tir.modify_bitmask |=\n+\t\t(MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH &\n+\t\t!!(hash_fields != hrxq->hash_fields ||\n+\t\thrxq->rss_key_len != rss_key_len ||\n+\t\tmemcmp(hrxq->rss_key, rss_key, rss_key_len)));\n+\n+\tmlx5_devx_tir_attr_set(dev, rss_key, rss_key_len, hash_fields,\n+\t\t\t       queues, queues_n,\n+\t\t\t       0, /* N/A - tunnel modification unsupported */\n+\t\t\t       rxq_obj_type, ind_tbl->rqt->id,\n+\t\t\t       &modify_tir.tir);\n+\tif (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {\n+\t\tDRV_LOG(ERR, \"port %u cannot modify DevX TIR\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tif (ind_tbl != hrxq->ind_table) {\n+\t\tmlx5_ind_table_obj_release(dev, hrxq->ind_table);\n+\t\thrxq->ind_table = ind_tbl;\n+\t}\n+\thrxq->hash_fields = hash_fields;\n+\tmemcpy(hrxq->rss_key, rss_key, rss_key_len);\n+\treturn 0;\n+error:\n+\terr = rte_errno;\n+\tif (ind_tbl != hrxq->ind_table)\n+\t\tmlx5_ind_table_obj_release(dev, ind_tbl);\n+\trte_errno = err;\n+\treturn -rte_errno;\n+}\n+\n /**\n  * Release the hash Rx queue.\n  *\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 26621ff193..5cff28196c 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -424,6 +424,10 @@ struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);\n void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);\n uint64_t mlx5_get_rx_port_offloads(void);\n uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);\n+int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,\n+\t\t     const uint8_t *rss_key, uint32_t rss_key_len,\n+\t\t     uint64_t hash_fields,\n+\t\t     const uint16_t *queues, uint32_t queues_n);\n \n /* mlx5_txq.c */\n \n",
    "prefixes": [
        "v2",
        "3/6"
    ]
}