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GET /api/patches/73532/?format=api
{ "id": 73532, "url": "https://patches.dpdk.org/api/patches/73532/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1594219387-240274-3-git-send-email-bingz@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594219387-240274-3-git-send-email-bingz@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594219387-240274-3-git-send-email-bingz@mellanox.com", "date": "2020-07-08T14:43:04", "name": "[2/5] net/mlx5: add flow translation of eCPRI header", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "88de7792129b7634ee4b3603e2e328566add8182", "submitter": { "id": 1357, "url": "https://patches.dpdk.org/api/people/1357/?format=api", "name": "Bing Zhao", "email": "bingz@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1594219387-240274-3-git-send-email-bingz@mellanox.com/mbox/", "series": [ { "id": 10893, "url": "https://patches.dpdk.org/api/series/10893/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10893", "date": "2020-07-08T14:43:02", "name": "add eCPRI support in mlx5 driver", "version": 1, "mbox": "https://patches.dpdk.org/series/10893/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/73532/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/73532/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C062EA0527;\n\tWed, 8 Jul 2020 16:43:32 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D74F41BE98;\n\tWed, 8 Jul 2020 16:43:20 +0200 (CEST)", "from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130])\n by dpdk.org (Postfix) with ESMTP id BFC121E49D\n for <dev@dpdk.org>; Wed, 8 Jul 2020 16:43:18 +0200 (CEST)" ], "From": "Bing Zhao <bingz@mellanox.com>", "To": "orika@mellanox.com,\n\tviacheslavo@mellanox.com", "Cc": "rasland@mellanox.com,\n\tmatan@mellanox.com,\n\tdev@dpdk.org", "Date": "Wed, 8 Jul 2020 22:43:04 +0800", "Message-Id": "<1594219387-240274-3-git-send-email-bingz@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594219387-240274-1-git-send-email-bingz@mellanox.com>", "References": "<1594219387-240274-1-git-send-email-bingz@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 2/5] net/mlx5: add flow translation of eCPRI\n\theader", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In the translation stage, the eCPRI item should be translated into\nthe format that lower layer driver could use. All the fields that\nneed to matched must be in network byte order after translation, as\nwell as the mask. Since the header in the item belongs to the network\nlayers stack, and the input parameter of the header is considered to\nbe in big-endian format already.\n\nBase on the definition in the PRM, the DW samples will be used for\nmatching in the FTE/STE. Now, the type field and only the PC ID, RTC\nID, and DLY MSR ID of the payload will be supported. The masks should\nbe 00 ff 00 00 ff ff(00) 00 00 in the network order. Two DWs are\nneeded to support such matching. The mask fields could be zeros to\nsupport some wildcard rules. But it makes no sense to support the\nrule matching only on the payload but without matching type filed.\n\nThe DW samples should be stored after the flex parser creation for\neCPRI. There is no need to query the sample IDs each time when\ncreating a flow rule with eCPRI item. It will not introduce\ninsertion rate degradation significantly.\n\nSigned-off-by: Bing Zhao <bingz@mellanox.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 16 ++++-\n drivers/net/mlx5/mlx5.h | 15 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 130 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 160 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c63795f..decc63d 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -709,6 +709,18 @@ struct mlx5_ifc_fte_match_set_misc3_bits {\n \tu8 reserved_at_170[0x90];\n };\n \n+struct mlx5_ifc_fte_match_set_misc4_bits {\n+\tu8 prog_sample_field_value_0[0x20];\n+\tu8 prog_sample_field_id_0[0x20];\n+\tu8 prog_sample_field_value_1[0x20];\n+\tu8 prog_sample_field_id_1[0x20];\n+\tu8 prog_sample_field_value_2[0x20];\n+\tu8 prog_sample_field_id_2[0x20];\n+\tu8 prog_sample_field_value_3[0x20];\n+\tu8 prog_sample_field_id_3[0x20];\n+\tu8 reserved_at_100[0x100];\n+};\n+\n /* Flow matcher. */\n struct mlx5_ifc_fte_match_param_bits {\n \tstruct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;\n@@ -716,6 +728,7 @@ struct mlx5_ifc_fte_match_param_bits {\n \tstruct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;\n \tstruct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;\n \tstruct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;\n+\tstruct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;\n };\n \n enum {\n@@ -723,7 +736,8 @@ enum {\n \tMLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,\n \tMLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,\n \tMLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,\n-\tMLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT\n+\tMLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,\n+\tMLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT\n };\n \n enum {\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 46e66eb..51775ca 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -529,6 +529,19 @@ struct mlx5_flow_id_pool {\n \tuint32_t max_id; /**< Maximum id can be allocated from the pool. */\n };\n \n+/* Supported flex parser profile ID. */\n+enum mlx5_flex_parser_profile_id {\n+\tMLX5_FLEX_PARSER_ECPRI_0 = 0,\n+\tMLX5_FLEX_PARSER_MAX = 8,\n+};\n+\n+/* Sample ID information of flex parser structure. */\n+struct mlx5_flex_parser_profiles {\n+\tuint32_t ids[4];\t/* Sample IDs for this profile. */\n+\tvoid *obj;\t\t/* Flex parser node object. */\n+\tuint32_t num;\t\t/* Actual number of samples. */\n+};\n+\n /*\n * Shared Infiniband device context for Master/Representors\n * which belong to same IB device with multiple IB ports.\n@@ -579,6 +592,8 @@ struct mlx5_dev_ctx_shared {\n \tstruct mlx5_devx_obj *tis; /* TIS object. */\n \tstruct mlx5_devx_obj *td; /* Transport domain. */\n \tstruct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */\n+\tstruct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];\n+\t/* Flex parser profiles information. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 6711c79..523d778 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -4779,6 +4779,34 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t cnt, next);\n }\n \n+static inline bool\n+flow_dv_flex_parser_ecpri_exist(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_flex_parser_profiles *prf =\n+\t\t\t\t&priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];\n+\n+\treturn !!prf->obj;\n+}\n+\n+\n+static int\n+flow_dv_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_flex_parser_profiles *prf =\n+\t\t\t\t&priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];\n+\n+\treturn 0;\n+}\n+\n+static void\n+flow_dv_flex_parser_ecpri_release(struct rte_eth_dev *dev)\n+{\n+\t(void)dev;\n+\treturn;\n+}\n+\n /**\n * Verify the @p attributes will be correctly understood by the NIC and store\n * them in the @p flow if everything is correct.\n@@ -7258,6 +7286,90 @@ struct field_modify_info modify_tcp[] = {\n \t\t rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));\n }\n \n+/**\n+ * Add eCPRI item to matcher and to the value.\n+ *\n+ * @param[in] dev\n+ * The devich to configure through.\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ * @param[in] samples\n+ * Sample IDs to be used in the matching.\n+ */\n+static void\n+flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,\n+\t\t\t void *key, const struct rte_flow_item *item)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct rte_flow_item_ecpri *ecpri_m = item->mask;\n+\tconst struct rte_flow_item_ecpri *ecpri_v = item->spec;\n+\tvoid *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\t\t misc_parameters_4);\n+\tvoid *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);\n+\tuint32_t *samples;\n+\tvoid *dw_m;\n+\tvoid *dw_v;\n+\n+\tif (!ecpri_v)\n+\t\treturn;\n+\tif (!ecpri_m)\n+\t\tecpri_m = &rte_flow_item_ecpri_mask;\n+\t/*\n+\t * Maximal four DW samples are supported in a single matching now.\n+\t * Two are used now for a eCPRI matching:\n+\t * 1. Type: one byte, mask should be 0x00ff0000 in network order\n+\t * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000\n+\t * if any.\n+\t */\n+\tif (!ecpri_m->hdr.common.type)\n+\t\treturn;\n+\tsamples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;\n+\t/* Need to take the whole DW as the mask to fill the entry. */\n+\tdw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,\n+\t\t\t prog_sample_field_value_0);\n+\tdw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,\n+\t\t\t prog_sample_field_value_0);\n+\t/* Already big endian (network order) in the header. */\n+\t*(uint32_t *)dw_m = ecpri_m->hdr.dw0;\n+\t*(uint32_t *)dw_v = ecpri_v->hdr.dw0;\n+\t/* Sample#0, used for matching type, offset 0. */\n+\tMLX5_SET(fte_match_set_misc4, misc4_m,\n+\t\t prog_sample_field_id_0, samples[0]);\n+\t/* It makes no sense to set the sample ID in the mask field. */\n+\tMLX5_SET(fte_match_set_misc4, misc4_v,\n+\t\t prog_sample_field_id_0, samples[0]);\n+\t/*\n+\t * Checking if message body part needs to be matched.\n+\t * Some wildcard rules only matching type field should be supported.\n+\t */\n+\tif (ecpri_m->hdr.dummy[0]) {\n+\t\tswitch (ecpri_v->hdr.common.type) {\n+\t\tcase RTE_ECPRI_MSG_TYPE_IQ_DATA:\n+\t\tcase RTE_ECPRI_MSG_TYPE_RTC_CTRL:\n+\t\tcase RTE_ECPRI_MSG_TYPE_DLY_MSR:\n+\t\t\tdw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,\n+\t\t\t\t\t prog_sample_field_value_1);\n+\t\t\tdw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,\n+\t\t\t\t\t prog_sample_field_value_1);\n+\t\t\t*(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];\n+\t\t\t*(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];\n+\t\t\t/* Sample#1, to match message body, offset 4. */\n+\t\t\tMLX5_SET(fte_match_set_misc4, misc4_m,\n+\t\t\t\t prog_sample_field_id_1, samples[1]);\n+\t\t\tMLX5_SET(fte_match_set_misc4, misc4_v,\n+\t\t\t\t prog_sample_field_id_1, samples[1]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Others, do not match any sample ID. */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };\n \n #define HEADER_IS_ZERO(match_criteria, headers)\t\t\t\t \\\n@@ -7293,6 +7405,9 @@ struct field_modify_info modify_tcp[] = {\n \tmatch_criteria_enable |=\n \t\t(!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<\n \t\tMLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;\n+\tmatch_criteria_enable |=\n+\t\t(!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<\n+\t\tMLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;\n \treturn match_criteria_enable;\n }\n \n@@ -8572,6 +8687,21 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;\n \t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_ECPRI:\n+\t\t\tif (!flow_dv_flex_parser_ecpri_exist(dev)) {\n+\t\t\t\tret = flow_dv_flex_parser_ecpri_alloc(dev);\n+\t\t\t\tif (ret)\n+\t\t\t\t\treturn rte_flow_error_set\n+\t\t\t\t\t\t(error, ret,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\t\"cannot create eCPRI parser\");\n+\t\t\t}\n+\t\t\tflow_dv_translate_item_ecpri(dev, match_mask,\n+\t\t\t\t\t\t match_value, items);\n+\t\t\t/* No other protocol should follow eCPRI layer. */\n+\t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n", "prefixes": [ "2/5" ] }