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GET /api/patches/73531/?format=api
{ "id": 73531, "url": "https://patches.dpdk.org/api/patches/73531/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1594219387-240274-2-git-send-email-bingz@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594219387-240274-2-git-send-email-bingz@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594219387-240274-2-git-send-email-bingz@mellanox.com", "date": "2020-07-08T14:43:03", "name": "[1/5] net/mlx5: add flow validation of eCPRI header", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0b6f725537d57a69cb90115cd14558208faa9d67", "submitter": { "id": 1357, "url": "https://patches.dpdk.org/api/people/1357/?format=api", "name": "Bing Zhao", "email": "bingz@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1594219387-240274-2-git-send-email-bingz@mellanox.com/mbox/", "series": [ { "id": 10893, "url": "https://patches.dpdk.org/api/series/10893/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10893", "date": "2020-07-08T14:43:02", "name": "add eCPRI support in mlx5 driver", "version": 1, "mbox": "https://patches.dpdk.org/series/10893/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/73531/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/73531/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 05201A0527;\n\tWed, 8 Jul 2020 16:43:24 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EC9781E4A3;\n\tWed, 8 Jul 2020 16:43:17 +0200 (CEST)", "from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130])\n by dpdk.org (Postfix) with ESMTP id 201E11E49A\n for <dev@dpdk.org>; Wed, 8 Jul 2020 16:43:16 +0200 (CEST)" ], "From": "Bing Zhao <bingz@mellanox.com>", "To": "orika@mellanox.com,\n\tviacheslavo@mellanox.com", "Cc": "rasland@mellanox.com,\n\tmatan@mellanox.com,\n\tdev@dpdk.org", "Date": "Wed, 8 Jul 2020 22:43:03 +0800", "Message-Id": "<1594219387-240274-2-git-send-email-bingz@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594219387-240274-1-git-send-email-bingz@mellanox.com>", "References": "<1594219387-240274-1-git-send-email-bingz@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 1/5] net/mlx5: add flow validation of eCPRI header", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When creating a flow with eCPRI header item, the validation of it is\nmandatory. The detailed limitations are listed below:\n 1. Over Ether / VLAN, ethertype must be 0xAEFE.\n 2. No tunnel support is described in the specification now.\n 3. L3 layer is only supported when L4 is UDP, see #4.\n 4. Over TCP is not supported from the specification, and over UDP\n is not supported right now.\n 5. Concatenation indicator matching is not supported now.\n 6. No need to check the revision.\n 7. Only type field in the common header is mandatory, and one byte\n should be matched integrally.\n 8. Fields in the message payload header are optional.\n 9. Only messages with type #0, #2 and #5 are supported now.\n\nSome limitations are only from software right now, because there is\nno need to support all the message types and variants of protocol\nstack listed in the specification.\n\nSigned-off-by: Bing Zhao <bingz@mellanox.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 106 +++++++++++++++++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_flow.h | 9 ++++\n drivers/net/mlx5/mlx5_flow_dv.c | 22 +++++++++\n 3 files changed, 136 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex ae5ccc2..9309603 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1227,11 +1227,17 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,\n \t\t\t\t\t \"rss action not supported for \"\n \t\t\t\t\t \"egress\");\n-\tif (rss->level > 1 && !tunnel)\n+\tif (rss->level > 1 && !tunnel)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL,\n \t\t\t\t\t \"inner RSS is not supported for \"\n \t\t\t\t\t \"non-tunnel flows\");\n+\tif ((item_flags & MLX5_FLOW_LAYER_ECPRI) &&\n+\t !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) {\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL,\n+\t\t\t\t\t \"RSS on eCPRI is not supported now\");\n+\t}\n \treturn 0;\n }\n \n@@ -1597,6 +1603,10 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n * Item specification.\n * @param[in] item_flags\n * Bit-fields that holds the items detected until now.\n+ * @param[in] last_item\n+ * Previous validated item in the pattern items.\n+ * @param[in] ether_type\n+ * Type in the ethernet layer header (including dot1q).\n * @param[in] acc_mask\n * Acceptable mask, if NULL default internal default mask\n * will be used to check whether item fields are supported.\n@@ -1695,6 +1705,10 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n * Item specification.\n * @param[in] item_flags\n * Bit-fields that holds the items detected until now.\n+ * @param[in] last_item\n+ * Previous validated item in the pattern items.\n+ * @param[in] ether_type\n+ * Type in the ethernet layer header (including dot1q).\n * @param[in] acc_mask\n * Acceptable mask, if NULL default internal default mask\n * will be used to check whether item fields are supported.\n@@ -2357,6 +2371,96 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \treturn 0;\n }\n \n+/**\n+ * Validate eCPRI item.\n+ *\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] item_flags\n+ * Bit-fields that holds the items detected until now.\n+ * @param[in] last_item\n+ * Previous validated item in the pattern items.\n+ * @param[in] ether_type\n+ * Type in the ethernet layer header (including dot1q).\n+ * @param[in] acc_mask\n+ * Acceptable mask, if NULL default internal default mask\n+ * will be used to check whether item fields are supported.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,\n+\t\t\t uint64_t item_flags,\n+\t\t\t uint64_t last_item,\n+\t\t\t uint16_t ether_type,\n+\t\t\t const struct rte_flow_item_ecpri *acc_mask,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_ecpri *mask = item->mask;\n+\tconst struct rte_flow_item_ecpri nic_mask = {\n+\t\t.hdr = {\n+\t\t\t.dw0 = RTE_BE32(((const struct rte_ecpri_msg_hdr) {\n+\t\t\t\t\t\t.common = {\n+\t\t\t\t\t\t\t.type = 0xFF,\n+\t\t\t\t\t\t},\n+\t\t\t\t\t}).dw0),\n+\t\t\t.dummy[0] = 0xFFFFFFFF,\n+\t\t},\n+\t};\n+\tconst uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 |\n+\t\t\t\t\tMLX5_FLOW_LAYER_OUTER_VLAN);\n+\tstruct rte_flow_item_ecpri mask_lo;\n+\n+\tif ((last_item & outer_l2_vlan) && ether_type &&\n+\t ether_type != RTE_ETHER_TYPE_ECPRI)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"eCPRI cannot follow L2/VLAN layer \"\n+\t\t\t\t\t \"which ether type is not 0xAEFE.\");\n+\tif (item_flags & MLX5_FLOW_LAYER_TUNNEL)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"eCPRI with tunnel is not supported \"\n+\t\t\t\t\t \"right now.\");\n+\tif (item_flags & MLX5_FLOW_LAYER_OUTER_L3)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"multiple L3 layers not supported\");\n+\telse if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"eCPRI cannot follow a TCP layer.\");\n+\t/* In specification, eCPRI could be over UDP layer. */\n+\telse if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"eCPRI over UDP layer is not yet\"\n+\t\t\t\t\t \"supported right now.\");\n+\t/* Mask for type field in common header could be zero. */\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_ecpri_mask;\n+\tmask_lo.hdr.dw0 = rte_be_to_cpu_32(mask->hdr.dw0);\n+\t/* Input mask is in big-endian format. */\n+\tif (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask,\n+\t\t\t\t\t \"partial mask is not supported \"\n+\t\t\t\t\t \"for protocol\");\n+\telse if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask,\n+\t\t\t\t\t \"message header mask must be after \"\n+\t\t\t\t\t \"a type mask\");\n+\treturn mlx5_flow_item_acceptable(item, (const uint8_t *)mask,\n+\t\t\t\t\t acc_mask ? (const uint8_t *)acc_mask\n+\t\t\t\t\t\t : (const uint8_t *)&nic_mask,\n+\t\t\t\t\t sizeof(struct rte_flow_item_ecpri),\n+\t\t\t\t\t error);\n+}\n+\n /* Allocate unique ID for the split Q/RSS subflows. */\n static uint32_t\n flow_qrss_get_id(struct rte_eth_dev *dev)\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 43cbda8..6dfeef3 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -128,6 +128,9 @@ enum mlx5_feature_name {\n /* Pattern tunnel Layer bits (continued). */\n #define MLX5_FLOW_LAYER_GTP (1u << 28)\n \n+/* Pattern eCPRI Layer bit. */\n+#define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -1027,6 +1030,12 @@ int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error);\n+int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,\n+\t\t\t\t uint64_t item_flags,\n+\t\t\t\t uint64_t last_item,\n+\t\t\t\t uint16_t ether_type,\n+\t\t\t\t const struct rte_flow_item_ecpri *acc_mask,\n+\t\t\t\t struct rte_flow_error *error);\n struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls\n \t\t\t\t\t(struct rte_eth_dev *dev,\n \t\t\t\t\t const struct mlx5_flow_meter *fm);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 8b5b683..6711c79 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -4923,6 +4923,16 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t.hop_limits = 0xff,\n \t\t},\n \t};\n+\tconst struct rte_flow_item_ecpri nic_ecpri_mask = {\n+\t\t.hdr = {\n+\t\t\t.dw0 = RTE_BE32(((const struct rte_ecpri_msg_hdr) {\n+\t\t\t\t\t\t.common = {\n+\t\t\t\t\t\t\t.type = 0xFF,\n+\t\t\t\t\t\t},\n+\t\t\t\t\t}).dw0),\n+\t\t\t.dummy[0] = 0xffffffff,\n+\t\t},\n+\t};\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_config *dev_conf = &priv->config;\n \tuint16_t queue_index = 0xFFFF;\n@@ -5173,6 +5183,17 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_ECPRI:\n+\t\t\t/* Capacity will be checked in the translate stage. */\n+\t\t\tret = mlx5_flow_validate_item_ecpri(items, item_flags,\n+\t\t\t\t\t\t\t last_item,\n+\t\t\t\t\t\t\t ether_type,\n+\t\t\t\t\t\t\t &nic_ecpri_mask,\n+\t\t\t\t\t\t\t error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -5882,6 +5903,7 @@ struct field_modify_info modify_tcp[] = {\n \t * Set match on ethertype only if ETH header is not followed by VLAN.\n \t * HW is optimized for IPv4/IPv6. In such cases, avoid setting\n \t * ethertype, and use ip_version field instead.\n+\t * eCPRI over Ether layer will use type value 0xAEFE.\n \t */\n \tif (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&\n \t eth_m->type == 0xFFFF) {\n", "prefixes": [ "1/5" ] }