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[
    {
        "id": 115478,
        "web_url": "https://patches.dpdk.org/comment/115478/",
        "msgid": "<CALBAE1OYj+PpszVY4N-w89H_RrD+i8-1bXitdUDDHHCc+vwgvA@mail.gmail.com>",
        "date": "2020-07-08T09:29:00",
        "subject": "Re: [dpdk-dev] [PATCH v4 4/4] net/qede: add support for get\n\tregister operation",
        "submitter": {
            "id": 1270,
            "url": "https://patches.dpdk.org/api/people/1270/",
            "name": "Jerin Jacob",
            "email": "jerinjacobk@gmail.com"
        },
        "content": "On Wed, Jul 8, 2020 at 2:47 AM Rasesh Mody <rmody@marvell.com> wrote:\n>\n> Add support for .get_reg eth_dev ops which will be used to collect the\n> firmware debug data.\n>\n> PMD on detecting on some HW errors will collect the FW/HW Dump to a\n> buffer and then it will save it to a file implemented in\n> qede_save_fw_dump().\n>\n> Dump file location and name:\n> Location: <RTE_SDK> or DPDK root\n> Name: qede_pmd_dump_mm-dd-yy_hh-mm-ss.bin\n>\n> DPDK applications can initiate a debug data collection by invoking DPDK\n> library’s rte_eth_dev_get_reg_info() API. This API invokes .get_reg()\n> interface in the PMD.\n>\n> PMD implementation of .get_reg() collects the FW/HW Dump, saves it to\n> data field of rte_dev_reg_info and passes it to the application. It’s\n> the responsibility of the application to save the FW/HW Dump to a file.\n> We recommendation using the file name format used by qede_save_fw_dump().\n>\n> Signed-off-by: Rasesh Mody <rmody@marvell.com>\n> Signed-off-by: Igor Russkikh <irusskikh@marvell.com>\n\nFound meson build failure with gcc 10. Please check.\n\nmeson  -Dexamples=l3fwd --buildtype=debugoptimized --werror\n--default-library=static /export/dpdk-next-net-mrvl/devtools/..\n./build-gcc-static\n\ngcc  -o drivers/librte_pmd_qede.so.20.0.3\n'drivers/a715181@@rte_pmd_qede@sha/meson-generated_.._rte_pmd_qede.pmd.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/bcm_osal.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_cxt.c.o' '\ndrivers/net/qede/base/f6110d5@@qede_base@sta/ecore_dcbx.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_dev.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_hw.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_init_f\nw_funcs.c.o' 'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_init_ops.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_int.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_l2.c.o'\n'drivers/net/qede/base/f6110d5@@qede_bas\ne@sta/ecore_mcp.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_sp_commands.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_spq.c.o'\n'drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_sriov.c.o'\n'drivers/net/qede/base/f61\n10d5@@qede_base@sta/ecore_vf.c.o'\n'drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_ethdev.c.o'\n'drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_filter.c.o'\n'drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o'\n'drivers/a715\n181@@tmp_rte_pmd_qede@sta/net_qede_qede_rxtx.c.o' -Wl,--as-needed\n-Wl,--no-undefined -shared -fPIC -Wl,--start-group\n-Wl,-soname,librte_pmd_qede.so.20.0 -Wl,--no-as-needed -pthread -lm\n-ldl -lnuma lib/librte_ethdev.so.20.0.3 lib/librte_eal.\nso.20.0.3 lib/librte_kvargs.so.20.0.3 lib/librte_telemetry.so.20.0.3\nlib/librte_net.so.20.0.3 lib/librte_mbuf.so.20.0.3\nlib/librte_mempool.so.20.0.3 lib/librte_ring.so.20.0.3\nlib/librte_meter.so.20.0.3 drivers/librte_bus_pci.so.20.0.3 lib/l\nibrte_pci.so.20.0.3 drivers/librte_bus_vdev.so.20.0.3\n-Wl,--version-script=/export/dpdk-next-net-mrvl/drivers/net/qede/rte_pmd_qede_version.map\n/usr/lib/libbsd.so -Wl,--end-group\n'-Wl,-rpath,$ORIGIN/../lib:$ORIGIN/' -Wl,-rpath-link,/export/\ndpdk-next-net-mrvl/build-gcc-static/lib\n-Wl,-rpath-link,/export/dpdk-next-net-mrvl/build-gcc-static/drivers\n/usr/bin/ld: drivers/net/qede/base/f6110d5@@qede_base@sta/ecore_dev.c.o:\nin function `ecore_resc_alloc':\n/export/dpdk-next-net-mrvl/build-gcc-static/../drivers/net/qede/base/ecore_dev.c:2516:\nundefined reference to `qed_dbg_alloc_user_data'\n/usr/bin/ld: /export/dpdk-next-net-mrvl/build-gcc-static/../drivers/net/qede/base/ecore_dev.c:2525:\nundefined reference to `qed_dbg_alloc_user_data'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:\nin function `qed_slowpath_start':\n/export/dpdk-next-net-mrvl/build-gcc-static/../drivers/net/qede/qede_main.c:285:\nundefined reference to `qed_dbg_pf_init'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xa8):\nundefined reference to `qed_dbg_grc'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xb0):\nundefined reference to `qed_dbg_grc_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xb8):\nundefined reference to `qed_dbg_idle_chk'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xc0):\nundefined reference to `qed_dbg_idle_chk_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xc8):\nundefined reference to `qed_dbg_reg_fifo'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xd0):\nundefined reference to `qed_dbg_reg_fifo_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xd8):\nundefined reference to `qed_dbg_mcp_trace'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xe0):\nundefined reference to `qed_dbg_mcp_trace_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xe8):\nundefined reference to `qed_dbg_protection_override'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xf0):\nundefined reference to `qed_dbg_protection_override_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0xf8):\nundefined reference to `qed_dbg_igu_fifo_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x100):\nundefined reference to `qed_dbg_igu_fifo'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x108):\nundefined reference to `qed_dbg_fw_asserts'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x110):\nundefined reference to `qed_dbg_fw_asserts_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x118):\nundefined reference to `qed_dbg_ilt'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x120):\nundefined reference to `qed_dbg_ilt_size'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x128):\nundefined reference to `qed_get_debug_engine'\n/usr/bin/ld: drivers/a715181@@tmp_rte_pmd_qede@sta/net_qede_qede_main.c.o:(.data.rel.ro+0x130):\nundefined reference to `qed_set_debug_engine'\n\n\n\n\n> ---\n>  doc/guides/nics/features/qede.ini |   1 +\n>  drivers/net/qede/Makefile         |   1 +\n>  drivers/net/qede/base/bcm_osal.c  |  25 +++\n>  drivers/net/qede/base/bcm_osal.h  |   5 +\n>  drivers/net/qede/qede_ethdev.c    |   1 +\n>  drivers/net/qede/qede_ethdev.h    |  25 +++\n>  drivers/net/qede/qede_regs.c      | 271 ++++++++++++++++++++++++++++++\n>  7 files changed, 329 insertions(+)\n>  create mode 100644 drivers/net/qede/qede_regs.c\n>\n> diff --git a/doc/guides/nics/features/qede.ini b/doc/guides/nics/features/qede.ini\n> index 20c90e626..f8716523e 100644\n> --- a/doc/guides/nics/features/qede.ini\n> +++ b/doc/guides/nics/features/qede.ini\n> @@ -31,6 +31,7 @@ Packet type parsing  = Y\n>  Basic stats          = Y\n>  Extended stats       = Y\n>  Stats per queue      = Y\n> +Registers dump       = Y\n>  Multiprocess aware   = Y\n>  Linux UIO            = Y\n>  Linux VFIO           = Y\n> diff --git a/drivers/net/qede/Makefile b/drivers/net/qede/Makefile\n> index 3b00338ff..0e8a67b0d 100644\n> --- a/drivers/net/qede/Makefile\n> +++ b/drivers/net/qede/Makefile\n> @@ -104,5 +104,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_main.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_rxtx.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_filter.c\n>  SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_debug.c\n> +SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_regs.c\n>\n>  include $(RTE_SDK)/mk/rte.lib.mk\n> diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\n> index 45557fe3c..65837b53d 100644\n> --- a/drivers/net/qede/base/bcm_osal.c\n> +++ b/drivers/net/qede/base/bcm_osal.c\n> @@ -246,6 +246,28 @@ qede_get_mcp_proto_stats(struct ecore_dev *edev,\n>         }\n>  }\n>\n> +static void qede_hw_err_handler(void *dev, enum ecore_hw_err_type err_type)\n> +{\n> +       struct ecore_dev *edev = dev;\n> +\n> +       switch (err_type) {\n> +       case ECORE_HW_ERR_FAN_FAIL:\n> +               break;\n> +\n> +       case ECORE_HW_ERR_MFW_RESP_FAIL:\n> +       case ECORE_HW_ERR_HW_ATTN:\n> +       case ECORE_HW_ERR_DMAE_FAIL:\n> +       case ECORE_HW_ERR_RAMROD_FAIL:\n> +       case ECORE_HW_ERR_FW_ASSERT:\n> +               OSAL_SAVE_FW_DUMP(0); /* Using port 0 as default port_id */\n> +               break;\n> +\n> +       default:\n> +               DP_NOTICE(edev, false, \"Unknown HW error [%d]\\n\", err_type);\n> +               return;\n> +       }\n> +}\n> +\n>  void\n>  qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)\n>  {\n> @@ -275,6 +297,9 @@ qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)\n>         }\n>\n>         DP_ERR(p_hwfn, \"HW error occurred [%s]\\n\", err_str);\n> +\n> +       qede_hw_err_handler(p_hwfn->p_dev, err_type);\n> +\n>         ecore_int_attn_clr_enable(p_hwfn->p_dev, true);\n>  }\n>\n> diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\n> index b4b94231b..5d4df5907 100644\n> --- a/drivers/net/qede/base/bcm_osal.h\n> +++ b/drivers/net/qede/base/bcm_osal.h\n> @@ -371,6 +371,11 @@ void qede_hw_err_notify(struct ecore_hwfn *p_hwfn,\n>\n>  /* TODO: */\n>  #define OSAL_SCHEDULE_RECOVERY_HANDLER(hwfn) nothing\n> +\n> +int qede_save_fw_dump(uint8_t port_id);\n> +\n> +#define OSAL_SAVE_FW_DUMP(port_id) qede_save_fw_dump(port_id)\n> +\n>  #define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) \\\n>         qede_hw_err_notify(hwfn, err_type)\n>\n> diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\n> index b5d6c7c43..e5a2581dd 100644\n> --- a/drivers/net/qede/qede_ethdev.c\n> +++ b/drivers/net/qede/qede_ethdev.c\n> @@ -2426,6 +2426,7 @@ static const struct eth_dev_ops qede_eth_dev_ops = {\n>         .udp_tunnel_port_add = qede_udp_dst_port_add,\n>         .udp_tunnel_port_del = qede_udp_dst_port_del,\n>         .fw_version_get = qede_fw_version_get,\n> +       .get_reg = qede_get_regs,\n>  };\n>\n>  static const struct eth_dev_ops qede_eth_vf_dev_ops = {\n> diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h\n> index b988a73f2..76c5dae3b 100644\n> --- a/drivers/net/qede/qede_ethdev.h\n> +++ b/drivers/net/qede/qede_ethdev.h\n> @@ -214,6 +214,8 @@ struct qede_tunn_params {\n>         uint16_t udp_port;\n>  };\n>\n> +#define QEDE_FW_DUMP_FILE_SIZE 128\n> +\n>  /*\n>   *  Structure to store private data for each port.\n>   */\n> @@ -252,6 +254,7 @@ struct qede_dev {\n>         char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];\n>         bool vport_started;\n>         int vlan_offload_mask;\n> +       char dump_file[QEDE_FW_DUMP_FILE_SIZE];\n>         void *ethdev;\n>  };\n>\n> @@ -313,4 +316,26 @@ void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);\n>  int qede_ucast_filter(struct rte_eth_dev *eth_dev,\n>                       struct ecore_filter_ucast *ucast,\n>                       bool add);\n> +\n> +#define REGDUMP_HEADER_SIZE sizeof(u32)\n> +#define REGDUMP_HEADER_FEATURE_SHIFT 24\n> +#define REGDUMP_HEADER_ENGINE_SHIFT 31\n> +#define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30\n> +\n> +enum debug_print_features {\n> +       OLD_MODE = 0,\n> +       IDLE_CHK = 1,\n> +       GRC_DUMP = 2,\n> +       MCP_TRACE = 3,\n> +       REG_FIFO = 4,\n> +       PROTECTION_OVERRIDE = 5,\n> +       IGU_FIFO = 6,\n> +       PHY = 7,\n> +       FW_ASSERTS = 8,\n> +};\n> +\n> +int qede_get_regs_len(struct qede_dev *qdev);\n> +int qede_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs);\n> +void qede_config_rx_mode(struct rte_eth_dev *eth_dev);\n> +void qed_dbg_dump(struct rte_eth_dev *eth_dev);\n>  #endif /* _QEDE_ETHDEV_H_ */\n> diff --git a/drivers/net/qede/qede_regs.c b/drivers/net/qede/qede_regs.c\n> new file mode 100644\n> index 000000000..4409d2180\n> --- /dev/null\n> +++ b/drivers/net/qede/qede_regs.c\n> @@ -0,0 +1,271 @@\n> +/* SPDX-License-Identifier: BSD-3-Clause\n> + * Copyright (c) 2020 Marvell Semiconductor Inc.\n> + * All rights reserved.\n> + * www.marvell.com\n> + */\n> +\n> +#include <stdio.h>\n> +#include <stdlib.h>\n> +#include <fcntl.h>\n> +#include <time.h>\n> +#include <rte_ethdev.h>\n> +#include \"base/bcm_osal.h\"\n> +#include \"qede_ethdev.h\"\n> +\n> +int\n> +qede_get_regs_len(struct qede_dev *qdev)\n> +{\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       int cur_engine, num_of_hwfns, regs_len = 0;\n> +       uint8_t org_engine;\n> +\n> +       if (IS_VF(edev))\n> +               return 0;\n> +\n> +       if (qdev->ops && qdev->ops->common) {\n> +               num_of_hwfns = qdev->dev_info.common.num_hwfns;\n> +               org_engine = qdev->ops->common->dbg_get_debug_engine(edev);\n> +               for (cur_engine = 0; cur_engine < num_of_hwfns; cur_engine++) {\n> +                       /* compute required buffer size for idle_chks and\n> +                        * grcDump for each hw function\n> +                        */\n> +                       DP_NOTICE(edev, false,\n> +                               \"Calculating idle_chk and grcdump register length for current engine\\n\");\n> +                       qdev->ops->common->dbg_set_debug_engine(edev,\n> +                                                               cur_engine);\n> +                       regs_len += REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_idle_chk_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_idle_chk_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_grc_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_reg_fifo_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_protection_override_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_igu_fifo_size(edev) +\n> +                               REGDUMP_HEADER_SIZE +\n> +                               qdev->ops->common->dbg_fw_asserts_size(edev);\n> +               }\n> +               /* compute required buffer size for mcp trace and add it to the\n> +                * total required buffer size\n> +                */\n> +               regs_len += REGDUMP_HEADER_SIZE +\n> +                           qdev->ops->common->dbg_mcp_trace_size(edev);\n> +\n> +               qdev->ops->common->dbg_set_debug_engine(edev, org_engine);\n> +       }\n> +       DP_NOTICE(edev, false, \"Total length = %u\\n\", regs_len);\n> +\n> +       return regs_len;\n> +}\n> +\n> +static uint32_t\n> +qede_calc_regdump_header(enum debug_print_features feature, int engine,\n> +                        uint32_t feature_size, uint8_t omit_engine)\n> +{\n> +       /* insert the engine, feature and mode inside the header and\n> +        * combine it with feature size\n> +        */\n> +       return (feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) |\n> +               (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) |\n> +               (engine << REGDUMP_HEADER_ENGINE_SHIFT));\n> +}\n> +\n> +int qede_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n> +{\n> +       struct qede_dev *qdev = eth_dev->data->dev_private;\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       uint32_t *buffer = regs->data;\n> +       int cur_engine, num_of_hwfns;\n> +       /* '1' tells the parser to omit the engine number in the output files */\n> +       uint8_t omit_engine = 0;\n> +       uint8_t org_engine;\n> +       uint32_t feature_size;\n> +       uint32_t offset = 0;\n> +\n> +       if (IS_VF(edev))\n> +               return -ENOTSUP;\n> +\n> +       if (buffer == NULL) {\n> +               regs->length = qede_get_regs_len(qdev);\n> +               regs->width =  sizeof(uint32_t);\n> +               DP_INFO(edev, \"Length %u\\n\", regs->length);\n> +               return 0;\n> +       }\n> +\n> +       memset(buffer, 0, regs->length);\n> +       num_of_hwfns = qdev->dev_info.common.num_hwfns;\n> +       if (num_of_hwfns == 1)\n> +               omit_engine = 1;\n> +\n> +       OSAL_MUTEX_ACQUIRE(&edev->dbg_lock);\n> +\n> +       org_engine = qdev->ops->common->dbg_get_debug_engine(edev);\n> +       for (cur_engine = 0; cur_engine < num_of_hwfns; cur_engine++) {\n> +               /* collect idle_chks and grcDump for each hw function */\n> +               DP_NOTICE(edev, false, \"obtaining idle_chk and grcdump for current engine\\n\");\n> +               qdev->ops->common->dbg_set_debug_engine(edev, cur_engine);\n> +\n> +               /* first idle_chk */\n> +               qdev->ops->common->dbg_idle_chk(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IDLE_CHK, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Idle Check1 feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* second idle_chk */\n> +               qdev->ops->common->dbg_idle_chk(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IDLE_CHK, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Idle Check2 feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* reg_fifo dump */\n> +               qdev->ops->common->dbg_reg_fifo(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(REG_FIFO, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Reg fifo feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* igu_fifo dump */\n> +               qdev->ops->common->dbg_igu_fifo(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(IGU_FIFO, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"IGU fifo feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* protection_override dump */\n> +               qdev->ops->common->dbg_protection_override(edev,\n> +                                                          (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                      qede_calc_regdump_header(PROTECTION_OVERRIDE, cur_engine,\n> +                                               feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"Protection override feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* fw_asserts dump */\n> +               qdev->ops->common->dbg_fw_asserts(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(FW_ASSERTS, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"FW assert feature_size %u\\n\",\n> +                         feature_size);\n> +\n> +               /* grc dump */\n> +               qdev->ops->common->dbg_grc(edev, (uint8_t *)buffer +\n> +                       offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +               *(uint32_t *)((uint8_t *)buffer + offset) =\n> +                       qede_calc_regdump_header(GRC_DUMP, cur_engine,\n> +                                                feature_size, omit_engine);\n> +               offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +               DP_NOTICE(edev, false, \"GRC dump feature_size %u\\n\",\n> +                         feature_size);\n> +       }\n> +\n> +       /* mcp_trace */\n> +       qdev->ops->common->dbg_mcp_trace(edev, (uint8_t *)buffer +\n> +               offset + REGDUMP_HEADER_SIZE, &feature_size);\n> +       *(uint32_t *)((uint8_t *)buffer + offset) =\n> +               qede_calc_regdump_header(MCP_TRACE, cur_engine, feature_size,\n> +                                        omit_engine);\n> +       offset += (feature_size + REGDUMP_HEADER_SIZE);\n> +       DP_NOTICE(edev, false, \"MCP trace feature_size %u\\n\", feature_size);\n> +\n> +       qdev->ops->common->dbg_set_debug_engine(edev, org_engine);\n> +\n> +       OSAL_MUTEX_RELEASE(&edev->dbg_lock);\n> +\n> +       return 0;\n> +}\n> +\n> +static void\n> +qede_set_fw_dump_file_name(struct qede_dev *qdev)\n> +{\n> +       time_t ltime;\n> +       struct tm *tm;\n> +\n> +       ltime = time(NULL);\n> +       tm = localtime(&ltime);\n> +       snprintf(qdev->dump_file, QEDE_FW_DUMP_FILE_SIZE,\n> +                \"qede_pmd_dump_%02d-%02d-%02d_%02d-%02d-%02d.bin\",\n> +                tm->tm_mon + 1, (int)tm->tm_mday, 1900 + tm->tm_year,\n> +                tm->tm_hour, tm->tm_min, tm->tm_sec);\n> +}\n> +\n> +static int\n> +qede_write_fwdump(const char *dump_file, void *dump, size_t len)\n> +{\n> +       int err = 0;\n> +       FILE *f;\n> +       size_t bytes;\n> +\n> +       f = fopen(dump_file, \"wb+\");\n> +\n> +       if (!f) {\n> +               fprintf(stderr, \"Can't open file %s: %s\\n\",\n> +                       dump_file, strerror(errno));\n> +               return 1;\n> +       }\n> +       bytes = fwrite(dump, 1, len, f);\n> +       if (bytes != len) {\n> +               fprintf(stderr, \"Can not write all of dump data bytes=%ld len=%ld\\n\",\n> +                       bytes, len);\n> +               err = 1;\n> +       }\n> +\n> +       if (fclose(f)) {\n> +               fprintf(stderr, \"Can't close file %s: %s\\n\",\n> +                       dump_file, strerror(errno));\n> +               err = 1;\n> +       }\n> +\n> +       return err;\n> +}\n> +\n> +int\n> +qede_save_fw_dump(uint8_t port_id)\n> +{\n> +       struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];\n> +       struct rte_dev_reg_info regs;\n> +       struct qede_dev *qdev = eth_dev->data->dev_private;\n> +       struct ecore_dev *edev = &qdev->edev;\n> +       int rc = 0;\n> +\n> +       if (!rte_eth_dev_is_valid_port(port_id)) {\n> +               DP_ERR(edev, \"port %u invalid port ID\", port_id);\n> +               return -ENODEV;\n> +       }\n> +\n> +       memset(&regs, 0, sizeof(regs));\n> +       regs.length = qede_get_regs_len(qdev);\n> +       regs.data = OSAL_ZALLOC(eth_dev, GFP_KERNEL, regs.length);\n> +       if (regs.data) {\n> +               qede_get_regs(eth_dev, &regs);\n> +               qede_set_fw_dump_file_name(qdev);\n> +               rc = qede_write_fwdump(qdev->dump_file, regs.data, regs.length);\n> +               if (!rc)\n> +                       DP_NOTICE(edev, false, \"FW dump written to %s file\\n\",\n> +                                 qdev->dump_file);\n> +               OSAL_FREE(edev, regs.data);\n> +       }\n> +\n> +       return rc;\n> +}\n> --\n> 2.18.0\n>",
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            "Subject": "Re: [dpdk-dev] [PATCH v4 4/4] net/qede: add support for get\n\tregister operation",
            "Cc": "Jerin Jacob <jerinj@marvell.com>, Ferruh Yigit <ferruh.yigit@intel.com>,\n dpdk-dev <dev@dpdk.org>,\n GR-Everest-DPDK-Dev <GR-Everest-DPDK-Dev@marvell.com>,\n Igor Russkikh <irusskikh@marvell.com>",
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            "Date": "Wed, 8 Jul 2020 14:59:00 +0530",
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]