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{
    "id": 73471,
    "url": "https://patches.dpdk.org/api/patches/73471/",
    "web_url": "https://patches.dpdk.org/patch/73471/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200707211617.4408-2-rmody@marvell.com>",
    "date": "2020-07-07T21:16:14",
    "name": "[v4,1/4] net/qede/base: re-arrange few structures for DDC",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "679872bd1eeba249fe8e444fe463e58ec69c94d8",
    "submitter": {
        "id": 1211,
        "url": "https://patches.dpdk.org/api/people/1211/",
        "name": "Rasesh Mody",
        "email": "rmody@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73471/mbox/",
    "series": [
        {
            "id": 10863,
            "url": "https://patches.dpdk.org/api/series/10863/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10863",
            "date": "2020-07-07T20:18:40",
            "name": "net/qede: add FW debug data collection support",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/10863/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73471/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/73471/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "To": "<jerinj@marvell.com>, <ferruh.yigit@intel.com>",
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        "Message-ID": "<20200707211617.4408-2-rmody@marvell.com>",
        "CC": "Rasesh Mody <rmody@marvell.com>, <dev@dpdk.org>,\n <GR-Everest-DPDK-Dev@marvell.com>, Igor Russkikh <irusskikh@marvell.com>",
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        ],
        "Subject": "[dpdk-dev] [PATCH v4 1/4] net/qede/base: re-arrange few structures\n\tfor DDC",
        "In-Reply-To": "<20200707201844.16111-1-rmody@marvell.com>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Date": "Tue, 7 Jul 2020 14:16:14 -0700",
        "Precedence": "list",
        "From": "Rasesh Mody <rmody@marvell.com>",
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        "References": "<20200707201844.16111-1-rmody@marvell.com>",
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        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>"
    },
    "content": "This patch rearranges some of the base driver structures which will be\nalso used by debug data collection (DDC) implementation. It adds a new\nfile ecore_hsi_func_common.h with Physical, Virtual memory descriptors.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/net/qede/base/ecore.h                 |   2 +\n drivers/net/qede/base/ecore_cxt.c             | 140 ++----------------\n drivers/net/qede/base/ecore_cxt.h             | 135 ++++++++++++++++-\n drivers/net/qede/base/ecore_dev.c             |  13 +-\n drivers/net/qede/base/ecore_hsi_func_common.h |  17 +++\n drivers/net/qede/base/ecore_init_fw_funcs.h   |   7 -\n 6 files changed, 172 insertions(+), 142 deletions(-)\n create mode 100644 drivers/net/qede/base/ecore_hsi_func_common.h",
    "diff": "diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex 498bb6f09..dc5fe4d80 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -24,6 +24,7 @@\n #include \"ecore_hsi_debug_tools.h\"\n #include \"ecore_hsi_init_func.h\"\n #include \"ecore_hsi_init_tool.h\"\n+#include \"ecore_hsi_func_common.h\"\n #include \"ecore_proto_if.h\"\n #include \"mcp_public.h\"\n \n@@ -671,6 +672,7 @@ struct ecore_hwfn {\n \n \tstruct dbg_tools_data\t\tdbg_info;\n \tvoid\t\t\t\t*dbg_user_info;\n+\tstruct virt_mem_desc\t\tdbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];\n \n \tstruct z_stream_s\t\t*stream;\n \ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex dda47ea67..23f37b1bf 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -20,12 +20,6 @@\n #include \"ecore_sriov.h\"\n #include \"ecore_mcp.h\"\n \n-/* Max number of connection types in HW (DQ/CDU etc.) */\n-#define MAX_CONN_TYPES\t\tPROTOCOLID_COMMON\n-#define NUM_TASK_TYPES\t\t2\n-#define NUM_TASK_PF_SEGMENTS\t4\n-#define NUM_TASK_VF_SEGMENTS\t1\n-\n /* Doorbell-Queue constants */\n #define DQ_RANGE_SHIFT\t4\n #define DQ_RANGE_ALIGN\t(1 << DQ_RANGE_SHIFT)\n@@ -90,128 +84,6 @@ struct src_ent {\n /* Alignment is inherent to the type1_task_context structure */\n #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)\n \n-/* PF per protocl configuration object */\n-#define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)\n-#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)\n-\n-struct ecore_tid_seg {\n-\tu32 count;\n-\tu8 type;\n-\tbool has_fl_mem;\n-};\n-\n-struct ecore_conn_type_cfg {\n-\tu32 cid_count;\n-\tu32 cids_per_vf;\n-\tstruct ecore_tid_seg tid_seg[TASK_SEGMENTS];\n-};\n-\n-/* ILT Client configuration,\n- * Per connection type (protocol) resources (cids, tis, vf cids etc.)\n- * 1 - for connection context (CDUC) and for each task context we need two\n- * values, for regular task context and for force load memory\n- */\n-#define ILT_CLI_PF_BLOCKS\t(1 + NUM_TASK_PF_SEGMENTS * 2)\n-#define ILT_CLI_VF_BLOCKS\t(1 + NUM_TASK_VF_SEGMENTS * 2)\n-#define CDUC_BLK\t\t(0)\n-#define SRQ_BLK\t\t\t(0)\n-#define CDUT_SEG_BLK(n)\t\t(1 + (u8)(n))\n-#define CDUT_FL_SEG_BLK(n, X)\t(1 + (n) + NUM_TASK_##X##_SEGMENTS)\n-\n-struct ilt_cfg_pair {\n-\tu32 reg;\n-\tu32 val;\n-};\n-\n-struct ecore_ilt_cli_blk {\n-\tu32 total_size;\t\t/* 0 means not active */\n-\tu32 real_size_in_page;\n-\tu32 start_line;\n-\tu32 dynamic_line_offset;\n-\tu32 dynamic_line_cnt;\n-};\n-\n-struct ecore_ilt_client_cfg {\n-\tbool active;\n-\n-\t/* ILT boundaries */\n-\tstruct ilt_cfg_pair first;\n-\tstruct ilt_cfg_pair last;\n-\tstruct ilt_cfg_pair p_size;\n-\n-\t/* ILT client blocks for PF */\n-\tstruct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];\n-\tu32 pf_total_lines;\n-\n-\t/* ILT client blocks for VFs */\n-\tstruct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];\n-\tu32 vf_total_lines;\n-};\n-\n-#define MAP_WORD_SIZE\t\tsizeof(unsigned long)\n-#define BITS_PER_MAP_WORD\t(MAP_WORD_SIZE * 8)\n-\n-struct ecore_cid_acquired_map {\n-\tu32 start_cid;\n-\tu32 max_count;\n-\tu32 *cid_map;\n-};\n-\n-struct ecore_src_t2 {\n-\tstruct phys_mem_desc\t*dma_mem;\n-\tu32\t\t\tnum_pages;\n-\tu64\t\t\tfirst_free;\n-\tu64\t\t\tlast_free;\n-};\n-\n-struct ecore_cxt_mngr {\n-\t/* Per protocl configuration */\n-\tstruct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];\n-\n-\t/* computed ILT structure */\n-\tstruct ecore_ilt_client_cfg clients[ILT_CLI_MAX];\n-\n-\t/* Task type sizes */\n-\tu32 task_type_size[NUM_TASK_TYPES];\n-\n-\t/* total number of VFs for this hwfn -\n-\t * ALL VFs are symmetric in terms of HW resources\n-\t */\n-\tu32 vf_count;\n-\n-\t/* Acquired CIDs */\n-\tstruct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];\n-\tstruct ecore_cid_acquired_map *acquired_vf[MAX_CONN_TYPES];\n-\n-\t/* ILT  shadow table */\n-\tstruct phys_mem_desc\t\t*ilt_shadow;\n-\tu32 pf_start_line;\n-\n-\t/* Mutex for a dynamic ILT allocation */\n-\tosal_mutex_t mutex;\n-\n-\t/* SRC T2 */\n-\tstruct ecore_src_t2\t\tsrc_t2;\n-\n-\t/* The infrastructure originally was very generic and context/task\n-\t * oriented - per connection-type we would set how many of those\n-\t * are needed, and later when determining how much memory we're\n-\t * needing for a given block we'd iterate over all the relevant\n-\t * connection-types.\n-\t * But since then we've had some additional resources, some of which\n-\t * require memory which is indepent of the general context/task\n-\t * scheme. We add those here explicitly per-feature.\n-\t */\n-\n-\t/* total number of SRQ's for this hwfn */\n-\tu32\t\t\t\tsrq_count;\n-\n-\t/* Maximal number of L2 steering filters */\n-\tu32\t\t\t\tarfs_count;\n-\n-\t/* TODO - VF arfs filters ? */\n-};\n-\n static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)\n {\n \treturn type == PROTOCOLID_TOE;\n@@ -945,7 +817,7 @@ static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)\n }\n \n #define for_each_ilt_valid_client(pos, clients)\t\t\\\n-\tfor (pos = 0; pos < ILT_CLI_MAX; pos++)\t\t\\\n+\tfor (pos = 0; pos < MAX_ILT_CLIENTS; pos++)\t\t\\\n \t\tif (!clients[pos].active) {\t\t\\\n \t\t\tcontinue;\t\t\t\\\n \t\t} else\t\t\t\t\t\\\n@@ -1238,7 +1110,7 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)\n \tclients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);\n \n \t/* default ILT page size for all clients is 64K */\n-\tfor (i = 0; i < ILT_CLI_MAX; i++)\n+\tfor (i = 0; i < MAX_ILT_CLIENTS; i++)\n \t\tp_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;\n \n \t/* due to removal of ISCSI/FCoE files union type0_task_context\n@@ -2306,3 +2178,11 @@ ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,\n \n \treturn ECORE_SUCCESS;\n }\n+\n+static u16 ecore_blk_calculate_pages(struct ecore_ilt_cli_blk *p_blk)\n+{\n+\tif (p_blk->real_size_in_page == 0)\n+\t\treturn 0;\n+\n+\treturn DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);\n+}\ndiff --git a/drivers/net/qede/base/ecore_cxt.h b/drivers/net/qede/base/ecore_cxt.h\nindex 55f08027d..7b91b953e 100644\n--- a/drivers/net/qede/base/ecore_cxt.h\n+++ b/drivers/net/qede/base/ecore_cxt.h\n@@ -31,7 +31,7 @@ enum ilt_clients {\n \tILT_CLI_TSDM,\n \tILT_CLI_RGFS,\n \tILT_CLI_TGFS,\n-\tILT_CLI_MAX\n+\tMAX_ILT_CLIENTS\n };\n \n u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,\n@@ -212,4 +212,137 @@ enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,\n #define ECORE_CTX_WORKING_MEM 0\n #define ECORE_CTX_FL_MEM 1\n \n+/* Max number of connection types in HW (DQ/CDU etc.) */\n+#define MAX_CONN_TYPES\t\tPROTOCOLID_COMMON\n+#define NUM_TASK_TYPES\t\t2\n+#define NUM_TASK_PF_SEGMENTS\t4\n+#define NUM_TASK_VF_SEGMENTS\t1\n+\n+/* PF per protocol configuration object */\n+#define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)\n+#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)\n+\n+struct ecore_tid_seg {\n+\tu32 count;\n+\tu8 type;\n+\tbool has_fl_mem;\n+};\n+\n+struct ecore_conn_type_cfg {\n+\tu32 cid_count;\n+\tu32 cids_per_vf;\n+\tstruct ecore_tid_seg tid_seg[TASK_SEGMENTS];\n+};\n+\n+/* ILT Client configuration,\n+ * Per connection type (protocol) resources (cids, tis, vf cids etc.)\n+ * 1 - for connection context (CDUC) and for each task context we need two\n+ * values, for regular task context and for force load memory\n+ */\n+#define ILT_CLI_PF_BLOCKS\t(1 + NUM_TASK_PF_SEGMENTS * 2)\n+#define ILT_CLI_VF_BLOCKS\t(1 + NUM_TASK_VF_SEGMENTS * 2)\n+#define CDUC_BLK\t\t(0)\n+#define SRQ_BLK\t\t\t(0)\n+#define CDUT_SEG_BLK(n)\t\t(1 + (u8)(n))\n+#define CDUT_FL_SEG_BLK(n, X)\t(1 + (n) + NUM_TASK_##X##_SEGMENTS)\n+\n+struct ilt_cfg_pair {\n+\tu32 reg;\n+\tu32 val;\n+};\n+\n+struct ecore_ilt_cli_blk {\n+\tu32 total_size;\t\t/* 0 means not active */\n+\tu32 real_size_in_page;\n+\tu32 start_line;\n+\tu32 dynamic_line_offset;\n+\tu32 dynamic_line_cnt;\n+};\n+\n+struct ecore_ilt_client_cfg {\n+\tbool active;\n+\n+\t/* ILT boundaries */\n+\tstruct ilt_cfg_pair first;\n+\tstruct ilt_cfg_pair last;\n+\tstruct ilt_cfg_pair p_size;\n+\n+\t/* ILT client blocks for PF */\n+\tstruct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];\n+\tu32 pf_total_lines;\n+\n+\t/* ILT client blocks for VFs */\n+\tstruct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];\n+\tu32 vf_total_lines;\n+};\n+\n+#define MAP_WORD_SIZE\t\tsizeof(unsigned long)\n+#define BITS_PER_MAP_WORD\t(MAP_WORD_SIZE * 8)\n+\n+struct ecore_cid_acquired_map {\n+\tu32 start_cid;\n+\tu32 max_count;\n+\tu32 *cid_map;\n+};\n+\n+struct ecore_src_t2 {\n+\tstruct phys_mem_desc\t*dma_mem;\n+\tu32\t\t\tnum_pages;\n+\tu64\t\t\tfirst_free;\n+\tu64\t\t\tlast_free;\n+};\n+\n+struct ecore_cxt_mngr {\n+\t/* Per protocol configuration */\n+\tstruct ecore_conn_type_cfg\tconn_cfg[MAX_CONN_TYPES];\n+\n+\t/* computed ILT structure */\n+\tstruct ecore_ilt_client_cfg\tclients[MAX_ILT_CLIENTS];\n+\n+\t/* Task type sizes */\n+\tu32\t\t\t\ttask_type_size[NUM_TASK_TYPES];\n+\n+\t/* total number of VFs for this hwfn -\n+\t * ALL VFs are symmetric in terms of HW resources\n+\t */\n+\tu32\t\t\t\tvf_count;\n+\tu32\t\t\t\tfirst_vf_in_pf;\n+\n+\t/* Acquired CIDs */\n+\tstruct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];\n+\tstruct ecore_cid_acquired_map *acquired_vf[MAX_CONN_TYPES];\n+\n+\t/* ILT  shadow table */\n+\tstruct phys_mem_desc\t\t*ilt_shadow;\n+\tu32\t\t\t\tilt_shadow_size;\n+\tu32\t\t\t\tpf_start_line;\n+\n+\t/* Mutex for a dynamic ILT allocation */\n+\tosal_mutex_t mutex;\n+\n+\t/* SRC T2 */\n+\tstruct ecore_src_t2\t\tsrc_t2;\n+\n+\t/* The infrastructure originally was very generic and context/task\n+\t * oriented - per connection-type we would set how many of those\n+\t * are needed, and later when determining how much memory we're\n+\t * needing for a given block we'd iterate over all the relevant\n+\t * connection-types.\n+\t * But since then we've had some additional resources, some of which\n+\t * require memory which is independent of the general context/task\n+\t * scheme. We add those here explicitly per-feature.\n+\t */\n+\n+\t/* total number of SRQ's for this hwfn */\n+\tu32\t\t\t\tsrq_count;\n+\n+\t/* Maximal number of L2 steering filters */\n+\tu32\t\t\t\tarfs_count;\n+\n+\t/* TODO - VF arfs filters ? */\n+\n+\tu8\t\t\t\ttask_type_id;\n+\tu16\t\t\t\ttask_ctx_size;\n+\tu16\t\t\t\tconn_ctx_size;\n+};\n #endif /* _ECORE_CID_ */\ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex e18c2fa89..814d9ced6 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -2358,6 +2358,7 @@ static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)\n enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n {\n \tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tenum dbg_status debug_status = DBG_STATUS_OK;\n \tint i;\n \n \tif (IS_VF(p_dev)) {\n@@ -2512,17 +2513,21 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n \t\t\tgoto alloc_err;\n \t\t}\n \n-\t\trc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);\n-\t\tif (rc) {\n+\t\tdebug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,\n+\t\t\t\t\t\t\t&p_hwfn->dbg_user_info);\n+\t\tif (debug_status) {\n \t\t\tDP_NOTICE(p_hwfn, false,\n \t\t\t\t  \"Failed to allocate dbg user info structure\\n\");\n+\t\t\trc = (enum _ecore_status_t)debug_status;\n \t\t\tgoto alloc_err;\n \t\t}\n \n-\t\trc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);\n-\t\tif (rc) {\n+\t\tdebug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,\n+\t\t\t\t\t\t\t&p_hwfn->dbg_user_info);\n+\t\tif (debug_status) {\n \t\t\tDP_NOTICE(p_hwfn, false,\n \t\t\t\t  \"Failed to allocate dbg user info structure\\n\");\n+\t\t\trc = (enum _ecore_status_t)debug_status;\n \t\t\tgoto alloc_err;\n \t\t}\n \t} /* hwfn loop */\ndiff --git a/drivers/net/qede/base/ecore_hsi_func_common.h b/drivers/net/qede/base/ecore_hsi_func_common.h\nnew file mode 100644\nindex 000000000..2cd175163\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_hsi_func_common.h\n@@ -0,0 +1,17 @@\n+#ifndef _HSI_FUNC_COMMON_H\n+#define _HSI_FUNC_COMMON_H\n+\n+/* Physical memory descriptor */\n+struct phys_mem_desc {\n+\tdma_addr_t phys_addr;\n+\tvoid *virt_addr;\n+\tu32 size; /* In bytes */\n+};\n+\n+/* Virtual memory descriptor */\n+struct virt_mem_desc {\n+\tvoid *ptr;\n+\tu32 size; /* In bytes */\n+};\n+\n+#endif\ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h\nindex 912451662..a393d088f 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.h\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.h\n@@ -9,13 +9,6 @@\n #include \"ecore_hsi_common.h\"\n #include \"ecore_hsi_eth.h\"\n \n-/* Physical memory descriptor */\n-struct phys_mem_desc {\n-\tdma_addr_t phys_addr;\n-\tvoid *virt_addr;\n-\tu32 size; /* In bytes */\n-};\n-\n /* Returns the VOQ based on port and TC */\n #define VOQ(port, tc, max_phys_tcs_per_port) \\\n \t((tc) == PURE_LB_TC ? NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + (port) : \\\n",
    "prefixes": [
        "v4",
        "1/4"
    ]
}