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{
    "id": 73466,
    "url": "https://patches.dpdk.org/api/patches/73466/",
    "web_url": "https://patches.dpdk.org/patch/73466/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200707201844.16111-3-rmody@marvell.com>",
    "date": "2020-07-07T20:18:42",
    "name": "[v3,2/4] net/qede/base: add changes for debug data collection",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "1a98e5147914cbcf8772f9db0e4a8ad64aa75c01",
    "submitter": {
        "id": 1211,
        "url": "https://patches.dpdk.org/api/people/1211/",
        "name": "Rasesh Mody",
        "email": "rmody@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73466/mbox/",
    "series": [
        {
            "id": 10681,
            "url": "https://patches.dpdk.org/api/series/10681/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10681",
            "date": "2020-06-30T08:32:11",
            "name": "net/qede: add FW debug data collection support",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/10681/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73466/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/73466/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "To": "<jerinj@marvell.com>, <ferruh.yigit@intel.com>",
        "X-Mailer": "git-send-email 2.18.0",
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        "List-Post": "<mailto:dev@dpdk.org>",
        "Message-ID": "<20200707201844.16111-3-rmody@marvell.com>",
        "CC": "Rasesh Mody <rmody@marvell.com>, <dev@dpdk.org>,\n <GR-Everest-DPDK-Dev@marvell.com>, Igor Russkikh <irusskikh@marvell.com>",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 10969A00BE;\n\tTue,  7 Jul 2020 22:19:22 +0200 (CEST)",
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            "from sc-exch04.marvell.com ([199.233.58.184])\n by mx0a-0016f401.pphosted.com with ESMTP id 322q4pwhan-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 07 Jul 2020 13:19:17 -0700",
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            "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 7 Jul 2020 13:19:16 -0700",
            "from irv1user08.caveonetworks.com (unknown [10.104.116.105])\n by maili.marvell.com (Postfix) with ESMTP id 145323F704B;\n Tue,  7 Jul 2020 13:19:16 -0700 (PDT)",
            "(from rmody@localhost)\n by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id 067KJFHa016325;\n Tue, 7 Jul 2020 13:19:15 -0700"
        ],
        "Subject": "[dpdk-dev] [PATCH v3 2/4] net/qede/base: add changes for debug data\n\tcollection",
        "In-Reply-To": "<20200630083215.13108-1-rmody@marvell.com>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-07_13:2020-07-07,\n 2020-07-07 signatures=0",
        "Date": "Tue, 7 Jul 2020 13:18:42 -0700",
        "Precedence": "list",
        "From": "Rasesh Mody <rmody@marvell.com>",
        "X-Authentication-Warning": "irv1user08.caveonetworks.com: rmody set sender to\n rmody@marvell.com using -f",
        "MIME-Version": "1.0",
        "References": "<20200630083215.13108-1-rmody@marvell.com>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Errors-To": "dev-bounces@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Content-Type": "text/plain",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>"
    },
    "content": "This patch adds base driver APIs required for debug data collection.\nIt adds support for dumping internal lookup tables(ilt), reading nvram\nimage, register definitions.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/net/qede/base/bcm_osal.c              |   6 +\n drivers/net/qede/base/bcm_osal.h              |   8 +-\n drivers/net/qede/base/common_hsi.h            |   1 +\n drivers/net/qede/base/ecore.h                 |  52 +-\n drivers/net/qede/base/ecore_cxt.c             |  60 ++\n drivers/net/qede/base/ecore_cxt.h             |   5 +\n drivers/net/qede/base/ecore_dev.c             |  13 +\n drivers/net/qede/base/ecore_hsi_common.h      | 184 +++-\n drivers/net/qede/base/ecore_hsi_debug_tools.h |   2 +-\n drivers/net/qede/base/ecore_mcp.c             | 211 +++++\n drivers/net/qede/base/ecore_mcp_api.h         |  37 +\n drivers/net/qede/base/ecore_status.h          |   2 +\n drivers/net/qede/base/reg_addr.h              | 846 ++++++++++++++++++\n drivers/net/qede/qede_ethdev.c                |   1 -\n drivers/net/qede/qede_main.c                  |   3 +-\n 15 files changed, 1414 insertions(+), 17 deletions(-)",
    "diff": "diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\nindex 54e5e4f98..45557fe3c 100644\n--- a/drivers/net/qede/base/bcm_osal.c\n+++ b/drivers/net/qede/base/bcm_osal.c\n@@ -289,3 +289,9 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length)\n \t}\n \treturn crc;\n }\n+\n+void qed_set_platform_str(struct ecore_hwfn *p_hwfn,\n+\t\t\t  char *buf_str, u32 buf_size)\n+{\n+\tsnprintf(buf_str, buf_size, \"%s.\", rte_version());\n+}\ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 88a2500a5..6ea3e7dda 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -8,6 +8,7 @@\n #define __BCM_OSAL_H\n \n #include <stdbool.h>\n+#include <time.h>\n #include <rte_bitops.h>\n #include <rte_byteorder.h>\n #include <rte_spinlock.h>\n@@ -19,6 +20,7 @@\n #include <rte_debug.h>\n #include <rte_ether.h>\n #include <rte_io.h>\n+#include <rte_version.h>\n \n /* Forward declaration */\n struct ecore_dev;\n@@ -450,7 +452,11 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length);\n \n #define OSAL_DIV_S64(a, b)\t((a) / (b))\n #define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing\n-#define OSAL_GET_EPOCH(p_hwfn)\t0\n+void qed_set_platform_str(struct ecore_hwfn *p_hwfn,\n+\t\t\t  char *buf_str, u32 buf_size);\n+#define OSAL_SET_PLATFORM_STR(p_hwfn, buf_str, buf_size) \\\n+\tqed_set_platform_str(p_hwfn, buf_str, buf_size)\n+#define OSAL_GET_EPOCH(p_hwfn) ((u32)time(NULL))\n #define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0)\n #define OSAL_DB_REC_OCCURRED(p_hwfn) nothing\n \ndiff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h\nindex e230fe5ac..1a02d460b 100644\n--- a/drivers/net/qede/base/common_hsi.h\n+++ b/drivers/net/qede/base/common_hsi.h\n@@ -145,6 +145,7 @@\n #define NUM_OF_CONNECTION_TYPES (8)\n #define NUM_OF_TASK_TYPES       (8)\n #define NUM_OF_LCIDS            (320)\n+#define NUM_OF_LTIDS            (320)\n \n /* Global PXP windows (GTT) */\n #define NUM_OF_GTT          19\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex dc5fe4d80..63bd7466a 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -576,6 +576,12 @@ enum BAR_ID {\n \tBAR_ID_1\t/* Used for doorbells */\n };\n \n+struct ecore_nvm_image_info {\n+\tu32\t\t\t\tnum_images;\n+\tstruct bist_nvm_image_att\t*image_att;\n+\tbool\t\t\t\tvalid;\n+};\n+\n struct ecore_hwfn {\n \tstruct ecore_dev\t\t*p_dev;\n \tu8\t\t\t\tmy_id;\t\t/* ID inside the PF */\n@@ -701,6 +707,9 @@ struct ecore_hwfn {\n \t */\n \tbool b_en_pacing;\n \n+\t/* Nvm images number and attributes */\n+\tstruct ecore_nvm_image_info     nvm_info;\n+\n \tstruct phys_mem_desc            *fw_overlay_mem;\n \n \t/* @DPDK */\n@@ -714,26 +723,34 @@ enum ecore_mf_mode {\n \tECORE_MF_UFP,\n };\n \n-/* @DPDK */\n-struct ecore_dbg_feature {\n-\tu8\t\t\t\t*dump_buf;\n-\tu32\t\t\t\tbuf_size;\n-\tu32\t\t\t\tdumped_dwords;\n+enum ecore_dev_type {\n+\tECORE_DEV_TYPE_BB,\n+\tECORE_DEV_TYPE_AH,\n };\n \n-enum qed_dbg_features {\n-\tDBG_FEATURE_BUS,\n+/* @DPDK */\n+enum ecore_dbg_features {\n \tDBG_FEATURE_GRC,\n \tDBG_FEATURE_IDLE_CHK,\n \tDBG_FEATURE_MCP_TRACE,\n \tDBG_FEATURE_REG_FIFO,\n+\tDBG_FEATURE_IGU_FIFO,\n \tDBG_FEATURE_PROTECTION_OVERRIDE,\n+\tDBG_FEATURE_FW_ASSERTS,\n+\tDBG_FEATURE_ILT,\n \tDBG_FEATURE_NUM\n };\n \n-enum ecore_dev_type {\n-\tECORE_DEV_TYPE_BB,\n-\tECORE_DEV_TYPE_AH,\n+struct ecore_dbg_feature {\n+\tu8\t\t\t\t*dump_buf;\n+\tu32\t\t\t\tbuf_size;\n+\tu32\t\t\t\tdumped_dwords;\n+};\n+\n+struct ecore_dbg_params {\n+\tstruct ecore_dbg_feature features[DBG_FEATURE_NUM];\n+\tu8 engine_for_debug;\n+\tbool print_data;\n };\n \n struct ecore_dev {\n@@ -914,10 +931,12 @@ struct ecore_dev {\n \tvoid\t\t\t\t*firmware;\n \tu64\t\t\t\tfw_len;\n #endif\n+\tbool\t\t\t\tdisable_ilt_dump;\n \n \t/* @DPDK */\n \tstruct ecore_dbg_feature\tdbg_features[DBG_FEATURE_NUM];\n-\tu8\t\t\t\tengine_for_debug;\n+\tstruct ecore_dbg_params\t\tdbg_params;\n+\tosal_mutex_t\t\t\tdbg_lock;\n };\n \n enum ecore_hsi_def_type {\n@@ -1067,6 +1086,17 @@ enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,\n enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);\n enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);\n \n+/**\n+ * @brief ecore_set_platform_str - Set the debug dump platform string.\n+ * Write the ecore version and device's string to the given buffer.\n+ *\n+ * @param p_hwfn\n+ * @param buf_str\n+ * @param buf_size\n+ */\n+void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,\n+\t\t\t    char *buf_str, u32 buf_size);\n+\n #define TSTORM_QZONE_START\tPXP_VF_BAR0_START_SDM_ZONE_A\n \n #define MSTORM_QZONE_START(dev) \\\ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex 23f37b1bf..d3025724b 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -2186,3 +2186,63 @@ static u16 ecore_blk_calculate_pages(struct ecore_ilt_cli_blk *p_blk)\n \n \treturn DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);\n }\n+\n+u16 ecore_get_cdut_num_pf_init_pages(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct ecore_ilt_client_cfg *p_cli;\n+\tstruct ecore_ilt_cli_blk *p_blk;\n+\tu16 i, pages = 0;\n+\n+\tp_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];\n+\tfor (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {\n+\t\tp_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];\n+\t\tpages += ecore_blk_calculate_pages(p_blk);\n+\t}\n+\n+\treturn pages;\n+}\n+\n+u16 ecore_get_cdut_num_vf_init_pages(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct ecore_ilt_client_cfg *p_cli;\n+\tstruct ecore_ilt_cli_blk *p_blk;\n+\tu16 i, pages = 0;\n+\n+\tp_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];\n+\tfor (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {\n+\t\tp_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)];\n+\t\tpages += ecore_blk_calculate_pages(p_blk);\n+\t}\n+\n+\treturn pages;\n+}\n+\n+u16 ecore_get_cdut_num_pf_work_pages(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct ecore_ilt_client_cfg *p_cli;\n+\tstruct ecore_ilt_cli_blk *p_blk;\n+\tu16 i, pages = 0;\n+\n+\tp_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];\n+\tfor (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {\n+\t\tp_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];\n+\t\tpages += ecore_blk_calculate_pages(p_blk);\n+\t}\n+\n+\treturn pages;\n+}\n+\n+u16 ecore_get_cdut_num_vf_work_pages(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct ecore_ilt_client_cfg *p_cli;\n+\tstruct ecore_ilt_cli_blk *p_blk;\n+\tu16 pages = 0, i;\n+\n+\tp_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];\n+\tfor (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {\n+\t\tp_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)];\n+\t\tpages += ecore_blk_calculate_pages(p_blk);\n+\t}\n+\n+\treturn pages;\n+}\ndiff --git a/drivers/net/qede/base/ecore_cxt.h b/drivers/net/qede/base/ecore_cxt.h\nindex 7b91b953e..80fe39ac0 100644\n--- a/drivers/net/qede/base/ecore_cxt.h\n+++ b/drivers/net/qede/base/ecore_cxt.h\n@@ -345,4 +345,9 @@ struct ecore_cxt_mngr {\n \tu16\t\t\t\ttask_ctx_size;\n \tu16\t\t\t\tconn_ctx_size;\n };\n+\n+u16 ecore_get_cdut_num_pf_init_pages(struct ecore_hwfn *p_hwfn);\n+u16 ecore_get_cdut_num_vf_init_pages(struct ecore_hwfn *p_hwfn);\n+u16 ecore_get_cdut_num_pf_work_pages(struct ecore_hwfn *p_hwfn);\n+u16 ecore_get_cdut_num_vf_work_pages(struct ecore_hwfn *p_hwfn);\n #endif /* _ECORE_CID_ */\ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 814d9ced6..35a8394de 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -6798,6 +6798,19 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb,\n \t((u8 *)fw_lsb)[1] = mac[4];\n }\n \n+void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,\n+\t\t\t    char *buf_str, u32 buf_size)\n+{\n+\tu32 len;\n+\n+\tOSAL_SNPRINTF(buf_str, buf_size, \"Ecore %d.%d.%d.%d. \",\n+\t\t      ECORE_MAJOR_VERSION, ECORE_MINOR_VERSION,\n+\t\t      ECORE_REVISION_VERSION, ECORE_ENGINEERING_VERSION);\n+\n+\tlen = OSAL_STRLEN(buf_str);\n+\tOSAL_SET_PLATFORM_STR(p_hwfn, &buf_str[len], buf_size - len);\n+}\n+\n bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)\n {\n \treturn !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);\ndiff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h\nindex 23cfcdeff..578c798a9 100644\n--- a/drivers/net/qede/base/ecore_hsi_common.h\n+++ b/drivers/net/qede/base/ecore_hsi_common.h\n@@ -10,6 +10,7 @@\n /* Add include to common target */\n /********************************/\n #include \"common_hsi.h\"\n+#include \"mcp_public.h\"\n \n \n /*\n@@ -2229,7 +2230,40 @@ struct fw_info_location {\n };\n \n \n-\n+/* DMAE parameters */\n+struct ecore_dmae_params {\n+\tu32 flags;\n+/* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the\n+ * source is a block of length DMAE_MAX_RW_SIZE and the\n+ * destination is larger, the source block will be duplicated as\n+ * many times as required to fill the destination block. This is\n+ * used mostly to write a zeroed buffer to destination address\n+ * using DMA\n+ */\n+#define ECORE_DMAE_PARAMS_RW_REPL_SRC_MASK        0x1\n+#define ECORE_DMAE_PARAMS_RW_REPL_SRC_SHIFT       0\n+#define ECORE_DMAE_PARAMS_SRC_VF_VALID_MASK       0x1\n+#define ECORE_DMAE_PARAMS_SRC_VF_VALID_SHIFT      1\n+#define ECORE_DMAE_PARAMS_DST_VF_VALID_MASK       0x1\n+#define ECORE_DMAE_PARAMS_DST_VF_VALID_SHIFT      2\n+#define ECORE_DMAE_PARAMS_COMPLETION_DST_MASK     0x1\n+#define ECORE_DMAE_PARAMS_COMPLETION_DST_SHIFT    3\n+#define ECORE_DMAE_PARAMS_PORT_VALID_MASK         0x1\n+#define ECORE_DMAE_PARAMS_PORT_VALID_SHIFT        4\n+#define ECORE_DMAE_PARAMS_SRC_PF_VALID_MASK       0x1\n+#define ECORE_DMAE_PARAMS_SRC_PF_VALID_SHIFT      5\n+#define ECORE_DMAE_PARAMS_DST_PF_VALID_MASK       0x1\n+#define ECORE_DMAE_PARAMS_DST_PF_VALID_SHIFT      6\n+#define ECORE_DMAE_PARAMS_RESERVED_MASK           0x1FFFFFF\n+#define ECORE_DMAE_PARAMS_RESERVED_SHIFT          7\n+\tu8 src_vfid;\n+\tu8 dst_vfid;\n+\tu8 port_id;\n+\tu8 src_pfid;\n+\tu8 dst_pfid;\n+\tu8 reserved1;\n+\t__le16 reserved2;\n+};\n \n /*\n  * IGU cleanup command\n@@ -2543,4 +2577,152 @@ struct ystorm_core_conn_ag_ctx {\n \t__le32 reg3 /* reg3 */;\n };\n \n+/*********/\n+/* DEBUG */\n+/*********/\n+\n+#define MFW_TRACE_SIGNATURE\t0x25071946\n+\n+/* The trace in the buffer */\n+#define MFW_TRACE_EVENTID_MASK\t\t0x00ffff\n+#define MFW_TRACE_PRM_SIZE_MASK\t\t0x0f0000\n+#define MFW_TRACE_PRM_SIZE_OFFSET\t16\n+#define MFW_TRACE_ENTRY_SIZE\t\t3\n+\n+struct mcp_trace {\n+\tu32\tsignature;\t/* Help to identify that the trace is valid */\n+\tu32\tsize;\t\t/* the size of the trace buffer in bytes*/\n+\tu32\tcurr_level;\t/* 2 - all will be written to the buffer\n+\t\t\t\t * 1 - debug trace will not be written\n+\t\t\t\t * 0 - just errors will be written to the buffer\n+\t\t\t\t */\n+\t/* a bit per module, 1 means mask it off, 0 means add it to the trace\n+\t * buffer\n+\t */\n+\tu32\tmodules_mask[2];\n+\n+\t/* Warning: the following pointers are assumed to be 32bits as they are\n+\t * used only in the MFW\n+\t */\n+\t/* The next trace will be written to this offset */\n+\tu32\ttrace_prod;\n+\t/* The oldest valid trace starts at this offset (usually very close\n+\t * after the current producer)\n+\t */\n+\tu32\ttrace_oldest;\n+};\n+\n+enum spad_sections {\n+\tSPAD_SECTION_TRACE,\n+\tSPAD_SECTION_NVM_CFG,\n+\tSPAD_SECTION_PUBLIC,\n+\tSPAD_SECTION_PRIVATE,\n+\tSPAD_SECTION_MAX\n+};\n+\n+#define MCP_TRACE_SIZE          2048    /* 2kb */\n+\n+/* This section is located at a fixed location in the beginning of the\n+ * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.\n+ * All the rest of data has a floating location which differs from version to\n+ * version, and is pointed by the mcp_meta_data below.\n+ * Moreover, the spad_layout section is part of the MFW firmware, and is loaded\n+ * with it from nvram in order to clear this portion.\n+ */\n+struct static_init {\n+\tu32 num_sections;\n+\toffsize_t sections[SPAD_SECTION_MAX];\n+#define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))\n+\n+\tstruct mcp_trace trace;\n+#define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))\n+\tu8 trace_buffer[MCP_TRACE_SIZE];\n+#define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))\n+\t/* running_mfw has the same definition as in nvm_map.h.\n+\t * This bit indicate both the running dir, and the running bundle.\n+\t * It is set once when the LIM is loaded.\n+\t */\n+\tu32 running_mfw;\n+#define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))\n+\tu32 build_time;\n+#define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))\n+\tu32 reset_type;\n+#define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))\n+\tu32 mfw_secure_mode;\n+#define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))\n+\tu16 pme_status_pf_bitmap;\n+#define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))\n+\tu16 pme_enable_pf_bitmap;\n+#define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))\n+\tu32 mim_nvm_addr;\n+\tu32 mim_start_addr;\n+\tu32 ah_pcie_link_params;\n+#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)\n+#define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)\n+#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)\n+#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)\n+#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)\n+#define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)\n+#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)\n+#define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)\n+#define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))\n+\n+\tu32 rsrv_persist[5];\t/* Persist reserved for MFW upgrades */\n+};\n+\n+#define NVM_MAGIC_VALUE\t\t0x669955aa\n+\n+enum nvm_image_type {\n+\tNVM_TYPE_TIM1 = 0x01,\n+\tNVM_TYPE_TIM2 = 0x02,\n+\tNVM_TYPE_MIM1 = 0x03,\n+\tNVM_TYPE_MIM2 = 0x04,\n+\tNVM_TYPE_MBA = 0x05,\n+\tNVM_TYPE_MODULES_PN = 0x06,\n+\tNVM_TYPE_VPD = 0x07,\n+\tNVM_TYPE_MFW_TRACE1 = 0x08,\n+\tNVM_TYPE_MFW_TRACE2 = 0x09,\n+\tNVM_TYPE_NVM_CFG1 = 0x0a,\n+\tNVM_TYPE_L2B = 0x0b,\n+\tNVM_TYPE_DIR1 = 0x0c,\n+\tNVM_TYPE_EAGLE_FW1 = 0x0d,\n+\tNVM_TYPE_FALCON_FW1 = 0x0e,\n+\tNVM_TYPE_PCIE_FW1 = 0x0f,\n+\tNVM_TYPE_HW_SET = 0x10,\n+\tNVM_TYPE_LIM = 0x11,\n+\tNVM_TYPE_AVS_FW1 = 0x12,\n+\tNVM_TYPE_DIR2 = 0x13,\n+\tNVM_TYPE_CCM = 0x14,\n+\tNVM_TYPE_EAGLE_FW2 = 0x15,\n+\tNVM_TYPE_FALCON_FW2 = 0x16,\n+\tNVM_TYPE_PCIE_FW2 = 0x17,\n+\tNVM_TYPE_AVS_FW2 = 0x18,\n+\tNVM_TYPE_INIT_HW = 0x19,\n+\tNVM_TYPE_DEFAULT_CFG = 0x1a,\n+\tNVM_TYPE_MDUMP = 0x1b,\n+\tNVM_TYPE_META = 0x1c,\n+\tNVM_TYPE_ISCSI_CFG = 0x1d,\n+\tNVM_TYPE_FCOE_CFG = 0x1f,\n+\tNVM_TYPE_ETH_PHY_FW1 = 0x20,\n+\tNVM_TYPE_ETH_PHY_FW2 = 0x21,\n+\tNVM_TYPE_BDN = 0x22,\n+\tNVM_TYPE_8485X_PHY_FW = 0x23,\n+\tNVM_TYPE_PUB_KEY = 0x24,\n+\tNVM_TYPE_RECOVERY = 0x25,\n+\tNVM_TYPE_PLDM = 0x26,\n+\tNVM_TYPE_UPK1 = 0x27,\n+\tNVM_TYPE_UPK2 = 0x28,\n+\tNVM_TYPE_MASTER_KC = 0x29,\n+\tNVM_TYPE_BACKUP_KC = 0x2a,\n+\tNVM_TYPE_HW_DUMP = 0x2b,\n+\tNVM_TYPE_HW_DUMP_OUT = 0x2c,\n+\tNVM_TYPE_BIN_NVM_META = 0x30,\n+\tNVM_TYPE_ROM_TEST = 0xf0,\n+\tNVM_TYPE_88X33X0_PHY_FW = 0x31,\n+\tNVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,\n+\tNVM_TYPE_MAX,\n+};\n+\n+#define DIR_ID_1    (0)\n+\n #endif /* __ECORE_HSI_COMMON__ */\ndiff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h\nindex eb72e93cf..c5ef67f84 100644\n--- a/drivers/net/qede/base/ecore_hsi_debug_tools.h\n+++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h\n@@ -245,6 +245,7 @@ struct dbg_mode_hdr {\n  * Attention register\n  */\n struct dbg_attn_reg {\n+\tstruct dbg_mode_hdr mode /* Mode header */;\n /* The offset of this registers attentions within the blocks attentions list\n  * (a value in the range 0..number of block attentions-1)\n  */\n@@ -1049,5 +1050,4 @@ struct dbg_tools_data {\n };\n \n \n-\n #endif /* __ECORE_HSI_DEBUG_TOOLS__ */\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 0a9e26805..cab089d81 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -3621,6 +3621,217 @@ enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(\n \treturn rc;\n }\n \n+enum _ecore_status_t\n+ecore_mcp_bist_nvm_get_num_images(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t  struct ecore_ptt *p_ptt, u32 *num_images)\n+{\n+\tu32 drv_mb_param = 0, rsp;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tSET_MFW_FIELD(drv_mb_param, DRV_MB_PARAM_BIST_TEST_INDEX,\n+\t\t      DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES);\n+\n+\trc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,\n+\t\t\t   drv_mb_param, &rsp, num_images);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tif (rsp == FW_MSG_CODE_UNSUPPORTED)\n+\t\trc = ECORE_NOTIMPL;\n+\telse if (rsp != FW_MSG_CODE_OK)\n+\t\trc = ECORE_UNKNOWN_ERROR;\n+\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t\n+ecore_mcp_bist_nvm_get_image_att(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t struct bist_nvm_image_att *p_image_att,\n+\t\t\t\t u32 image_index)\n+{\n+\tu32 buf_size, nvm_offset = 0, resp, param;\n+\tenum _ecore_status_t rc;\n+\n+\tSET_MFW_FIELD(nvm_offset, DRV_MB_PARAM_BIST_TEST_INDEX,\n+\t\t      DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX);\n+\tSET_MFW_FIELD(nvm_offset, DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX,\n+\t\t      image_index);\n+\trc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,\n+\t\t\t\t  nvm_offset, &resp, &param, &buf_size,\n+\t\t\t\t  (u32 *)p_image_att);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tif (resp == FW_MSG_CODE_UNSUPPORTED)\n+\t\trc = ECORE_NOTIMPL;\n+\telse if ((resp != FW_MSG_CODE_OK) || (p_image_att->return_code != 1))\n+\t\trc = ECORE_UNKNOWN_ERROR;\n+\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t ecore_mcp_nvm_info_populate(struct ecore_hwfn *p_hwfn)\n+{\n+\tstruct ecore_nvm_image_info nvm_info;\n+\tstruct ecore_ptt *p_ptt;\n+\tenum _ecore_status_t rc;\n+\tu32 i;\n+\n+\tif (p_hwfn->nvm_info.valid)\n+\t\treturn ECORE_SUCCESS;\n+\n+#ifndef ASIC_ONLY\n+\tif (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ||\n+\t    CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))\n+\t\treturn ECORE_SUCCESS;\n+#endif\n+\n+\tp_ptt = ecore_ptt_acquire(p_hwfn);\n+\tif (!p_ptt) {\n+\t\tDP_ERR(p_hwfn, \"failed to acquire ptt\\n\");\n+\t\treturn ECORE_BUSY;\n+\t}\n+\n+\t/* Acquire from MFW the amount of available images */\n+\tOSAL_MEM_ZERO(&nvm_info, sizeof(nvm_info));\n+\trc = ecore_mcp_bist_nvm_get_num_images(p_hwfn, p_ptt,\n+\t\t\t\t\t       &nvm_info.num_images);\n+\tif (rc == ECORE_NOTIMPL) {\n+\t\tDP_INFO(p_hwfn, \"DRV_MSG_CODE_BIST_TEST is not supported\\n\");\n+\t\tgoto out;\n+\t} else if ((rc != ECORE_SUCCESS) || (nvm_info.num_images == 0)) {\n+\t\tDP_ERR(p_hwfn, \"Failed getting number of images\\n\");\n+\t\tgoto err0;\n+\t}\n+\n+\tnvm_info.image_att = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,\n+\t\t\t\t\t nvm_info.num_images *\n+\t\t\t\t\t sizeof(struct bist_nvm_image_att));\n+\tif (!nvm_info.image_att) {\n+\t\trc = ECORE_NOMEM;\n+\t\tgoto err0;\n+\t}\n+\n+\t/* Iterate over images and get their attributes */\n+\tfor (i = 0; i < nvm_info.num_images; i++) {\n+\t\trc = ecore_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,\n+\t\t\t\t\t\t      &nvm_info.image_att[i],\n+\t\t\t\t\t\t      i);\n+\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\tDP_ERR(p_hwfn,\n+\t\t\t       \"Failed getting image index %d attributes\\n\",\n+\t\t\t       i);\n+\t\t\tgoto err1;\n+\t\t}\n+\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_SP, \"image index %d, size %x\\n\", i,\n+\t\t\t   nvm_info.image_att[i].len);\n+\t}\n+out:\n+\t/* Update hwfn's nvm_info */\n+\tif (nvm_info.num_images) {\n+\t\tp_hwfn->nvm_info.num_images = nvm_info.num_images;\n+\t\tif (p_hwfn->nvm_info.image_att)\n+\t\t\tOSAL_FREE(p_hwfn->p_dev, p_hwfn->nvm_info.image_att);\n+\t\tp_hwfn->nvm_info.image_att = nvm_info.image_att;\n+\t\tp_hwfn->nvm_info.valid = true;\n+\t}\n+\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\treturn ECORE_SUCCESS;\n+\n+err1:\n+\tOSAL_FREE(p_hwfn->p_dev, nvm_info.image_att);\n+err0:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t\n+ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn,\n+\t\t\t    enum ecore_nvm_images image_id,\n+\t\t\t    struct ecore_nvm_image_att *p_image_att)\n+{\n+\tenum nvm_image_type type;\n+\tu32 i;\n+\n+\t/* Translate image_id into MFW definitions */\n+\tswitch (image_id) {\n+\tcase ECORE_NVM_IMAGE_ISCSI_CFG:\n+\t\ttype = NVM_TYPE_ISCSI_CFG;\n+\t\tbreak;\n+\tcase ECORE_NVM_IMAGE_FCOE_CFG:\n+\t\ttype = NVM_TYPE_FCOE_CFG;\n+\t\tbreak;\n+\tcase ECORE_NVM_IMAGE_MDUMP:\n+\t\ttype = NVM_TYPE_MDUMP;\n+\t\tbreak;\n+\tcase ECORE_NVM_IMAGE_NVM_CFG1:\n+\t\ttype = NVM_TYPE_NVM_CFG1;\n+\t\tbreak;\n+\tcase ECORE_NVM_IMAGE_DEFAULT_CFG:\n+\t\ttype = NVM_TYPE_DEFAULT_CFG;\n+\t\tbreak;\n+\tcase ECORE_NVM_IMAGE_NVM_META:\n+\t\ttype = NVM_TYPE_META;\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_NOTICE(p_hwfn, false, \"Unknown request of image_id %08x\\n\",\n+\t\t\t  image_id);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\tecore_mcp_nvm_info_populate(p_hwfn);\n+\tfor (i = 0; i < p_hwfn->nvm_info.num_images; i++) {\n+\t\tif (type == p_hwfn->nvm_info.image_att[i].image_type)\n+\t\t\tbreak;\n+\t}\n+\tif (i == p_hwfn->nvm_info.num_images) {\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,\n+\t\t\t   \"Failed to find nvram image of type %08x\\n\",\n+\t\t\t   image_id);\n+\t\treturn ECORE_NOENT;\n+\t}\n+\n+\tp_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;\n+\tp_image_att->length = p_hwfn->nvm_info.image_att[i].len;\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t     enum ecore_nvm_images image_id,\n+\t\t\t\t\t     u8 *p_buffer, u32 buffer_len)\n+{\n+\tstruct ecore_nvm_image_att image_att;\n+\tenum _ecore_status_t rc;\n+\n+\tOSAL_MEM_ZERO(p_buffer, buffer_len);\n+\n+\trc = ecore_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t/* Validate sizes - both the image's and the supplied buffer's */\n+\tif (image_att.length <= 4) {\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,\n+\t\t\t   \"Image [%d] is too small - only %d bytes\\n\",\n+\t\t\t   image_id, image_att.length);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\tif (image_att.length > buffer_len) {\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,\n+\t\t\t   \"Image [%d] is too big - %08x bytes where only %08x are available\\n\",\n+\t\t\t   image_id, image_att.length, buffer_len);\n+\t\treturn ECORE_NOMEM;\n+\t}\n+\n+\treturn ecore_mcp_nvm_read(p_hwfn->p_dev, image_att.start_addr,\n+\t\t\t\t  (u8 *)p_buffer, image_att.length);\n+}\n+\n enum _ecore_status_t\n ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,\n \t\t\t       struct ecore_ptt *p_ptt,\ndiff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h\nindex dc889ab8e..53c130be7 100644\n--- a/drivers/net/qede/base/ecore_mcp_api.h\n+++ b/drivers/net/qede/base/ecore_mcp_api.h\n@@ -121,6 +121,10 @@ struct ecore_mcp_function_info {\n enum ecore_nvm_images {\n \tECORE_NVM_IMAGE_ISCSI_CFG,\n \tECORE_NVM_IMAGE_FCOE_CFG,\n+\tECORE_NVM_IMAGE_MDUMP,\n+\tECORE_NVM_IMAGE_NVM_CFG1,\n+\tECORE_NVM_IMAGE_DEFAULT_CFG,\n+\tECORE_NVM_IMAGE_NVM_META,\n };\n #endif\n \n@@ -970,6 +974,39 @@ enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,\n enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,\n \t\t\t   u8 *p_buf, u32 len);\n \n+struct ecore_nvm_image_att {\n+\tu32 start_addr;\n+\tu32 length;\n+};\n+\n+/**\n+ * @brief Allows reading a whole nvram image\n+ *\n+ * @param p_hwfn\n+ * @param image_id - image to get attributes for\n+ * @param p_image_att - image attributes structure into which to fill data\n+ *\n+ * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.\n+ */\n+enum _ecore_status_t\n+ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn,\n+\t\t\t    enum ecore_nvm_images image_id,\n+\t\t\t    struct ecore_nvm_image_att *p_image_att);\n+\n+/**\n+ * @brief Allows reading a whole nvram image\n+ *\n+ * @param p_hwfn\n+ * @param image_id - image requested for reading\n+ * @param p_buffer - allocated buffer into which to fill data\n+ * @param buffer_len - length of the allocated buffer.\n+ *\n+ * @return ECORE_SUCCESS iff p_buffer now contains the nvram image.\n+ */\n+enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t     enum ecore_nvm_images image_id,\n+\t\t\t\t\t     u8 *p_buffer, u32 buffer_len);\n+\n /**\n  * @brief - Sends an NVM write command request to the MFW with\n  *          payload.\ndiff --git a/drivers/net/qede/base/ecore_status.h b/drivers/net/qede/base/ecore_status.h\nindex b893f1d41..01cf9fd31 100644\n--- a/drivers/net/qede/base/ecore_status.h\n+++ b/drivers/net/qede/base/ecore_status.h\n@@ -8,6 +8,8 @@\n #define __ECORE_STATUS_H__\n \n enum _ecore_status_t {\n+\tECORE_NOENT = -15,\n+\tECORE_CONN_REFUSED = -14,\n \tECORE_CONN_RESET = -13,\n \tECORE_UNKNOWN_ERROR  = -12,\n \tECORE_NORESOURCES\t = -11,\ndiff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h\nindex 91d889dc8..c84d3865f 100644\n--- a/drivers/net/qede/base/reg_addr.h\n+++ b/drivers/net/qede/base/reg_addr.h\n@@ -1245,3 +1245,849 @@\n #define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL\n #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL\n #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL\n+\n+#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB 15200\n+#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 22000\n+#define TSEM_REG_DBG_GPRE_VECT 0x1701410UL\n+#define MSEM_REG_DBG_GPRE_VECT 0x1801410UL\n+#define USEM_REG_DBG_GPRE_VECT 0x1901410UL\n+#define XSEM_REG_DBG_GPRE_VECT 0x1401410UL\n+#define YSEM_REG_DBG_GPRE_VECT 0x1501410UL\n+#define PSEM_REG_DBG_GPRE_VECT 0x1601410UL\n+#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE 0x000748UL\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE (0x1UL << 0)\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE_SHIFT 0\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE (0x1UL << 1)\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE_SHIFT 1\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE (0x1UL << 2)\n+  #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE_SHIFT 2\n+#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE 0x00074cUL\n+  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE (0x1UL << 0)\n+  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE_SHIFT 0\n+  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE (0x1UL << 1)\n+  #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE_SHIFT 1\n+#define NWS_REG_NWS_CMU_K2 0x720000UL\n+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 0x000680UL\n+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 0x000684UL\n+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 0x0006c0UL\n+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 0x0006c4UL\n+#define MS_REG_MS_CMU_K2 0x6a4000UL\n+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL\n+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL\n+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL\n+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL\n+#define PHY_PCIE_REG_PHY0_K2 0x620000UL\n+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL\n+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL\n+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL\n+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL\n+#define PHY_PCIE_REG_PHY1_K2 0x624000UL\n+#define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2 0x054364UL\n+#define PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2 0x05436cUL\n+#define RDIF_REG_DEBUG_ERROR_INFO 0x300400UL\n+#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64\n+#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64\n+#define TDIF_REG_DEBUG_ERROR_INFO 0x310400UL\n+#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64\n+#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64\n+#define SEM_FAST_REG_VFC_STATUS 0x000b4cUL\n+  #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY (0x1UL << 0)\n+  #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY_SHIFT 0\n+  #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY (0x1UL << 1)\n+  #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY_SHIFT 1\n+  #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING (0x1UL << 2)\n+  #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING_SHIFT 2\n+#define RSS_REG_RSS_RAM_DATA_SIZE 4\n+#define BRB_REG_BIG_RAM_DATA_SIZE 64\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_1 0x0084c0UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_2 0x0084e4UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_3 0x008508UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_4 0x00852cUL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_5 0x008550UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_6 0x008574UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_IGU_OUT_7 0x008598UL\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_NIG 0x0085bcUL\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_NIG_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_PXP 0x0085e0UL\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_PXP_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_MCP_OUT_0 0x008628UL\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR 0x008748UL\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31_SHIFT 31\n+#define MISC_REG_AEU_ENABLE1_SYS_KILL 0x008604UL\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0 (0x1UL << 0)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0_SHIFT 0\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1 (0x1UL << 1)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1_SHIFT 1\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2 (0x1UL << 2)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2_SHIFT 2\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3 (0x1UL << 3)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3_SHIFT 3\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4 (0x1UL << 4)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4_SHIFT 4\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5 (0x1UL << 5)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5_SHIFT 5\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6 (0x1UL << 6)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6_SHIFT 6\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO (0x1UL << 7)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO_SHIFT 7\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8 (0x1UL << 8)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8_SHIFT 8\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9 (0x1UL << 9)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9_SHIFT 9\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10 (0x1UL << 10)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10_SHIFT 10\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11 (0x1UL << 11)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11_SHIFT 11\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12 (0x1UL << 12)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12_SHIFT 12\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13 (0x1UL << 13)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13_SHIFT 13\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14 (0x1UL << 14)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14_SHIFT 14\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15 (0x1UL << 15)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15_SHIFT 15\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16 (0x1UL << 16)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16_SHIFT 16\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17 (0x1UL << 17)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17_SHIFT 17\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18 (0x1UL << 18)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18_SHIFT 18\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19 (0x1UL << 19)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19_SHIFT 19\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20 (0x1UL << 20)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20_SHIFT 20\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21 (0x1UL << 21)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21_SHIFT 21\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22 (0x1UL << 22)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22_SHIFT 22\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23 (0x1UL << 23)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23_SHIFT 23\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24 (0x1UL << 24)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24_SHIFT 24\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25 (0x1UL << 25)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25_SHIFT 25\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26 (0x1UL << 26)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26_SHIFT 26\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27 (0x1UL << 27)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27_SHIFT 27\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28 (0x1UL << 28)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28_SHIFT 28\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29 (0x1UL << 29)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29_SHIFT 29\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30 (0x1UL << 30)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30_SHIFT 30\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31 (0x1UL << 31)\n+  #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31_SHIFT 31\n+#define DBG_REG_FULL_BUFFER_THR 0x01045cUL\n+#define MISC_REG_AEU_MASK_ATTN_MCP 0x008498UL\n+#define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0x008800UL\n+#define MISC_REG_AEU_GENERAL_MASK 0x008828UL\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK (0x1UL << 0)\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT 0\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK (0x1UL << 1)\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT 1\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK (0x1UL << 2)\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT 2\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK (0x1UL << 3)\n+  #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT 3\ndiff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\nindex 7f5a34bcb..b5d6c7c43 100644\n--- a/drivers/net/qede/qede_ethdev.c\n+++ b/drivers/net/qede/qede_ethdev.c\n@@ -7,7 +7,6 @@\n #include \"qede_ethdev.h\"\n #include <rte_string_fns.h>\n #include <rte_alarm.h>\n-#include <rte_version.h>\n #include <rte_kvargs.h>\n \n static const struct qed_eth_ops *qed_ops;\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 02f70beb3..51aa639c6 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -5,7 +5,6 @@\n  */\n \n #include <limits.h>\n-#include <time.h>\n #include <rte_alarm.h>\n #include <rte_string_fns.h>\n \n@@ -66,7 +65,7 @@ qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,\n \thw_prepare_params.initiate_pf_flr = true;\n \thw_prepare_params.allow_mdump = false;\n \thw_prepare_params.b_en_pacing = false;\n-\thw_prepare_params.epoch = (u32)time(NULL);\n+\thw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev));\n \trc = ecore_hw_prepare(edev, &hw_prepare_params);\n \tif (rc) {\n \t\tDP_ERR(edev, \"hw prepare failed\\n\");\n",
    "prefixes": [
        "v3",
        "2/4"
    ]
}