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GET /api/patches/73460/?format=api
{ "id": 73460, "url": "https://patches.dpdk.org/api/patches/73460/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1594137293-22468-4-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594137293-22468-4-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594137293-22468-4-git-send-email-phil.yang@arm.com", "date": "2020-07-07T15:54:53", "name": "[v4,4/4] eventdev: relax smp barriers with C11 atomics", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a630828363a30fe1c9b3a77522bc61a1ad221b50", "submitter": { "id": 833, "url": "https://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1594137293-22468-4-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 10861, "url": "https://patches.dpdk.org/api/series/10861/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10861", "date": "2020-07-07T15:54:50", "name": "[v4,1/4] eventdev: fix race condition on timer list counter", "version": 4, "mbox": "https://patches.dpdk.org/series/10861/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/73460/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/73460/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9C258A00BE;\n\tTue, 7 Jul 2020 17:55:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C5D901DED5;\n\tTue, 7 Jul 2020 17:55:36 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id CE21A1DEC3;\n Tue, 7 Jul 2020 17:55:33 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45C65113E;\n Tue, 7 Jul 2020 08:55:33 -0700 (PDT)", "from phil-VirtualBox.arm.com (A010647.Arm.com [10.170.226.105])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E05973F68F;\n Tue, 7 Jul 2020 08:55:28 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "jerinj@marvell.com,\n\tdev@dpdk.org", "Cc": "thomas@monjalon.net, erik.g.carrillo@intel.com,\n Honnappa.Nagarahalli@arm.com, drc@linux.vnet.ibm.com, Ruifeng.Wang@arm.com,\n Dharmik.Thakkar@arm.com, nd@arm.com, david.marchand@redhat.com,\n mdr@ashroe.eu, nhorman@tuxdriver.com, dodji@redhat.com, stable@dpdk.org", "Date": "Tue, 7 Jul 2020 23:54:53 +0800", "Message-Id": "<1594137293-22468-4-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1594137293-22468-1-git-send-email-phil.yang@arm.com>", "References": "<1594120403-17643-1-git-send-email-phil.yang@arm.com>\n <1594137293-22468-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH v4 4/4] eventdev: relax smp barriers with C11\n\tatomics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The impl_opaque field is shared between the timer arm and cancel\noperations. Meanwhile, the state flag acts as a guard variable to\nmake sure the update of impl_opaque is synchronized. The original\ncode uses rte_smp barriers to achieve that. This patch uses C11\natomics with an explicit one-way memory barrier instead of full\nbarriers rte_smp_w/rmb() to avoid the unnecessary barrier on aarch64.\n\nSince compilers can generate the same instructions for volatile and\nnon-volatile variable in C11 __atomics built-ins, so remain the volatile\nkeyword in front of state enum to avoid the ABI break issue.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Dharmik Thakkar <dharmik.thakkar@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nAcked-by: Erik Gabriel Carrillo <erik.g.carrillo@intel.com>\n---\nv4:\n1. Fix typo.\n2. Cc to stable release. (Honnappa)\n\nv3:\nFix ABI issue: revert to 'volatile enum rte_event_timer_state type state'.\n\nv2:\n1. Removed implementation-specific opaque data cleanup code.\n2. Replaced thread fence with atomic ACQURE/RELEASE ordering on state access.\n\n lib/librte_eventdev/rte_event_timer_adapter.c | 55 ++++++++++++++++++---------\n 1 file changed, 37 insertions(+), 18 deletions(-)", "diff": "diff --git a/lib/librte_eventdev/rte_event_timer_adapter.c b/lib/librte_eventdev/rte_event_timer_adapter.c\nindex aa01b4d..4c5e49e 100644\n--- a/lib/librte_eventdev/rte_event_timer_adapter.c\n+++ b/lib/librte_eventdev/rte_event_timer_adapter.c\n@@ -629,7 +629,8 @@ swtim_callback(struct rte_timer *tim)\n \t\tsw->expired_timers[sw->n_expired_timers++] = tim;\n \t\tsw->stats.evtim_exp_count++;\n \n-\t\tevtim->state = RTE_EVENT_TIMER_NOT_ARMED;\n+\t\t__atomic_store_n(&evtim->state, RTE_EVENT_TIMER_NOT_ARMED,\n+\t\t\t\t__ATOMIC_RELEASE);\n \t}\n \n \tif (event_buffer_batch_ready(&sw->buffer)) {\n@@ -1020,6 +1021,7 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter,\n \tint n_lcores;\n \t/* Timer list for this lcore is not in use. */\n \tuint16_t exp_state = 0;\n+\tenum rte_event_timer_state n_state;\n \n #ifdef RTE_LIBRTE_EVENTDEV_DEBUG\n \t/* Check that the service is running. */\n@@ -1060,30 +1062,36 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter,\n \t}\n \n \tfor (i = 0; i < nb_evtims; i++) {\n-\t\t/* Don't modify the event timer state in these cases */\n-\t\tif (evtims[i]->state == RTE_EVENT_TIMER_ARMED) {\n+\t\tn_state = __atomic_load_n(&evtims[i]->state, __ATOMIC_ACQUIRE);\n+\t\tif (n_state == RTE_EVENT_TIMER_ARMED) {\n \t\t\trte_errno = EALREADY;\n \t\t\tbreak;\n-\t\t} else if (!(evtims[i]->state == RTE_EVENT_TIMER_NOT_ARMED ||\n-\t\t\t evtims[i]->state == RTE_EVENT_TIMER_CANCELED)) {\n+\t\t} else if (!(n_state == RTE_EVENT_TIMER_NOT_ARMED ||\n+\t\t\t n_state == RTE_EVENT_TIMER_CANCELED)) {\n \t\t\trte_errno = EINVAL;\n \t\t\tbreak;\n \t\t}\n \n \t\tret = check_timeout(evtims[i], adapter);\n \t\tif (unlikely(ret == -1)) {\n-\t\t\tevtims[i]->state = RTE_EVENT_TIMER_ERROR_TOOLATE;\n+\t\t\t__atomic_store_n(&evtims[i]->state,\n+\t\t\t\t\tRTE_EVENT_TIMER_ERROR_TOOLATE,\n+\t\t\t\t\t__ATOMIC_RELAXED);\n \t\t\trte_errno = EINVAL;\n \t\t\tbreak;\n \t\t} else if (unlikely(ret == -2)) {\n-\t\t\tevtims[i]->state = RTE_EVENT_TIMER_ERROR_TOOEARLY;\n+\t\t\t__atomic_store_n(&evtims[i]->state,\n+\t\t\t\t\tRTE_EVENT_TIMER_ERROR_TOOEARLY,\n+\t\t\t\t\t__ATOMIC_RELAXED);\n \t\t\trte_errno = EINVAL;\n \t\t\tbreak;\n \t\t}\n \n \t\tif (unlikely(check_destination_event_queue(evtims[i],\n \t\t\t\t\t\t\t adapter) < 0)) {\n-\t\t\tevtims[i]->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\t__atomic_store_n(&evtims[i]->state,\n+\t\t\t\t\tRTE_EVENT_TIMER_ERROR,\n+\t\t\t\t\t__ATOMIC_RELAXED);\n \t\t\trte_errno = EINVAL;\n \t\t\tbreak;\n \t\t}\n@@ -1099,13 +1107,18 @@ __swtim_arm_burst(const struct rte_event_timer_adapter *adapter,\n \t\t\t\t\t SINGLE, lcore_id, NULL, evtims[i]);\n \t\tif (ret < 0) {\n \t\t\t/* tim was in RUNNING or CONFIG state */\n-\t\t\tevtims[i]->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\t__atomic_store_n(&evtims[i]->state,\n+\t\t\t\t\tRTE_EVENT_TIMER_ERROR,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\tbreak;\n \t\t}\n \n-\t\trte_smp_wmb();\n \t\tEVTIM_LOG_DBG(\"armed an event timer\");\n-\t\tevtims[i]->state = RTE_EVENT_TIMER_ARMED;\n+\t\t/* RELEASE ordering guarantees the adapter specific value\n+\t\t * changes observed before the update of state.\n+\t\t */\n+\t\t__atomic_store_n(&evtims[i]->state, RTE_EVENT_TIMER_ARMED,\n+\t\t\t\t__ATOMIC_RELEASE);\n \t}\n \n \tif (i < nb_evtims)\n@@ -1132,6 +1145,7 @@ swtim_cancel_burst(const struct rte_event_timer_adapter *adapter,\n \tstruct rte_timer *timp;\n \tuint64_t opaque;\n \tstruct swtim *sw = swtim_pmd_priv(adapter);\n+\tenum rte_event_timer_state n_state;\n \n #ifdef RTE_LIBRTE_EVENTDEV_DEBUG\n \t/* Check that the service is running. */\n@@ -1143,16 +1157,18 @@ swtim_cancel_burst(const struct rte_event_timer_adapter *adapter,\n \n \tfor (i = 0; i < nb_evtims; i++) {\n \t\t/* Don't modify the event timer state in these cases */\n-\t\tif (evtims[i]->state == RTE_EVENT_TIMER_CANCELED) {\n+\t\t/* ACQUIRE ordering guarantees the access of implementation\n+\t\t * specific opaque data under the correct state.\n+\t\t */\n+\t\tn_state = __atomic_load_n(&evtims[i]->state, __ATOMIC_ACQUIRE);\n+\t\tif (n_state == RTE_EVENT_TIMER_CANCELED) {\n \t\t\trte_errno = EALREADY;\n \t\t\tbreak;\n-\t\t} else if (evtims[i]->state != RTE_EVENT_TIMER_ARMED) {\n+\t\t} else if (n_state != RTE_EVENT_TIMER_ARMED) {\n \t\t\trte_errno = EINVAL;\n \t\t\tbreak;\n \t\t}\n \n-\t\trte_smp_rmb();\n-\n \t\topaque = evtims[i]->impl_opaque[0];\n \t\ttimp = (struct rte_timer *)(uintptr_t)opaque;\n \t\tRTE_ASSERT(timp != NULL);\n@@ -1166,9 +1182,12 @@ swtim_cancel_burst(const struct rte_event_timer_adapter *adapter,\n \n \t\trte_mempool_put(sw->tim_pool, (void **)timp);\n \n-\t\tevtims[i]->state = RTE_EVENT_TIMER_CANCELED;\n-\n-\t\trte_smp_wmb();\n+\t\t/* The RELEASE ordering here pairs with atomic ordering\n+\t\t * to make sure the state update data observed between\n+\t\t * threads.\n+\t\t */\n+\t\t__atomic_store_n(&evtims[i]->state, RTE_EVENT_TIMER_CANCELED,\n+\t\t\t\t__ATOMIC_RELEASE);\n \t}\n \n \treturn i;\n", "prefixes": [ "v4", "4/4" ] }