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{
    "id": 73452,
    "url": "https://patches.dpdk.org/api/patches/73452/",
    "web_url": "https://patches.dpdk.org/patch/73452/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200707151601.16500-1-arkadiuszx.kusztal@intel.com>",
    "date": "2020-07-07T15:16:00",
    "name": "[v5,1/2] drivers/qat: add chacha poly implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "3bc954344661c0b9766ac7064b387b9cf44e7e93",
    "submitter": {
        "id": 452,
        "url": "https://patches.dpdk.org/api/people/452/",
        "name": "Kusztal, ArkadiuszX",
        "email": "arkadiuszx.kusztal@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "https://patches.dpdk.org/api/users/6690/",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "akhil.goyal@nxp.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73452/mbox/",
    "series": [
        {
            "id": 10859,
            "url": "https://patches.dpdk.org/api/series/10859/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10859",
            "date": "2020-07-07T15:16:00",
            "name": "[v5,1/2] drivers/qat: add chacha poly implementation",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/10859/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73452/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/73452/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "IronPort-SDR": [
            "\n 3QkvAgl0nPSeh/sZe7bKReEuBgeAqCBElQos7LXLQwi1jAijrB/dV2mM7k0g8Ej5taJKsnGmbk\n cDfoTInFNPUQ==",
            "\n A6k9VH7MtU8+xpKDrZN+DOAUoVU+flQtXEvxkJm8c73Y5jhu4s/cle4OCNwY308gGChEPbPAi5\n 5c3wYLjLA6rw=="
        ],
        "X-Mailer": "git-send-email 2.19.1.windows.1",
        "To": "dev@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8BAFAA00BE;\n\tTue,  7 Jul 2020 17:16:56 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EB5991DEA8;\n\tTue,  7 Jul 2020 17:16:42 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id 438161DEA8\n for <dev@dpdk.org>; Tue,  7 Jul 2020 17:16:41 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Jul 2020 08:16:40 -0700",
            "from akusztax-mobl.ger.corp.intel.com ([10.104.121.84])\n by fmsmga002.fm.intel.com with ESMTP; 07 Jul 2020 08:16:38 -0700"
        ],
        "X-BeenThere": "dev@dpdk.org",
        "X-Amp-File-Uploaded": "False",
        "Subject": "[dpdk-dev] [PATCH v5 1/2] drivers/qat: add chacha poly\n\timplementation",
        "Date": "Tue,  7 Jul 2020 17:16:00 +0200",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Cc": "akhil.goyal@nxp.com, fiona.trahe@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "X-ExtLoop1": "1",
        "Precedence": "list",
        "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "Content-Transfer-Encoding": "8bit",
        "MIME-Version": "1.0",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9675\"; a=\"127209418\"",
            "E=Sophos;i=\"5.75,324,1589266800\"; d=\"scan'208\";a=\"127209418\"",
            "E=Sophos;i=\"5.75,324,1589266800\"; d=\"scan'208\";a=\"315552739\""
        ],
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Errors-To": "dev-bounces@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Message-Id": "<20200707151601.16500-1-arkadiuszx.kusztal@intel.com>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "This patchset adds Chacha20-Poly1305 implementation to Intel\nQuickAssist Technology pmd.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\nThis patch depends on \"drivers/qat: improve handling of multi process\" patchset [1]\n\n[1] http://patchwork.dpdk.org/project/dpdk/list/?series=10855\n\nv5:\n- rebased against changes in qat\n\n doc/guides/cryptodevs/features/qat.ini    |  13 +--\n doc/guides/cryptodevs/qat.rst             |   1 +\n doc/guides/rel_notes/release_20_08.rst    |   4 +\n drivers/common/qat/qat_adf/icp_qat_hw.h   |  10 ++-\n drivers/crypto/qat/qat_sym_capabilities.h |  32 +++++++\n drivers/crypto/qat/qat_sym_pmd.c          |   1 +\n drivers/crypto/qat/qat_sym_session.c      | 141 ++++++++++++++++--------------\n 7 files changed, 127 insertions(+), 75 deletions(-)",
    "diff": "diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini\nindex 2d56b18..9e82f28 100644\n--- a/doc/guides/cryptodevs/features/qat.ini\n+++ b/doc/guides/cryptodevs/features/qat.ini\n@@ -66,12 +66,13 @@ AES CMAC (128) = Y\n ; Supported AEAD algorithms of the 'qat' crypto driver.\n ;\n [AEAD]\n-AES GCM (128) = Y\n-AES GCM (192) = Y\n-AES GCM (256) = Y\n-AES CCM (128) = Y\n-AES CCM (192) = Y\n-AES CCM (256) = Y\n+AES GCM (128)     = Y\n+AES GCM (192)     = Y\n+AES GCM (256)     = Y\n+AES CCM (128)     = Y\n+AES CCM (192)     = Y\n+AES CCM (256)     = Y\n+CHACHA20-POLY1305 = Y\n \n ;\n ; Supported Asymmetric algorithms of the 'qat' crypto driver.\ndiff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex ee873e7..7f4036c 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -75,6 +75,7 @@ Supported AEAD algorithms:\n \n * ``RTE_CRYPTO_AEAD_AES_GCM``\n * ``RTE_CRYPTO_AEAD_AES_CCM``\n+* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``\n \n Protocol offloads:\n \ndiff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst\nindex 3ca2eb2..0a63e0b 100644\n--- a/doc/guides/rel_notes/release_20_08.rst\n+++ b/doc/guides/rel_notes/release_20_08.rst\n@@ -112,6 +112,10 @@ New Features\n   Implemented improvements in handling multi process applications\n   using QAT symmetric/asymmetric crypto and compression services.\n \n+* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.**\n+\n+  Added Chacha20-Poly1305 AEAD algorithm.\n+\n * **Updated the OCTEON TX2 crypto PMD.**\n \n   Added Chacha20-Poly1305 AEAD algorithm support in OCTEON TX2 crypto PMD.\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex cef6486..fdc0f19 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -204,7 +204,9 @@ enum icp_qat_hw_cipher_algo {\n \tICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,\n \tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,\n \tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,\n-\tICP_QAT_HW_CIPHER_DELIMITER = 10\n+\tICP_QAT_HW_CIPHER_ALGO_SM4 = 10,\n+\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11,\n+\tICP_QAT_HW_CIPHER_DELIMITER = 12\n };\n \n enum icp_qat_hw_cipher_mode {\n@@ -306,6 +308,12 @@ enum icp_qat_hw_cipher_convert {\n #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16\n #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16\n #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2\n+#define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32\n+#define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12\n+#define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64\n+#define ICP_QAT_HW_SPC_CTR_SZ 16\n+#define ICP_QAT_HW_CHACHAPOLY_ICV_SZ 16\n+#define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14\n \n #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ\n \ndiff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h\nindex b16581f..4ee7989 100644\n--- a/drivers/crypto/qat/qat_sym_capabilities.h\n+++ b/drivers/crypto/qat/qat_sym_capabilities.h\n@@ -699,6 +699,38 @@\n \t\t}, }\t\t\t\t\t\t\t\\\n \t}\n \n+#define QAT_EXTRA_GEN3_SYM_CAPABILITIES\t\t\t\t\t\\\n+\t{\t/* Chacha20-Poly1305 */\t\t\t\t\t\\\n+\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\t\\\n+\t\t\t{.aead = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, \\\n+\t\t\t\t.block_size = 64,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 32,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 16,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.aad_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 240,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 12,\t\t\t\\\n+\t\t\t\t\t.max = 12,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n #ifdef RTE_LIBRTE_SECURITY\n #define QAT_SECURITY_SYM_CAPABILITIES\t\t\t\t\t\\\n \t{\t/* AES DOCSIS BPI */\t\t\t\t\t\\\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 2dcda4a..36e098a 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -35,6 +35,7 @@ static const struct rte_cryptodev_capabilities qat_gen2_sym_capabilities[] = {\n static const struct rte_cryptodev_capabilities qat_gen3_sym_capabilities[] = {\n \tQAT_BASE_GEN1_SYM_CAPABILITIES,\n \tQAT_EXTRA_GEN2_SYM_CAPABILITIES,\n+\tQAT_EXTRA_GEN3_SYM_CAPABILITIES,\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex c7c2d36..717893c 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -632,69 +632,68 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n }\n \n static int\n-qat_sym_session_handle_single_pass(struct qat_sym_dev_private *internals,\n-\t\tstruct qat_sym_session *session,\n+qat_sym_session_handle_single_pass(struct qat_sym_session *session,\n \t\tstruct rte_crypto_aead_xform *aead_xform)\n {\n-\tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n+\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n+\t\t\t(void *) &session->fw_req.serv_specif_rqpars;\n \n-\tif (qat_dev_gen == QAT_GEN3 &&\n-\t\t\taead_xform->iv.length == QAT_AES_GCM_SPC_IV_SIZE) {\n-\t\t/* Use faster Single-Pass GCM */\n-\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n-\t\t\t\t(void *) &session->fw_req.serv_specif_rqpars;\n-\n-\t\tsession->is_single_pass = 1;\n-\t\tsession->min_qat_dev_gen = QAT_GEN3;\n-\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER;\n+\tsession->is_single_pass = 1;\n+\tsession->min_qat_dev_gen = QAT_GEN3;\n+\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER;\n+\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) {\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_AEAD_MODE;\n-\t\tsession->cipher_iv.offset = aead_xform->iv.offset;\n-\t\tsession->cipher_iv.length = aead_xform->iv.length;\n-\t\tif (qat_sym_session_aead_create_cd_cipher(session,\n-\t\t\t\taead_xform->key.data, aead_xform->key.length))\n-\t\t\treturn -EINVAL;\n-\t\tsession->aad_len = aead_xform->aad_length;\n-\t\tsession->digest_length = aead_xform->digest_length;\n-\t\tif (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n-\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n-\t\t\tsession->auth_op = ICP_QAT_HW_AUTH_GENERATE;\n-\t\t\tICP_QAT_FW_LA_RET_AUTH_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_RET_AUTH_RES);\n-\t\t} else {\n-\t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n-\t\t\tsession->auth_op = ICP_QAT_HW_AUTH_VERIFY;\n-\t\t\tICP_QAT_FW_LA_CMP_AUTH_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_CMP_AUTH_RES);\n-\t\t}\n-\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n-\t\tICP_QAT_FW_LA_PROTO_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n \t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n-\t\tsession->fw_req.comn_hdr.service_cmd_id =\n-\t\t\t\tICP_QAT_FW_LA_CMD_CIPHER;\n-\t\tsession->cd.cipher.cipher_config.val =\n-\t\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD(\n-\t\t\t\t\tICP_QAT_HW_CIPHER_AEAD_MODE,\n-\t\t\t\t\tsession->qat_cipher_alg,\n-\t\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT,\n-\t\t\t\t\tsession->qat_dir);\n-\t\tQAT_FIELD_SET(session->cd.cipher.cipher_config.val,\n-\t\t\t\taead_xform->digest_length,\n-\t\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n-\t\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n-\t\tsession->cd.cipher.cipher_config.reserved =\n-\t\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(\n-\t\t\t\t\taead_xform->aad_length);\n-\t\tcipher_param->spc_aad_sz = aead_xform->aad_length;\n-\t\tcipher_param->spc_auth_res_sz = aead_xform->digest_length;\n+\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n+\t} else {\n+\t\t/* Chacha-Poly is special case that use QAT CTR mode */\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t}\n+\tsession->cipher_iv.offset = aead_xform->iv.offset;\n+\tsession->cipher_iv.length = aead_xform->iv.length;\n+\tif (qat_sym_session_aead_create_cd_cipher(session,\n+\t\t\taead_xform->key.data, aead_xform->key.length))\n+\t\treturn -EINVAL;\n+\tsession->aad_len = aead_xform->aad_length;\n+\tsession->digest_length = aead_xform->digest_length;\n+\tif (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\t\tsession->auth_op = ICP_QAT_HW_AUTH_GENERATE;\n+\t\tICP_QAT_FW_LA_RET_AUTH_SET(\n+\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_RET_AUTH_RES);\n+\t} else {\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\t\tsession->auth_op = ICP_QAT_HW_AUTH_VERIFY;\n+\t\tICP_QAT_FW_LA_CMP_AUTH_SET(\n+\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_CMP_AUTH_RES);\n \t}\n+\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n+\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n+\tICP_QAT_FW_LA_PROTO_SET(\n+\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\tsession->fw_req.comn_hdr.service_cmd_id =\n+\t\t\tICP_QAT_FW_LA_CMD_CIPHER;\n+\tsession->cd.cipher.cipher_config.val =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD(\n+\t\t\t\tICP_QAT_HW_CIPHER_AEAD_MODE,\n+\t\t\t\tsession->qat_cipher_alg,\n+\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT,\n+\t\t\t\tsession->qat_dir);\n+\tQAT_FIELD_SET(session->cd.cipher.cipher_config.val,\n+\t\t\taead_xform->digest_length,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n+\tsession->cd.cipher.cipher_config.reserved =\n+\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(\n+\t\t\t\taead_xform->aad_length);\n+\tcipher_param->spc_aad_sz = aead_xform->aad_length;\n+\tcipher_param->spc_auth_res_sz = aead_xform->digest_length;\n+\n \treturn 0;\n }\n \n@@ -865,6 +864,10 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n {\n \tstruct rte_crypto_aead_xform *aead_xform = &xform->aead;\n \tenum rte_crypto_auth_operation crypto_operation;\n+\tstruct qat_sym_dev_private *internals =\n+\t\t\tdev->data->dev_private;\n+\tenum qat_device_gen qat_dev_gen =\n+\t\t\tinternals->qat_dev->qat_dev_gen;\n \n \t/*\n \t * Store AEAD IV parameters as cipher IV,\n@@ -875,6 +878,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \n \tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n \n+\tsession->is_single_pass = 0;\n \tswitch (aead_xform->algo) {\n \tcase RTE_CRYPTO_AEAD_AES_GCM:\n \t\tif (qat_sym_validate_aes_key(aead_xform->key.length,\n@@ -884,6 +888,11 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n+\t\tif (qat_dev_gen > QAT_GEN2 && aead_xform->iv.length ==\n+\t\t\t\tQAT_AES_GCM_SPC_IV_SIZE) {\n+\t\t\treturn qat_sym_session_handle_single_pass(session,\n+\t\t\t\t\taead_xform);\n+\t\t}\n \t\tif (session->cipher_iv.length == 0)\n \t\t\tsession->cipher_iv.length = AES_GCM_J0_LEN;\n \n@@ -897,23 +906,19 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;\n \t\tbreak;\n+\tcase RTE_CRYPTO_AEAD_CHACHA20_POLY1305:\n+\t\tif (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)\n+\t\t\treturn -EINVAL;\n+\t\tsession->qat_cipher_alg =\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;\n+\t\treturn qat_sym_session_handle_single_pass(session,\n+\t\t\t\t\t\taead_xform);\n \tdefault:\n \t\tQAT_LOG(ERR, \"Crypto: Undefined AEAD specified %u\\n\",\n \t\t\t\taead_xform->algo);\n \t\treturn -EINVAL;\n \t}\n \n-\tsession->is_single_pass = 0;\n-\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t/* Use faster Single-Pass GCM if possible */\n-\t\tint res = qat_sym_session_handle_single_pass(\n-\t\t\t\tdev->data->dev_private, session, aead_xform);\n-\t\tif (res < 0)\n-\t\t\treturn res;\n-\t\tif (session->is_single_pass)\n-\t\t\treturn 0;\n-\t}\n-\n \tif ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n \t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||\n \t\t\t(aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&\n",
    "prefixes": [
        "v5",
        "1/2"
    ]
}