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[
    {
        "id": 115512,
        "web_url": "https://patches.dpdk.org/comment/115512/",
        "msgid": "<b3f83d51-0e0a-49ab-adf3-0b4ae3bdd3e4@intel.com>",
        "date": "2020-07-08T12:37:16",
        "subject": "Re: [dpdk-dev] [PATCH v7 2/3] test/lpm: add LPM RCU integration\n\tfunctional tests",
        "submitter": {
            "id": 1216,
            "url": "https://patches.dpdk.org/api/people/1216/",
            "name": "Vladimir Medvedkin",
            "email": "vladimir.medvedkin@intel.com"
        },
        "content": "Hi Ruifeng,\n\nJust a few nits\n\nOn 07/07/2020 16:15, Ruifeng Wang wrote:\n> Add positive and negative tests for API rte_lpm_rcu_qsbr_add.\n> Also test LPM library behavior when RCU QSBR is enabled.\n>\n> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>\n> Reviewed-by: Gavin Hu <gavin.hu@arm.com>\n> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n> ---\n>   app/test/test_lpm.c | 291 +++++++++++++++++++++++++++++++++++++++++++-\n>   1 file changed, 290 insertions(+), 1 deletion(-)\n>\n> diff --git a/app/test/test_lpm.c b/app/test/test_lpm.c\n> index 3a3fd097f..93742e3c7 100644\n> --- a/app/test/test_lpm.c\n> +++ b/app/test/test_lpm.c\n> @@ -8,6 +8,7 @@\n>   \n>   #include <rte_ip.h>\n>   #include <rte_lpm.h>\n> +#include <rte_malloc.h>\n>   \n>   #include \"test.h\"\n>   #include \"test_xmmt_ops.h\"\n> @@ -40,6 +41,9 @@ static int32_t test15(void);\n>   static int32_t test16(void);\n>   static int32_t test17(void);\n>   static int32_t test18(void);\n> +static int32_t test19(void);\n> +static int32_t test20(void);\n> +static int32_t test21(void);\n>   \n>   rte_lpm_test tests[] = {\n>   /* Test Cases */\n> @@ -61,7 +65,10 @@ rte_lpm_test tests[] = {\n>   \ttest15,\n>   \ttest16,\n>   \ttest17,\n> -\ttest18\n> +\ttest18,\n> +\ttest19,\n> +\ttest20,\n> +\ttest21\n>   };\n>   \n>   #define MAX_DEPTH 32\n> @@ -1265,6 +1272,288 @@ test18(void)\n>   \treturn PASS;\n>   }\n>   \n> +/*\n> + * rte_lpm_rcu_qsbr_add positive and negative tests.\n> + *  - Add RCU QSBR variable to LPM\n> + *  - Add another RCU QSBR variable to LPM\n> + *  - Check returns\n> + */\n> +int32_t\n> +test19(void)\n> +{\n> +\tstruct rte_lpm *lpm = NULL;\n> +\tstruct rte_lpm_config config;\n> +\tsize_t sz;\n> +\tstruct rte_rcu_qsbr *qsv;\n> +\tstruct rte_rcu_qsbr *qsv2;\n> +\tint32_t status;\n> +\tstruct rte_lpm_rcu_config rcu_cfg = {0};\n> +\n> +\tconfig.max_rules = MAX_RULES;\n> +\tconfig.number_tbl8s = NUMBER_TBL8S;\n> +\tconfig.flags = 0;\n> +\n> +\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n> +\tTEST_LPM_ASSERT(lpm != NULL);\n> +\n> +\t/* Create RCU QSBR variable */\n> +\tsz = rte_rcu_qsbr_get_memsize(RTE_MAX_LCORE);\n> +\tqsv = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n> +\t\t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n> +\tTEST_LPM_ASSERT(qsv != NULL);\n> +\n> +\tstatus = rte_rcu_qsbr_init(qsv, RTE_MAX_LCORE);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\trcu_cfg.v = qsv;\n> +\t/* Invalid QSBR mode */\n> +\trcu_cfg.mode = 2;\n> +\tstatus = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n> +\tTEST_LPM_ASSERT(status != 0);\n> +\n> +\trcu_cfg.mode = RTE_LPM_QSBR_MODE_DQ;\n> +\t/* Attach RCU QSBR to LPM table */\n> +\tstatus = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\t/* Create and attach another RCU QSBR to LPM table */\n> +\tqsv2 = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n> +\t\t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n> +\tTEST_LPM_ASSERT(qsv2 != NULL);\n> +\n> +\trcu_cfg.v = qsv2;\n> +\trcu_cfg.mode = RTE_LPM_QSBR_MODE_SYNC;\n> +\tstatus = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n> +\tTEST_LPM_ASSERT(status != 0);\n> +\n> +\trte_lpm_free(lpm);\n> +\trte_free(qsv);\n> +\trte_free(qsv2);\n> +\n> +\treturn PASS;\n> +}\n> +\n> +/*\n> + * rte_lpm_rcu_qsbr_add DQ mode functional test.\n> + * Reader and writer are in the same thread in this test.\n> + *  - Create LPM which supports 1 tbl8 group at max\n> + *  - Add RCU QSBR variable to LPM\n> + *  - Add a rule with depth=28 (> 24)\n> + *  - Register a reader thread (not a real thread)\n> + *  - Reader lookup existing rule\n> + *  - Writer delete the rule\n> + *  - Reader lookup the rule\n> + *  - Writer re-add the rule (no available tbl8 group)\n> + *  - Reader report quiescent state and unregister\n> + *  - Writer re-add the rule\n> + *  - Reader lookup the rule\n> + */\n> +int32_t\n> +test20(void)\n> +{\n> +\tstruct rte_lpm *lpm = NULL;\n> +\tstruct rte_lpm_config config;\n> +\tsize_t sz;\n> +\tstruct rte_rcu_qsbr *qsv;\n> +\tint32_t status;\n> +\tuint32_t ip, next_hop, next_hop_return;\n> +\tuint8_t depth;\n> +\tstruct rte_lpm_rcu_config rcu_cfg = {0};\n> +\n> +\tconfig.max_rules = MAX_RULES;\n> +\tconfig.number_tbl8s = 1;\n> +\tconfig.flags = 0;\n> +\n> +\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n> +\tTEST_LPM_ASSERT(lpm != NULL);\n> +\n> +\t/* Create RCU QSBR variable */\n> +\tsz = rte_rcu_qsbr_get_memsize(1);\n> +\tqsv = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n> +\t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n> +\tTEST_LPM_ASSERT(qsv != NULL);\n> +\n> +\tstatus = rte_rcu_qsbr_init(qsv, 1);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\trcu_cfg.v = qsv;\n> +\trcu_cfg.mode = RTE_LPM_QSBR_MODE_DQ;\n> +\t/* Attach RCU QSBR to LPM table */\n> +\tstatus = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\tip = RTE_IPV4(192, 18, 100, 100);\n\n\nThis is a globally routed ip, it looks like you missed \"6\" in the second \noctet. Here it is better to use the rfc5737 address, rather than rfc1918.\n\n\n> +\tdepth = 28;\n> +\tnext_hop = 1;\n> +\tstatus = rte_lpm_add(lpm, ip, depth, next_hop);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\tTEST_LPM_ASSERT(lpm->tbl24[ip>>8].valid_group);\n> +\n> +\t/* Register pseudo reader */\n> +\tstatus = rte_rcu_qsbr_thread_register(qsv, 0);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\trte_rcu_qsbr_thread_online(qsv, 0);\n> +\n> +\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\tTEST_LPM_ASSERT(next_hop_return == next_hop);\n> +\n> +\t/* Writer update */\n> +\tstatus = rte_lpm_delete(lpm, ip, depth);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\tTEST_LPM_ASSERT(!lpm->tbl24[ip>>8].valid);\n> +\n> +\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n> +\tTEST_LPM_ASSERT(status != 0);\n> +\n> +\tstatus = rte_lpm_add(lpm, ip, depth, next_hop);\n> +\tTEST_LPM_ASSERT(status != 0);\n> +\n> +\t/* Reader quiescent */\n> +\trte_rcu_qsbr_quiescent(qsv, 0);\n> +\n> +\tstatus = rte_lpm_add(lpm, ip, depth, next_hop);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\trte_rcu_qsbr_thread_offline(qsv, 0);\n> +\tstatus = rte_rcu_qsbr_thread_unregister(qsv, 0);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\tTEST_LPM_ASSERT(next_hop_return == next_hop);\n> +\n> +\trte_lpm_free(lpm);\n> +\trte_free(qsv);\n> +\n> +\treturn PASS;\n> +}\n> +\n> +static struct rte_lpm *g_lpm;\n> +static struct rte_rcu_qsbr *g_v;\n> +static uint32_t g_ip = RTE_IPV4(192, 18, 100, 100);\n\n\nSame here as above\n\n\n> +static volatile uint8_t writer_done;\n> +/* Report quiescent state interval every 1024 lookups. Larger critical\n> + * sections in reader will result in writer polling multiple times.\n> + */\n> +#define QSBR_REPORTING_INTERVAL 1024\n> +#define WRITER_ITERATIONS\t512\n> +\n> +/*\n> + * Reader thread using rte_lpm data structure with RCU.\n> + */\n> +static int\n> +test_lpm_rcu_qsbr_reader(void *arg)\n> +{\n> +\tint i;\n> +\tuint32_t next_hop_return = 0;\n> +\n> +\tRTE_SET_USED(arg);\n> +\t/* Register this thread to report quiescent state */\n> +\trte_rcu_qsbr_thread_register(g_v, 0);\n> +\trte_rcu_qsbr_thread_online(g_v, 0);\n> +\n> +\tdo {\n> +\t\tfor (i = 0; i < QSBR_REPORTING_INTERVAL; i++)\n> +\t\t\trte_lpm_lookup(g_lpm, g_ip, &next_hop_return);\n> +\n> +\t\t/* Update quiescent state */\n> +\t\trte_rcu_qsbr_quiescent(g_v, 0);\n> +\t} while (!writer_done);\n> +\n> +\trte_rcu_qsbr_thread_offline(g_v, 0);\n> +\trte_rcu_qsbr_thread_unregister(g_v, 0);\n> +\n> +\treturn 0;\n> +}\n> +\n> +/*\n> + * rte_lpm_rcu_qsbr_add sync mode functional test.\n> + * 1 Reader and 1 writer. They cannot be in the same thread in this test.\n> + *  - Create LPM which supports 1 tbl8 group at max\n> + *  - Add RCU QSBR variable with sync mode to LPM\n> + *  - Register a reader thread. Reader keeps looking up a specific rule.\n> + *  - Writer keeps adding and deleting a specific rule with depth=28 (> 24)\n> + */\n> +int32_t\n> +test21(void)\n> +{\n> +\tstruct rte_lpm_config config;\n> +\tsize_t sz;\n> +\tint32_t status;\n> +\tuint32_t i, next_hop;\n> +\tuint8_t depth;\n> +\tstruct rte_lpm_rcu_config rcu_cfg = {0};\n> +\n> +\tif (rte_lcore_count() < 2) {\n> +\t\tprintf(\"Not enough cores for %s, expecting at least 2\\n\",\n> +\t\t\t__func__);\n> +\t\treturn TEST_SKIPPED;\n> +\t}\n> +\n> +\tconfig.max_rules = MAX_RULES;\n> +\tconfig.number_tbl8s = 1;\n> +\tconfig.flags = 0;\n> +\n> +\tg_lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n> +\tTEST_LPM_ASSERT(g_lpm != NULL);\n> +\n> +\t/* Create RCU QSBR variable */\n> +\tsz = rte_rcu_qsbr_get_memsize(1);\n> +\tg_v = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n> +\t\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n> +\tTEST_LPM_ASSERT(g_v != NULL);\n> +\n> +\tstatus = rte_rcu_qsbr_init(g_v, 1);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\trcu_cfg.v = g_v;\n> +\trcu_cfg.mode = RTE_LPM_QSBR_MODE_SYNC;\n> +\t/* Attach RCU QSBR to LPM table */\n> +\tstatus = rte_lpm_rcu_qsbr_add(g_lpm, &rcu_cfg, NULL);\n> +\tTEST_LPM_ASSERT(status == 0);\n> +\n> +\twriter_done = 0;\n> +\t/* Launch reader thread */\n> +\trte_eal_remote_launch(test_lpm_rcu_qsbr_reader, NULL,\n> +\t\t\t\trte_get_next_lcore(-1, 1, 0));\n> +\n> +\tdepth = 28;\n> +\tnext_hop = 1;\n> +\tstatus = rte_lpm_add(g_lpm, g_ip, depth, next_hop);\n> +\tif (status != 0) {\n> +\t\tprintf(\"%s: Failed to add rule\\n\", __func__);\n> +\t\tgoto error;\n> +\t}\n> +\n> +\t/* Writer update */\n> +\tfor (i = 0; i < WRITER_ITERATIONS; i++) {\n> +\t\tstatus = rte_lpm_delete(g_lpm, g_ip, depth);\n> +\t\tif (status != 0) {\n> +\t\t\tprintf(\"%s: Failed to delete rule at iteration %d\\n\",\n> +\t\t\t\t__func__, i);\n> +\t\t\tgoto error;\n> +\t\t}\n> +\n> +\t\tstatus = rte_lpm_add(g_lpm, g_ip, depth, next_hop);\n> +\t\tif (status != 0) {\n> +\t\t\tprintf(\"%s: Failed to add rule at iteration %d\\n\",\n> +\t\t\t\t__func__, i);\n> +\t\t\tgoto error;\n> +\t\t}\n> +\t}\n> +\n> +error:\n> +\twriter_done = 1;\n> +\t/* Wait until reader exited. */\n> +\trte_eal_mp_wait_lcore();\n> +\n> +\trte_lpm_free(g_lpm);\n> +\trte_free(g_v);\n> +\n> +\treturn (status == 0) ? PASS : -1;\n> +}\n> +\n>   /*\n>    * Do all unit tests.\n>    */\n\nAcked-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>",
        "headers": {
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            "References": "<20190906094534.36060-1-ruifeng.wang@arm.com>\n <20200707151554.64431-1-ruifeng.wang@arm.com>\n <20200707151554.64431-3-ruifeng.wang@arm.com>",
            "Subject": "Re: [dpdk-dev] [PATCH v7 2/3] test/lpm: add LPM RCU integration\n\tfunctional tests",
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            "From": "\"Medvedkin, Vladimir\" <vladimir.medvedkin@intel.com>",
            "Received": [
                "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 42CECA0526;\n\tWed,  8 Jul 2020 14:37:23 +0200 (CEST)",
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            "Date": "Wed, 8 Jul 2020 13:37:16 +0100",
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            "To": "Ruifeng Wang <ruifeng.wang@arm.com>,\n Bruce Richardson <bruce.richardson@intel.com>",
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    },
    {
        "id": 115528,
        "web_url": "https://patches.dpdk.org/comment/115528/",
        "msgid": "<HE1PR0801MB20258C304AE23716F6CE67999E670@HE1PR0801MB2025.eurprd08.prod.outlook.com>",
        "date": "2020-07-08T14:00:57",
        "subject": "Re: [dpdk-dev] [PATCH v7 2/3] test/lpm: add LPM RCU integration\n\tfunctional tests",
        "submitter": {
            "id": 1198,
            "url": "https://patches.dpdk.org/api/people/1198/",
            "name": "Ruifeng Wang",
            "email": "ruifeng.wang@arm.com"
        },
        "content": "From: Medvedkin, Vladimir <vladimir.medvedkin@intel.com>\nSent: Wednesday, July 8, 2020 8:37 PM\nTo: Ruifeng Wang <Ruifeng.Wang@arm.com>; Bruce Richardson <bruce.richardson@intel.com>\nCc: dev@dpdk.org; mdr@ashroe.eu; konstantin.ananyev@intel.com; Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>\nSubject: Re: [PATCH v7 2/3] test/lpm: add LPM RCU integration functional tests\n\n\nHi Ruifeng,\n\nJust a few nits\n\n[Ruifeng] Thank you for reviewing this patch.\nOn 07/07/2020 16:15, Ruifeng Wang wrote:\n\nAdd positive and negative tests for API rte_lpm_rcu_qsbr_add.\n\nAlso test LPM library behavior when RCU QSBR is enabled.\n\n\n\nSigned-off-by: Ruifeng Wang <ruifeng.wang@arm.com><mailto:ruifeng.wang@arm.com>\n\nReviewed-by: Gavin Hu <gavin.hu@arm.com><mailto:gavin.hu@arm.com>\n\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com><mailto:honnappa.nagarahalli@arm.com>\n\n---\n\n app/test/test_lpm.c | 291 +++++++++++++++++++++++++++++++++++++++++++-\n\n 1 file changed, 290 insertions(+), 1 deletion(-)\n\n\n\ndiff --git a/app/test/test_lpm.c b/app/test/test_lpm.c\n\nindex 3a3fd097f..93742e3c7 100644\n\n--- a/app/test/test_lpm.c\n\n+++ b/app/test/test_lpm.c\n\n@@ -8,6 +8,7 @@\n\n\n\n #include <rte_ip.h>\n\n #include <rte_lpm.h>\n\n+#include <rte_malloc.h>\n\n\n\n #include \"test.h\"\n\n #include \"test_xmmt_ops.h\"\n\n@@ -40,6 +41,9 @@ static int32_t test15(void);\n\n static int32_t test16(void);\n\n static int32_t test17(void);\n\n static int32_t test18(void);\n\n+static int32_t test19(void);\n\n+static int32_t test20(void);\n\n+static int32_t test21(void);\n\n\n\n rte_lpm_test tests[] = {\n\n /* Test Cases */\n\n@@ -61,7 +65,10 @@ rte_lpm_test tests[] = {\n\n        test15,\n\n        test16,\n\n        test17,\n\n-       test18\n\n+       test18,\n\n+       test19,\n\n+       test20,\n\n+       test21\n\n };\n\n\n\n #define MAX_DEPTH 32\n\n@@ -1265,6 +1272,288 @@ test18(void)\n\n        return PASS;\n\n }\n\n\n\n+/*\n\n+ * rte_lpm_rcu_qsbr_add positive and negative tests.\n\n+ *  - Add RCU QSBR variable to LPM\n\n+ *  - Add another RCU QSBR variable to LPM\n\n+ *  - Check returns\n\n+ */\n\n+int32_t\n\n+test19(void)\n\n+{\n\n+       struct rte_lpm *lpm = NULL;\n\n+       struct rte_lpm_config config;\n\n+       size_t sz;\n\n+       struct rte_rcu_qsbr *qsv;\n\n+       struct rte_rcu_qsbr *qsv2;\n\n+       int32_t status;\n\n+       struct rte_lpm_rcu_config rcu_cfg = {0};\n\n+\n\n+       config.max_rules = MAX_RULES;\n\n+       config.number_tbl8s = NUMBER_TBL8S;\n\n+       config.flags = 0;\n\n+\n\n+       lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n\n+       TEST_LPM_ASSERT(lpm != NULL);\n\n+\n\n+       /* Create RCU QSBR variable */\n\n+       sz = rte_rcu_qsbr_get_memsize(RTE_MAX_LCORE);\n\n+       qsv = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n\n+                                      RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n\n+       TEST_LPM_ASSERT(qsv != NULL);\n\n+\n\n+       status = rte_rcu_qsbr_init(qsv, RTE_MAX_LCORE);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       rcu_cfg.v = qsv;\n\n+       /* Invalid QSBR mode */\n\n+       rcu_cfg.mode = 2;\n\n+       status = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n\n+       TEST_LPM_ASSERT(status != 0);\n\n+\n\n+       rcu_cfg.mode = RTE_LPM_QSBR_MODE_DQ;\n\n+       /* Attach RCU QSBR to LPM table */\n\n+       status = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       /* Create and attach another RCU QSBR to LPM table */\n\n+       qsv2 = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n\n+                                      RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n\n+       TEST_LPM_ASSERT(qsv2 != NULL);\n\n+\n\n+       rcu_cfg.v = qsv2;\n\n+       rcu_cfg.mode = RTE_LPM_QSBR_MODE_SYNC;\n\n+       status = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n\n+       TEST_LPM_ASSERT(status != 0);\n\n+\n\n+       rte_lpm_free(lpm);\n\n+       rte_free(qsv);\n\n+       rte_free(qsv2);\n\n+\n\n+       return PASS;\n\n+}\n\n+\n\n+/*\n\n+ * rte_lpm_rcu_qsbr_add DQ mode functional test.\n\n+ * Reader and writer are in the same thread in this test.\n\n+ *  - Create LPM which supports 1 tbl8 group at max\n\n+ *  - Add RCU QSBR variable to LPM\n\n+ *  - Add a rule with depth=28 (> 24)\n\n+ *  - Register a reader thread (not a real thread)\n\n+ *  - Reader lookup existing rule\n\n+ *  - Writer delete the rule\n\n+ *  - Reader lookup the rule\n\n+ *  - Writer re-add the rule (no available tbl8 group)\n\n+ *  - Reader report quiescent state and unregister\n\n+ *  - Writer re-add the rule\n\n+ *  - Reader lookup the rule\n\n+ */\n\n+int32_t\n\n+test20(void)\n\n+{\n\n+       struct rte_lpm *lpm = NULL;\n\n+       struct rte_lpm_config config;\n\n+       size_t sz;\n\n+       struct rte_rcu_qsbr *qsv;\n\n+       int32_t status;\n\n+       uint32_t ip, next_hop, next_hop_return;\n\n+       uint8_t depth;\n\n+       struct rte_lpm_rcu_config rcu_cfg = {0};\n\n+\n\n+       config.max_rules = MAX_RULES;\n\n+       config.number_tbl8s = 1;\n\n+       config.flags = 0;\n\n+\n\n+       lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n\n+       TEST_LPM_ASSERT(lpm != NULL);\n\n+\n\n+       /* Create RCU QSBR variable */\n\n+       sz = rte_rcu_qsbr_get_memsize(1);\n\n+       qsv = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n\n+                              RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n\n+       TEST_LPM_ASSERT(qsv != NULL);\n\n+\n\n+       status = rte_rcu_qsbr_init(qsv, 1);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       rcu_cfg.v = qsv;\n\n+       rcu_cfg.mode = RTE_LPM_QSBR_MODE_DQ;\n\n+       /* Attach RCU QSBR to LPM table */\n\n+       status = rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg, NULL);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       ip = RTE_IPV4(192, 18, 100, 100);\n\n\n\nThis is a globally routed ip, it looks like you missed \"6\" in the second octet. Here it is better to use the rfc5737 address, rather than rfc1918.\n\n[Ruifeng] Agreed. Use reserved address is better. Will change to rfc5737 address in next version.\n\n\n\n+       depth = 28;\n\n+       next_hop = 1;\n\n+       status = rte_lpm_add(lpm, ip, depth, next_hop);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+       TEST_LPM_ASSERT(lpm->tbl24[ip>>8].valid_group);\n\n+\n\n+       /* Register pseudo reader */\n\n+       status = rte_rcu_qsbr_thread_register(qsv, 0);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+       rte_rcu_qsbr_thread_online(qsv, 0);\n\n+\n\n+       status = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+       TEST_LPM_ASSERT(next_hop_return == next_hop);\n\n+\n\n+       /* Writer update */\n\n+       status = rte_lpm_delete(lpm, ip, depth);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+       TEST_LPM_ASSERT(!lpm->tbl24[ip>>8].valid);\n\n+\n\n+       status = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\n+       TEST_LPM_ASSERT(status != 0);\n\n+\n\n+       status = rte_lpm_add(lpm, ip, depth, next_hop);\n\n+       TEST_LPM_ASSERT(status != 0);\n\n+\n\n+       /* Reader quiescent */\n\n+       rte_rcu_qsbr_quiescent(qsv, 0);\n\n+\n\n+       status = rte_lpm_add(lpm, ip, depth, next_hop);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       rte_rcu_qsbr_thread_offline(qsv, 0);\n\n+       status = rte_rcu_qsbr_thread_unregister(qsv, 0);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       status = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+       TEST_LPM_ASSERT(next_hop_return == next_hop);\n\n+\n\n+       rte_lpm_free(lpm);\n\n+       rte_free(qsv);\n\n+\n\n+       return PASS;\n\n+}\n\n+\n\n+static struct rte_lpm *g_lpm;\n\n+static struct rte_rcu_qsbr *g_v;\n\n+static uint32_t g_ip = RTE_IPV4(192, 18, 100, 100);\n\n\n\nSame here as above\n\n[Ruifeng] Will change. Thank you.\n\n\n\n+static volatile uint8_t writer_done;\n\n+/* Report quiescent state interval every 1024 lookups. Larger critical\n\n+ * sections in reader will result in writer polling multiple times.\n\n+ */\n\n+#define QSBR_REPORTING_INTERVAL 1024\n\n+#define WRITER_ITERATIONS     512\n\n+\n\n+/*\n\n+ * Reader thread using rte_lpm data structure with RCU.\n\n+ */\n\n+static int\n\n+test_lpm_rcu_qsbr_reader(void *arg)\n\n+{\n\n+       int i;\n\n+       uint32_t next_hop_return = 0;\n\n+\n\n+       RTE_SET_USED(arg);\n\n+       /* Register this thread to report quiescent state */\n\n+       rte_rcu_qsbr_thread_register(g_v, 0);\n\n+       rte_rcu_qsbr_thread_online(g_v, 0);\n\n+\n\n+       do {\n\n+               for (i = 0; i < QSBR_REPORTING_INTERVAL; i++)\n\n+                       rte_lpm_lookup(g_lpm, g_ip, &next_hop_return);\n\n+\n\n+               /* Update quiescent state */\n\n+               rte_rcu_qsbr_quiescent(g_v, 0);\n\n+       } while (!writer_done);\n\n+\n\n+       rte_rcu_qsbr_thread_offline(g_v, 0);\n\n+       rte_rcu_qsbr_thread_unregister(g_v, 0);\n\n+\n\n+       return 0;\n\n+}\n\n+\n\n+/*\n\n+ * rte_lpm_rcu_qsbr_add sync mode functional test.\n\n+ * 1 Reader and 1 writer. They cannot be in the same thread in this test.\n\n+ *  - Create LPM which supports 1 tbl8 group at max\n\n+ *  - Add RCU QSBR variable with sync mode to LPM\n\n+ *  - Register a reader thread. Reader keeps looking up a specific rule.\n\n+ *  - Writer keeps adding and deleting a specific rule with depth=28 (> 24)\n\n+ */\n\n+int32_t\n\n+test21(void)\n\n+{\n\n+       struct rte_lpm_config config;\n\n+       size_t sz;\n\n+       int32_t status;\n\n+       uint32_t i, next_hop;\n\n+       uint8_t depth;\n\n+       struct rte_lpm_rcu_config rcu_cfg = {0};\n\n+\n\n+       if (rte_lcore_count() < 2) {\n\n+               printf(\"Not enough cores for %s, expecting at least 2\\n\",\n\n+                       __func__);\n\n+               return TEST_SKIPPED;\n\n+       }\n\n+\n\n+       config.max_rules = MAX_RULES;\n\n+       config.number_tbl8s = 1;\n\n+       config.flags = 0;\n\n+\n\n+       g_lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);\n\n+       TEST_LPM_ASSERT(g_lpm != NULL);\n\n+\n\n+       /* Create RCU QSBR variable */\n\n+       sz = rte_rcu_qsbr_get_memsize(1);\n\n+       g_v = (struct rte_rcu_qsbr *)rte_zmalloc_socket(NULL, sz,\n\n+                              RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n\n+       TEST_LPM_ASSERT(g_v != NULL);\n\n+\n\n+       status = rte_rcu_qsbr_init(g_v, 1);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       rcu_cfg.v = g_v;\n\n+       rcu_cfg.mode = RTE_LPM_QSBR_MODE_SYNC;\n\n+       /* Attach RCU QSBR to LPM table */\n\n+       status = rte_lpm_rcu_qsbr_add(g_lpm, &rcu_cfg, NULL);\n\n+       TEST_LPM_ASSERT(status == 0);\n\n+\n\n+       writer_done = 0;\n\n+       /* Launch reader thread */\n\n+       rte_eal_remote_launch(test_lpm_rcu_qsbr_reader, NULL,\n\n+                              rte_get_next_lcore(-1, 1, 0));\n\n+\n\n+       depth = 28;\n\n+       next_hop = 1;\n\n+       status = rte_lpm_add(g_lpm, g_ip, depth, next_hop);\n\n+       if (status != 0) {\n\n+               printf(\"%s: Failed to add rule\\n\", __func__);\n\n+               goto error;\n\n+       }\n\n+\n\n+       /* Writer update */\n\n+       for (i = 0; i < WRITER_ITERATIONS; i++) {\n\n+               status = rte_lpm_delete(g_lpm, g_ip, depth);\n\n+               if (status != 0) {\n\n+                       printf(\"%s: Failed to delete rule at iteration %d\\n\",\n\n+                              __func__, i);\n\n+                       goto error;\n\n+               }\n\n+\n\n+               status = rte_lpm_add(g_lpm, g_ip, depth, next_hop);\n\n+               if (status != 0) {\n\n+                       printf(\"%s: Failed to add rule at iteration %d\\n\",\n\n+                              __func__, i);\n\n+                       goto error;\n\n+               }\n\n+       }\n\n+\n\n+error:\n\n+       writer_done = 1;\n\n+       /* Wait until reader exited. */\n\n+       rte_eal_mp_wait_lcore();\n\n+\n\n+       rte_lpm_free(g_lpm);\n\n+       rte_free(g_v);\n\n+\n\n+       return (status == 0) ? PASS : -1;\n\n+}\n\n+\n\n /*\n\n  * Do all unit tests.\n\n  */\n\n\n\nAcked-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com><mailto:vladimir.medvedkin@intel.com>\n\n\n\n\n\n\n\n--\n\nRegards,\n\nVladimir",
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            "Subject": "Re: [dpdk-dev] [PATCH v7 2/3] test/lpm: add LPM RCU integration\n\tfunctional tests",
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            "From": "Ruifeng Wang <Ruifeng.Wang@arm.com>",
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