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{
    "id": 73414,
    "url": "https://patches.dpdk.org/api/patches/73414/?format=api",
    "web_url": "https://patches.dpdk.org/patch/73414/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1594115449-13750-5-git-send-email-phil.yang@arm.com>",
    "date": "2020-07-07T09:50:49",
    "name": "[v6,4/4] eal/atomic: add wrapper for C11 atomic thread fence",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "3794299bd951b87507692337487ea2245f550f78",
    "submitter": {
        "id": 833,
        "url": "https://patches.dpdk.org/api/people/833/?format=api",
        "name": "Phil Yang",
        "email": "phil.yang@arm.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73414/mbox/",
    "series": [
        {
            "id": 10843,
            "url": "https://patches.dpdk.org/api/series/10843/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10843",
            "date": "2020-07-07T09:50:45",
            "name": "generic rte atomic APIs deprecate proposal",
            "version": 6,
            "mbox": "https://patches.dpdk.org/series/10843/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73414/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73414/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "References": "<1590483667-10318-1-git-send-email-phil.yang@arm.com>\n <1594115449-13750-1-git-send-email-phil.yang@arm.com>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Subject": "[dpdk-dev] [PATCH v6 4/4] eal/atomic: add wrapper for C11 atomic\n\tthread fence",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Phil Yang <phil.yang@arm.com>",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 15813A00BE;\n\tTue,  7 Jul 2020 11:52:03 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F10A91DDC7;\n\tTue,  7 Jul 2020 11:51:41 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id BEF9A1DDD4\n for <dev@dpdk.org>; Tue,  7 Jul 2020 11:51:40 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 40CC8C0A;\n Tue,  7 Jul 2020 02:51:40 -0700 (PDT)",
            "from phil-VirtualBox.shanghai.arm.com\n (phil-VirtualBox.shanghai.arm.com [10.169.109.153])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1D7623F718;\n Tue,  7 Jul 2020 02:51:36 -0700 (PDT)"
        ],
        "To": "thomas@monjalon.net,\n\tdev@dpdk.org,\n\tdavid.marchand@redhat.com",
        "X-Mailer": "git-send-email 2.7.4",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Tue,  7 Jul 2020 17:50:49 +0800",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "In-Reply-To": "<1594115449-13750-1-git-send-email-phil.yang@arm.com>",
        "Cc": "drc@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, jerinj@marvell.com,\n konstantin.ananyev@intel.com, Ola.Liljedahl@arm.com, ruifeng.wang@arm.com,\n nd@arm.com",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1594115449-13750-5-git-send-email-phil.yang@arm.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "Provide a wrapper for __atomic_thread_fence built-in to support\noptimized code for __ATOMIC_SEQ_CST memory order for x86 platforms.\n\nSuggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Ola Liljedahl <Ola.Liljedahl@arm.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n lib/librte_eal/arm/include/rte_atomic_32.h  |  6 ++++++\n lib/librte_eal/arm/include/rte_atomic_64.h  |  6 ++++++\n lib/librte_eal/include/generic/rte_atomic.h |  6 ++++++\n lib/librte_eal/ppc/include/rte_atomic.h     |  6 ++++++\n lib/librte_eal/x86/include/rte_atomic.h     | 17 +++++++++++++++++\n 5 files changed, 41 insertions(+)",
    "diff": "diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/arm/include/rte_atomic_32.h\nindex 7dc0d06..dbe7cc6 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_32.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_32.h\n@@ -37,6 +37,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() rte_rmb()\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h\nindex 7b7099c..22ff8ec 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_64.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_64.h\n@@ -41,6 +41,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------ 128 bit atomic operations -------------------------*/\n \n #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)\ndiff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal/include/generic/rte_atomic.h\nindex e6ab15a..5b941db 100644\n--- a/lib/librte_eal/include/generic/rte_atomic.h\n+++ b/lib/librte_eal/include/generic/rte_atomic.h\n@@ -158,6 +158,12 @@ static inline void rte_cio_rmb(void);\n \tasm volatile (\"\" : : : \"memory\");\t\\\n } while(0)\n \n+/**\n+ * Synchronization fence between threads based on the specified\n+ * memory order.\n+ */\n+static inline void rte_atomic_thread_fence(int mo);\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n \n /**\ndiff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc/include/rte_atomic.h\nindex 7e3e131..91c5f30 100644\n--- a/lib/librte_eal/ppc/include/rte_atomic.h\n+++ b/lib/librte_eal/ppc/include/rte_atomic.h\n@@ -40,6 +40,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() rte_rmb()\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n /* To be compatible with Power7, use GCC built-in functions for 16 bit\n  * operations */\ndiff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86/include/rte_atomic.h\nindex b9dcd30..bd256e7 100644\n--- a/lib/librte_eal/x86/include/rte_atomic.h\n+++ b/lib/librte_eal/x86/include/rte_atomic.h\n@@ -83,6 +83,23 @@ rte_smp_mb(void)\n \n #define rte_cio_rmb() rte_compiler_barrier()\n \n+/**\n+ * Synchronization fence between threads based on the specified\n+ * memory order.\n+ *\n+ * On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates\n+ * full 'mfence' which is quite expensive. The optimized\n+ * implementation of rte_smp_mb is used instead.\n+ */\n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\tif (mo == __ATOMIC_SEQ_CST)\n+\t\trte_smp_mb();\n+\telse\n+\t\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n \n #ifndef RTE_FORCE_INTRINSICS\n",
    "prefixes": [
        "v6",
        "4/4"
    ]
}