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GET /api/patches/7340/?format=api
{ "id": 7340, "url": "https://patches.dpdk.org/api/patches/7340/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com", "date": "2015-09-30T19:04:30", "name": "[dpdk-dev] i40e: fix wrong alignment for the number of HW descriptors", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8f1918c6f2ec8a15a20afd72e0cb66c2e15c7b85", "submitter": { "id": 33, "url": "https://patches.dpdk.org/api/people/33/?format=api", "name": "Ananyev, Konstantin", "email": "konstantin.ananyev@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7340/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7340/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1DB538E69;\n\tWed, 30 Sep 2015 21:36:11 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id E1A66E72\n\tfor <dev@dpdk.org>; Wed, 30 Sep 2015 21:36:09 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP; 30 Sep 2015 12:36:08 -0700", "from irvmail001.ir.intel.com ([163.33.26.43])\n\tby fmsmga001.fm.intel.com with ESMTP; 30 Sep 2015 12:36:08 -0700", "from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com\n\t[10.237.217.46])\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n\tt8UJ4XP5002996; Wed, 30 Sep 2015 20:04:33 +0100", "from sivswdev02.ir.intel.com (localhost [127.0.0.1])\n\tby sivswdev02.ir.intel.com with ESMTP id t8UJ4XEZ021077;\n\tWed, 30 Sep 2015 20:04:33 +0100", "(from kananye1@localhost)\n\tby sivswdev02.ir.intel.com with id t8UJ4WB0021073;\n\tWed, 30 Sep 2015 20:04:32 +0100" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,613,1437462000\"; d=\"scan'208\";a=\"800785482\"", "From": "Konstantin Ananyev <konstantin.ananyev@intel.com>", "To": "dev@dpdk.org", "Date": "Wed, 30 Sep 2015 20:04:30 +0100", "Message-Id": "<1443639870-20879-1-git-send-email-konstantin.ananyev@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "Subject": "[dpdk-dev] [PATCH] i40e: fix wrong alignment for the number of HW\n\tdescriptors", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "According to XL710 datasheet:\nRX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0\nregister is cleared, the QLEN must be whole number of 32\ndescriptors.\nTX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0\nregister is cleared, the QLEN must be whole number of 32\ndescriptors.\n\nSo make sure that for both RX and TX queues number of HW descriptors is\na multiple of 32.\n\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n drivers/net/i40e/i40e_rxtx.c | 26 +++++++++++++-------------\n drivers/net/i40e/i40e_rxtx.h | 6 ++++++\n 2 files changed, 19 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c\nindex fd656d5..260e580 100644\n--- a/drivers/net/i40e/i40e_rxtx.c\n+++ b/drivers/net/i40e/i40e_rxtx.c\n@@ -57,9 +57,6 @@\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n \n-#define I40E_MIN_RING_DESC 64\n-#define I40E_MAX_RING_DESC 4096\n-#define I40E_ALIGN 128\n #define DEFAULT_TX_RS_THRESH 32\n #define DEFAULT_TX_FREE_THRESH 32\n #define I40E_MAX_PKT_TYPE 256\n@@ -68,6 +65,9 @@\n \n #define I40E_DMA_MEM_ALIGN 4096\n \n+/* Base address of the HW descriptor ring should be 128B aligned. */\n+#define I40E_RING_BASE_ALIGN\t128\n+\n #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \\\n \t\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS)\n \n@@ -2126,9 +2126,9 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,\n \t\t\t \"index exceeds the maximum\");\n \t\treturn I40E_ERR_PARAM;\n \t}\n-\tif (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||\n-\t\t\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n-\t\t\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n+\tif (nb_desc % I40E_ALIGN_RING_DESC != 0 ||\n+\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n+\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n \t\tPMD_DRV_LOG(ERR, \"Number (%u) of receive descriptors is \"\n \t\t\t \"invalid\", nb_desc);\n \t\treturn I40E_ERR_PARAM;\n@@ -2338,9 +2338,9 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \t\treturn I40E_ERR_PARAM;\n \t}\n \n-\tif (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||\n-\t\t\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n-\t\t\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n+\tif (nb_desc % I40E_ALIGN_RING_DESC != 0 ||\n+\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n+\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n \t\tPMD_DRV_LOG(ERR, \"Number (%u) of transmit descriptors is \"\n \t\t\t \"invalid\", nb_desc);\n \t\treturn I40E_ERR_PARAM;\n@@ -2537,10 +2537,10 @@ i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,\n \n #ifdef RTE_LIBRTE_XEN_DOM0\n \treturn rte_memzone_reserve_bounded(z_name, ring_size,\n-\t\tsocket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);\n+\t\tsocket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);\n #else\n \treturn rte_memzone_reserve_aligned(z_name, ring_size,\n-\t\t\t\tsocket_id, 0, I40E_ALIGN);\n+\t\t\t\tsocket_id, 0, I40E_RING_BASE_ALIGN);\n #endif\n }\n \n@@ -2554,10 +2554,10 @@ i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)\n \t\treturn mz;\n #ifdef RTE_LIBRTE_XEN_DOM0\n \tmz = rte_memzone_reserve_bounded(name, len,\n-\t\tsocket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);\n+\t\tsocket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);\n #else\n \tmz = rte_memzone_reserve_aligned(name, len,\n-\t\t\t\tsocket_id, 0, I40E_ALIGN);\n+\t\t\t\tsocket_id, 0, I40E_RING_BASE_ALIGN);\n #endif\n \treturn mz;\n }\ndiff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h\nindex 4385142..3d9884d 100644\n--- a/drivers/net/i40e/i40e_rxtx.h\n+++ b/drivers/net/i40e/i40e_rxtx.h\n@@ -51,6 +51,12 @@\n #define I40E_RXBUF_SZ_1024 1024\n #define I40E_RXBUF_SZ_2048 2048\n \n+/* In none-PXE mode QLEN must be whole number of 32 descriptors. */\n+#define\tI40E_ALIGN_RING_DESC\t32\n+\n+#define\tI40E_MIN_RING_DESC\t64\n+#define\tI40E_MAX_RING_DESC\t4096\n+\n enum i40e_header_split_mode {\n \ti40e_header_split_none = 0,\n \ti40e_header_split_enabled = 1,\n", "prefixes": [ "dpdk-dev" ] }