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{
    "id": 73385,
    "url": "https://patches.dpdk.org/api/patches/73385/",
    "web_url": "https://patches.dpdk.org/patch/73385/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200707092244.12791-6-hemant.agrawal@nxp.com>",
    "date": "2020-07-07T09:22:20",
    "name": "[v2,05/29] bus/fslmc: rework portal allocation to a per thread basis",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "7d7614c1c11d2d507a77762826cbb799c73afbbb",
    "submitter": {
        "id": 477,
        "url": "https://patches.dpdk.org/api/people/477/",
        "name": "Hemant Agrawal",
        "email": "hemant.agrawal@nxp.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@intel.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73385/mbox/",
    "series": [
        {
            "id": 10842,
            "url": "https://patches.dpdk.org/api/series/10842/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10842",
            "date": "2020-07-07T09:22:15",
            "name": "NXP DPAAx enhancements",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/10842/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73385/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/73385/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Message-Id": "<20200707092244.12791-6-hemant.agrawal@nxp.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "To": "dev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com,\n\tNipun Gupta <nipun.gupta@nxp.com>",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8DD28A00BE;\n\tTue,  7 Jul 2020 11:27:50 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9E78D1DCF5;\n\tTue,  7 Jul 2020 11:27:06 +0200 (CEST)",
            "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n by dpdk.org (Postfix) with ESMTP id D5C1C1DC2E\n for <dev@dpdk.org>; Tue,  7 Jul 2020 11:27:00 +0200 (CEST)",
            "from inva021.nxp.com (localhost [127.0.0.1])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B77B12008E1;\n Tue,  7 Jul 2020 11:27:00 +0200 (CEST)",
            "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n [165.114.16.14])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9889D2008DD;\n Tue,  7 Jul 2020 11:26:58 +0200 (CEST)",
            "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n [10.232.133.63])\n by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 02520402FC;\n Tue,  7 Jul 2020 17:26:55 +0800 (SGT)"
        ],
        "Subject": "[dpdk-dev] [PATCH v2 05/29] bus/fslmc: rework portal allocation to\n\ta per thread basis",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "In-Reply-To": "<20200707092244.12791-1-hemant.agrawal@nxp.com>",
        "Precedence": "list",
        "From": "Hemant Agrawal <hemant.agrawal@nxp.com>",
        "References": "<20200527132326.1382-1-hemant.agrawal@nxp.com>\n <20200707092244.12791-1-hemant.agrawal@nxp.com>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Errors-To": "dev-bounces@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Date": "Tue,  7 Jul 2020 14:52:20 +0530",
        "X-Mailman-Version": "2.1.15",
        "X-Virus-Scanned": "ClamAV using ClamSMTP",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>"
    },
    "content": "From: Nipun Gupta <nipun.gupta@nxp.com>\n\nThe patch reworks the portal allocation which was previously\nbeing done on per lcore basis to a per thread basis.\nNow user can also create its own threads and use DPAA2 portals\nfor packet I/O.\n\nSigned-off-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/bus/fslmc/Makefile               |   1 +\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 220 +++++++++++++----------\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.h |   3 -\n 3 files changed, 124 insertions(+), 100 deletions(-)",
    "diff": "diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile\nindex c70e359c8..b98d758ee 100644\n--- a/drivers/bus/fslmc/Makefile\n+++ b/drivers/bus/fslmc/Makefile\n@@ -17,6 +17,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc\n CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include\n CFLAGS += -I$(RTE_SDK)/drivers/common/dpaax\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common\n+LDLIBS += -lpthread\n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n LDLIBS += -lrte_ethdev\n LDLIBS += -lrte_common_dpaax\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\nindex 21c535f2f..47ae72749 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n@@ -62,6 +62,9 @@ uint8_t dpaa2_dqrr_size;\n /* Variable to store DPAA2 EQCR size */\n uint8_t dpaa2_eqcr_size;\n \n+/* Variable to hold the portal_key, once created.*/\n+static pthread_key_t dpaa2_portal_key;\n+\n /*Stashing Macros default for LS208x*/\n static int dpaa2_core_cluster_base = 0x04;\n static int dpaa2_cluster_sz = 2;\n@@ -87,6 +90,32 @@ static int dpaa2_cluster_sz = 2;\n  * Cluster 4 (ID = x07) : CPU14, CPU15;\n  */\n \n+static int\n+dpaa2_get_core_id(void)\n+{\n+\trte_cpuset_t cpuset;\n+\tint i, ret, cpu_id = -1;\n+\n+\tret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),\n+\t\t&cpuset);\n+\tif (ret) {\n+\t\tDPAA2_BUS_ERR(\"pthread_getaffinity_np() failed\");\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tif (CPU_ISSET(i, &cpuset)) {\n+\t\t\tif (cpu_id == -1)\n+\t\t\t\tcpu_id = i;\n+\t\t\telse\n+\t\t\t\t/* Multiple cpus are affined */\n+\t\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn cpu_id;\n+}\n+\n static int\n dpaa2_core_cluster_sdest(int cpu_id)\n {\n@@ -97,7 +126,7 @@ dpaa2_core_cluster_sdest(int cpu_id)\n \n #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV\n static void\n-dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid)\n+dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id)\n {\n #define STRING_LEN\t28\n #define COMMAND_LEN\t50\n@@ -130,7 +159,7 @@ dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid)\n \t\treturn;\n \t}\n \n-\tcpu_mask = cpu_mask << dpaa2_cpu[lcoreid];\n+\tcpu_mask = cpu_mask << dpaa2_cpu[cpu_id];\n \tsnprintf(command, COMMAND_LEN, \"echo %X > /proc/irq/%s/smp_affinity\",\n \t\t cpu_mask, token);\n \tret = system(command);\n@@ -144,7 +173,7 @@ dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid)\n \tfclose(file);\n }\n \n-static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)\n+static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)\n {\n \tstruct epoll_event epoll_ev;\n \tint eventfd, dpio_epoll_fd, ret;\n@@ -181,36 +210,42 @@ static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)\n \t}\n \tdpio_dev->epoll_fd = dpio_epoll_fd;\n \n-\tdpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, lcoreid);\n+\tdpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id);\n \n \treturn 0;\n }\n+\n+static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev)\n+{\n+\tint ret;\n+\n+\tret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0);\n+\tif (ret)\n+\t\tDPAA2_BUS_ERR(\"DPIO interrupt disable failed\");\n+\n+\tclose(dpio_dev->epoll_fd);\n+}\n #endif\n \n static int\n-dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)\n+dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)\n {\n \tint sdest, ret;\n \tint cpu_id;\n \n \t/* Set the Stashing Destination */\n-\tif (lcoreid < 0) {\n-\t\tlcoreid = rte_get_master_lcore();\n-\t\tif (lcoreid < 0) {\n-\t\t\tDPAA2_BUS_ERR(\"Getting CPU Index failed\");\n-\t\t\treturn -1;\n-\t\t}\n+\tcpu_id = dpaa2_get_core_id();\n+\tif (cpu_id < 0) {\n+\t\tDPAA2_BUS_ERR(\"Thread not affined to a single core\");\n+\t\treturn -1;\n \t}\n \n-\tcpu_id = dpaa2_cpu[lcoreid];\n-\n \t/* Set the STASH Destination depending on Current CPU ID.\n \t * Valid values of SDEST are 4,5,6,7. Where,\n \t */\n-\n \tsdest = dpaa2_core_cluster_sdest(cpu_id);\n-\tDPAA2_BUS_DEBUG(\"Portal= %d  CPU= %u lcore id =%u SDEST= %d\",\n-\t\t\tdpio_dev->index, cpu_id, lcoreid, sdest);\n+\tDPAA2_BUS_DEBUG(\"Portal= %d  CPU= %u SDEST= %d\",\n+\t\t\tdpio_dev->index, cpu_id, sdest);\n \n \tret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,\n \t\t\t\t\t    dpio_dev->token, sdest);\n@@ -220,7 +255,7 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)\n \t}\n \n #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV\n-\tif (dpaa2_dpio_intr_init(dpio_dev, lcoreid)) {\n+\tif (dpaa2_dpio_intr_init(dpio_dev, cpu_id)) {\n \t\tDPAA2_BUS_ERR(\"Interrupt registration failed for dpio\");\n \t\treturn -1;\n \t}\n@@ -229,7 +264,17 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)\n \treturn 0;\n }\n \n-static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid)\n+static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)\n+{\n+\tif (dpio_dev) {\n+#ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV\n+\t\tdpaa2_dpio_intr_deinit(dpio_dev);\n+#endif\n+\t\trte_atomic16_clear(&dpio_dev->ref_count);\n+\t}\n+}\n+\n+static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)\n {\n \tstruct dpaa2_dpio_dev *dpio_dev = NULL;\n \tint ret;\n@@ -245,9 +290,18 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid)\n \tDPAA2_BUS_DEBUG(\"New Portal %p (%d) affined thread - %lu\",\n \t\t\tdpio_dev, dpio_dev->index, syscall(SYS_gettid));\n \n-\tret = dpaa2_configure_stashing(dpio_dev, lcoreid);\n-\tif (ret)\n+\tret = dpaa2_configure_stashing(dpio_dev);\n+\tif (ret) {\n \t\tDPAA2_BUS_ERR(\"dpaa2_configure_stashing failed\");\n+\t\treturn NULL;\n+\t}\n+\n+\tret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev);\n+\tif (ret) {\n+\t\tDPAA2_BUS_ERR(\"pthread_setspecific failed with ret: %d\", ret);\n+\t\tdpaa2_put_qbman_swp(dpio_dev);\n+\t\treturn NULL;\n+\t}\n \n \treturn dpio_dev;\n }\n@@ -255,98 +309,55 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid)\n int\n dpaa2_affine_qbman_swp(void)\n {\n-\tunsigned int lcore_id = rte_lcore_id();\n+\tstruct dpaa2_dpio_dev *dpio_dev;\n \tuint64_t tid = syscall(SYS_gettid);\n \n-\tif (lcore_id == LCORE_ID_ANY)\n-\t\tlcore_id = rte_get_master_lcore();\n-\t/* if the core id is not supported */\n-\telse if (lcore_id >= RTE_MAX_LCORE)\n-\t\treturn -1;\n-\n-\tif (dpaa2_io_portal[lcore_id].dpio_dev) {\n-\t\tDPAA2_BUS_DP_INFO(\"DPAA Portal=%p (%d) is being shared\"\n-\t\t\t    \" between thread %\" PRIu64 \" and current \"\n-\t\t\t    \"%\" PRIu64 \"\\n\",\n-\t\t\t    dpaa2_io_portal[lcore_id].dpio_dev,\n-\t\t\t    dpaa2_io_portal[lcore_id].dpio_dev->index,\n-\t\t\t    dpaa2_io_portal[lcore_id].net_tid,\n-\t\t\t    tid);\n-\t\tRTE_PER_LCORE(_dpaa2_io).dpio_dev\n-\t\t\t= dpaa2_io_portal[lcore_id].dpio_dev;\n-\t\trte_atomic16_inc(&dpaa2_io_portal\n-\t\t\t\t [lcore_id].dpio_dev->ref_count);\n-\t\tdpaa2_io_portal[lcore_id].net_tid = tid;\n-\n-\t\tDPAA2_BUS_DP_DEBUG(\"Old Portal=%p (%d) affined thread - \"\n-\t\t\t\t   \"%\" PRIu64 \"\\n\",\n-\t\t\t    dpaa2_io_portal[lcore_id].dpio_dev,\n-\t\t\t    dpaa2_io_portal[lcore_id].dpio_dev->index,\n-\t\t\t    tid);\n-\t\treturn 0;\n-\t}\n-\n \t/* Populate the dpaa2_io_portal structure */\n-\tdpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);\n-\n-\tif (dpaa2_io_portal[lcore_id].dpio_dev) {\n-\t\tRTE_PER_LCORE(_dpaa2_io).dpio_dev\n-\t\t\t= dpaa2_io_portal[lcore_id].dpio_dev;\n-\t\tdpaa2_io_portal[lcore_id].net_tid = tid;\n+\tif (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) {\n+\t\tdpio_dev = dpaa2_get_qbman_swp();\n+\t\tif (!dpio_dev) {\n+\t\t\tDPAA2_BUS_ERR(\"No software portal resource left\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tRTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev;\n \n-\t\treturn 0;\n-\t} else {\n-\t\treturn -1;\n+\t\tDPAA2_BUS_INFO(\n+\t\t\t\"DPAA Portal=%p (%d) is affined to thread %\" PRIu64,\n+\t\t\tdpio_dev, dpio_dev->index, tid);\n \t}\n+\treturn 0;\n }\n \n int\n dpaa2_affine_qbman_ethrx_swp(void)\n {\n-\tunsigned int lcore_id = rte_lcore_id();\n+\tstruct dpaa2_dpio_dev *dpio_dev;\n \tuint64_t tid = syscall(SYS_gettid);\n \n-\tif (lcore_id == LCORE_ID_ANY)\n-\t\tlcore_id = rte_get_master_lcore();\n-\t/* if the core id is not supported */\n-\telse if (lcore_id >= RTE_MAX_LCORE)\n-\t\treturn -1;\n+\t/* Populate the dpaa2_io_portal structure */\n+\tif (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) {\n+\t\tdpio_dev = dpaa2_get_qbman_swp();\n+\t\tif (!dpio_dev) {\n+\t\t\tDPAA2_BUS_ERR(\"No software portal resource left\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tRTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev;\n \n-\tif (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {\n-\t\tDPAA2_BUS_DP_INFO(\n-\t\t\t\"DPAA Portal=%p (%d) is being shared between thread\"\n-\t\t\t\" %\" PRIu64 \" and current %\" PRIu64 \"\\n\",\n-\t\t\tdpaa2_io_portal[lcore_id].ethrx_dpio_dev,\n-\t\t\tdpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,\n-\t\t\tdpaa2_io_portal[lcore_id].sec_tid,\n-\t\t\ttid);\n-\t\tRTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev\n-\t\t\t= dpaa2_io_portal[lcore_id].ethrx_dpio_dev;\n-\t\trte_atomic16_inc(&dpaa2_io_portal\n-\t\t\t\t [lcore_id].ethrx_dpio_dev->ref_count);\n-\t\tdpaa2_io_portal[lcore_id].sec_tid = tid;\n-\n-\t\tDPAA2_BUS_DP_DEBUG(\n-\t\t\t\"Old Portal=%p (%d) affined thread\"\n-\t\t\t\" - %\" PRIu64 \"\\n\",\n-\t\t\tdpaa2_io_portal[lcore_id].ethrx_dpio_dev,\n-\t\t\tdpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,\n-\t\t\ttid);\n-\t\treturn 0;\n+\t\tDPAA2_BUS_INFO(\n+\t\t\t\"DPAA Portal=%p (%d) is affined for eth rx to thread %\"\n+\t\t\tPRIu64, dpio_dev, dpio_dev->index, tid);\n \t}\n+\treturn 0;\n+}\n \n-\t/* Populate the dpaa2_io_portal structure */\n-\tdpaa2_io_portal[lcore_id].ethrx_dpio_dev =\n-\t\tdpaa2_get_qbman_swp(lcore_id);\n-\n-\tif (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {\n-\t\tRTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev\n-\t\t\t= dpaa2_io_portal[lcore_id].ethrx_dpio_dev;\n-\t\tdpaa2_io_portal[lcore_id].sec_tid = tid;\n-\t\treturn 0;\n-\t} else {\n-\t\treturn -1;\n-\t}\n+static void dpaa2_portal_finish(void *arg)\n+{\n+\tRTE_SET_USED(arg);\n+\n+\tdpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev);\n+\tdpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev);\n+\n+\tpthread_setspecific(dpaa2_portal_key, NULL);\n }\n \n /*\n@@ -398,6 +409,7 @@ dpaa2_create_dpio_device(int vdev_fd,\n \tstruct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};\n \tstruct qbman_swp_desc p_des;\n \tstruct dpio_attr attr;\n+\tint ret;\n \tstatic int check_lcore_cpuset;\n \n \tif (obj_info->num_regions < NUM_DPIO_REGIONS) {\n@@ -547,12 +559,26 @@ dpaa2_create_dpio_device(int vdev_fd,\n \n \tTAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);\n \n+\tif (!dpaa2_portal_key) {\n+\t\t/* create the key, supplying a function that'll be invoked\n+\t\t * when a portal affined thread will be deleted.\n+\t\t */\n+\t\tret = pthread_key_create(&dpaa2_portal_key,\n+\t\t\t\t\t dpaa2_portal_finish);\n+\t\tif (ret) {\n+\t\t\tDPAA2_BUS_DEBUG(\"Unable to create pthread key (%d)\",\n+\t\t\t\t\tret);\n+\t\t\tgoto err;\n+\t\t}\n+\t}\n+\n \treturn 0;\n \n err:\n \tif (dpio_dev->dpio) {\n \t\tdpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);\n \t\tdpio_close(dpio_dev->dpio, CMD_PRI_LOW,  dpio_dev->token);\n+\t\trte_free(dpio_dev->eqresp);\n \t\trte_free(dpio_dev->dpio);\n \t}\n \ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\nindex f6436f2e5..b8eb8ee0a 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n@@ -14,9 +14,6 @@\n struct dpaa2_io_portal_t {\n \tstruct dpaa2_dpio_dev *dpio_dev;\n \tstruct dpaa2_dpio_dev *ethrx_dpio_dev;\n-\tuint64_t net_tid;\n-\tuint64_t sec_tid;\n-\tvoid *eventdev;\n };\n \n /*! Global per thread DPIO portal */\n",
    "prefixes": [
        "v2",
        "05/29"
    ]
}