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{
    "id": 73353,
    "url": "https://patches.dpdk.org/api/patches/73353/",
    "web_url": "https://patches.dpdk.org/patch/73353/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200706234333.26310-1-honnappa.nagarahalli@arm.com>",
    "date": "2020-07-06T23:43:31",
    "name": "[v4,1/3] eal: adjust barriers for IO on Armv8-a",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "5af4cd863f0eb525f23afd11c1e351d2e373f32b",
    "submitter": {
        "id": 1045,
        "url": "https://patches.dpdk.org/api/people/1045/",
        "name": "Honnappa Nagarahalli",
        "email": "honnappa.nagarahalli@arm.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/patch/73353/mbox/",
    "series": [
        {
            "id": 10828,
            "url": "https://patches.dpdk.org/api/series/10828/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10828",
            "date": "2020-07-06T23:43:31",
            "name": "[v4,1/3] eal: adjust barriers for IO on Armv8-a",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/10828/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/73353/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/73353/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Message-Id": "<20200706234333.26310-1-honnappa.nagarahalli@arm.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "To": "dev@dpdk.org, honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com,\n jerinj@marvell.com, hemant.agrawal@nxp.com, ajit.khaparde@broadcom.com,\n igorch@amazon.com, thomas@monjalon.net, viacheslavo@mellanox.com,\n arybchenko@solarflare.com, bruce.richardson@intel.com",
        "Cc": "nd@arm.com",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6744EA00C5;\n\tTue,  7 Jul 2020 01:43:51 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 518531DC7E;\n\tTue,  7 Jul 2020 01:43:50 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 2FA081DC0F\n for <dev@dpdk.org>; Tue,  7 Jul 2020 01:43:49 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 908E4C0A;\n Mon,  6 Jul 2020 16:43:48 -0700 (PDT)",
            "from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com\n [10.118.12.27])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CB693F718;\n Mon,  6 Jul 2020 16:43:48 -0700 (PDT)"
        ],
        "Subject": "[dpdk-dev] [PATCH v4 1/3] eal: adjust barriers for IO on Armv8-a",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "In-Reply-To": "<20200410164127.54229-1-gavin.hu@arm.com>",
        "Precedence": "list",
        "From": "Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>",
        "References": "<20200410164127.54229-1-gavin.hu@arm.com>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Errors-To": "dev-bounces@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Date": "Mon,  6 Jul 2020 18:43:31 -0500",
        "X-Mailman-Version": "2.1.15",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>"
    },
    "content": "Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy\natomicity memory model.\n\nArmv8-a memory model has been strengthened to require\nother-multi-copy atomicity. This property requires memory accesses\nfrom an observer to become visible to all other observers\nsimultaneously [3]. This means\n\na) A write arriving at an endpoint shared between multiple CPUs is\n   visible to all CPUs\nb) A write that is visible to all CPUs is also visible to all other\n   observers in the shareability domain\n\nThis allows for using cheaper DMB instructions in the place of DSB\nfor devices that are visible to all CPUs (i.e. devices that DPDK\ncaters to).\n\nPlease refer to [1], [2] and [3] for more information.\n\n[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f\n[2] https://www.youtube.com/watch?v=i6DayghhA8Q\n[3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/\n\nSigned-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\nTested-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n lib/librte_eal/arm/include/rte_atomic_64.h | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h\nindex 7b7099cdc..e42f69edc 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_64.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_64.h\n@@ -1,6 +1,6 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n  * Copyright(c) 2015 Cavium, Inc\n- * Copyright(c) 2019 Arm Limited\n+ * Copyright(c) 2020 Arm Limited\n  */\n \n #ifndef _RTE_ATOMIC_ARM64_H_\n@@ -19,11 +19,11 @@ extern \"C\" {\n #include <rte_compat.h>\n #include <rte_debug.h>\n \n-#define rte_mb() asm volatile(\"dsb sy\" : : : \"memory\")\n+#define rte_mb() asm volatile(\"dmb osh\" : : : \"memory\")\n \n-#define rte_wmb() asm volatile(\"dsb st\" : : : \"memory\")\n+#define rte_wmb() asm volatile(\"dmb oshst\" : : : \"memory\")\n \n-#define rte_rmb() asm volatile(\"dsb ld\" : : : \"memory\")\n+#define rte_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\n \n #define rte_smp_mb() asm volatile(\"dmb ish\" : : : \"memory\")\n \n@@ -37,9 +37,9 @@ extern \"C\" {\n \n #define rte_io_rmb() rte_rmb()\n \n-#define rte_cio_wmb() asm volatile(\"dmb oshst\" : : : \"memory\")\n+#define rte_cio_wmb() rte_wmb()\n \n-#define rte_cio_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\n+#define rte_cio_rmb() rte_rmb()\n \n /*------------------------ 128 bit atomic operations -------------------------*/\n \n",
    "prefixes": [
        "v4",
        "1/3"
    ]
}