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{
    "id": 7208,
    "url": "https://patches.dpdk.org/api/patches/7208/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443426751-4906-2-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1443426751-4906-2-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1443426751-4906-2-git-send-email-wenzhuo.lu@intel.com",
    "date": "2015-09-28T07:52:28",
    "name": "[dpdk-dev,1/4] ixgbe: 512 entries RSS table on x550",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6d0bb9dcc0a58fbe7a3923af1778ebb00f27bece",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443426751-4906-2-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/7208/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/7208/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D37EB56B7;\n\tMon, 28 Sep 2015 09:52:43 +0200 (CEST)",
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            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP; 28 Sep 2015 00:52:42 -0700",
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            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t8S7qZnZ004951; Mon, 28 Sep 2015 15:52:37 +0800",
            "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t8S7qYi7004947; \n\tMon, 28 Sep 2015 15:52:34 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.17,602,1437462000\"; d=\"scan'208\";a=\"569657371\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Mon, 28 Sep 2015 15:52:28 +0800",
        "Message-Id": "<1443426751-4906-2-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1443426751-4906-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1443426751-4906-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 1/4] ixgbe: 512 entries RSS table on x550",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Comparing with the older NICs, x550's RSS redirection table is enlarged to 512\nentries. As the original code is for the NICs which have a 128 entries RSS table,\nit means only part of the RSS table is set on x550. So, RSS cannot work as\nexpected on x550, it doesn't redirect the packets evenly.\nThis patch configs the entries beyond 128 on x550 to let RSS work well, and also\nupdate the query and update functions to support 512 entries.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 106 ++++++++++++++++++++++++++++++++++-----\n drivers/net/ixgbe/ixgbe_rxtx.c   |  18 +++++--\n 2 files changed, 109 insertions(+), 15 deletions(-)",
    "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex ec2918c..a1ef26f 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -2397,7 +2397,17 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n \t};\n \tdev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);\n-\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n+\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tdev_info->reta_size = ETH_RSS_RETA_SIZE_512;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n+\t\tbreak;\n+\t}\n+\n \tdev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;\n }\n \n@@ -3205,14 +3215,29 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n-\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n-\t\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n-\t\treturn -EINVAL;\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tif (reta_size != ETH_RSS_RETA_SIZE_512) {\n+\t\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table \"\n+\t\t\t\t\t\"configured (%d) doesn't match the \"\n+\t\t\t\t\t\"number hardware can supported (%d)\\n\",\n+\t\t\t\t\treta_size, ETH_RSS_RETA_SIZE_512);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table \"\n+\t\t\t\t\t\"configured (%d) doesn't match the \"\n+\t\t\t\t\t\"number hardware can supported (%d)\\n\",\n+\t\t\t\t\treta_size, ETH_RSS_RETA_SIZE_128);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n \t}\n \n-\tfor (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {\n+\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {\n \t\tidx = i / RTE_RETA_GROUP_SIZE;\n \t\tshift = i % RTE_RETA_GROUP_SIZE;\n \t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n@@ -3234,6 +3259,30 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);\n \t}\n \n+\tfor (i = ETH_RSS_RETA_SIZE_128; i < reta_size; i += IXGBE_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tIXGBE_4_BIT_MASK);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tif (mask == IXGBE_4_BIT_MASK)\n+\t\t\tr = 0;\n+\t\telse\n+\t\t\tr = IXGBE_READ_REG(hw,\n+\t\t\t\tIXGBE_ERETA((i - ETH_RSS_RETA_SIZE_128) >> 2));\n+\t\tfor (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n+\t\t\telse\n+\t\t\t\treta |= r & (IXGBE_8_BIT_MASK <<\n+\t\t\t\t\t\t(CHAR_BIT * j));\n+\t\t}\n+\t\tIXGBE_WRITE_REG(hw,\n+\t\t\tIXGBE_ERETA((i - ETH_RSS_RETA_SIZE_128) >> 2), reta);\n+\t}\n+\n \treturn 0;\n }\n \n@@ -3248,11 +3297,26 @@ ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n-\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n-\t\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n-\t\treturn -EINVAL;\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tif (reta_size != ETH_RSS_RETA_SIZE_512) {\n+\t\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table \"\n+\t\t\t\t\t\" configured (%d) doesn't match the \"\n+\t\t\t\t\t\"number hardware can supported (%d)\\n\",\n+\t\t\t\t\treta_size, ETH_RSS_RETA_SIZE_512);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table \"\n+\t\t\t\t\t\" configured (%d) doesn't match the \"\n+\t\t\t\t\t\"number hardware can supported (%d)\\n\",\n+\t\t\t\t\treta_size, ETH_RSS_RETA_SIZE_128);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n \t}\n \n \tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {\n@@ -3272,6 +3336,24 @@ ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \n+\tfor (i = ETH_RSS_RETA_SIZE_128; i < reta_size; i += IXGBE_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tIXGBE_4_BIT_MASK);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\treta = IXGBE_READ_REG(hw,\n+\t\t\t\tIXGBE_ERETA((i - ETH_RSS_RETA_SIZE_128) >> 2));\n+\t\tfor (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta_conf[idx].reta[shift + j] =\n+\t\t\t\t\t((reta >> (CHAR_BIT * j)) &\n+\t\t\t\t\t\tIXGBE_8_BIT_MASK);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex a598a72..a746ae7 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2790,7 +2790,7 @@ ixgbe_rss_configure(struct rte_eth_dev *dev)\n {\n \tstruct rte_eth_rss_conf rss_conf;\n \tstruct ixgbe_hw *hw;\n-\tuint32_t reta;\n+\tuint32_t reta = 0;\n \tuint16_t i;\n \tuint16_t j;\n \n@@ -2802,8 +2802,7 @@ ixgbe_rss_configure(struct rte_eth_dev *dev)\n \t * The byte-swap is needed because NIC registers are in\n \t * little-endian order.\n \t */\n-\treta = 0;\n-\tfor (i = 0, j = 0; i < 128; i++, j++) {\n+\tfor (i = 0, j = 0; i < ETH_RSS_RETA_SIZE_128; i++, j++) {\n \t\tif (j == dev->data->nb_rx_queues)\n \t\t\tj = 0;\n \t\treta = (reta << 8) | j;\n@@ -2812,6 +2811,19 @@ ixgbe_rss_configure(struct rte_eth_dev *dev)\n \t\t\t\t\trte_bswap32(reta));\n \t}\n \n+\tif ((hw->mac.type == ixgbe_mac_X550) ||\n+\t\t(hw->mac.type == ixgbe_mac_X550EM_x)) {\n+\t\tfor (i = 0, j = 0; i < (ETH_RSS_RETA_SIZE_512 - ETH_RSS_RETA_SIZE_128);\n+\t\t\ti++, j++) {\n+\t\t\tif (j == dev->data->nb_rx_queues)\n+\t\t\t\tj = 0;\n+\t\t\treta = (reta << 8) | j;\n+\t\t\tif ((i & 3) == 3)\n+\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_ERETA(i >> 2),\n+\t\t\t\t\t\trte_bswap32(reta));\n+\t\t}\n+\t}\n+\n \t/*\n \t * Configure the RSS key and the RSS protocols used to compute\n \t * the RSS hash of input packets.\n",
    "prefixes": [
        "dpdk-dev",
        "1/4"
    ]
}