Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/70766/?format=api
{ "id": 70766, "url": "https://patches.dpdk.org/api/patches/70766/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-5-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200603024016.30636-5-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200603024016.30636-5-qi.z.zhang@intel.com", "date": "2020-06-03T02:39:28", "name": "[04/52] net/ice/base: avoid undefined behavior", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "57875f6878747ef63e4a8aecefcfff4021de96c3", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-5-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 10300, "url": "https://patches.dpdk.org/api/series/10300/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10300", "date": "2020-06-03T02:39:24", "name": "net/ice: base code update", "version": 1, "mbox": "https://patches.dpdk.org/series/10300/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/70766/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/70766/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1820CA04EF;\n\tWed, 3 Jun 2020 04:37:02 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CD3331C0C3;\n\tWed, 3 Jun 2020 04:36:30 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 13EC11C002\n for <dev@dpdk.org>; Wed, 3 Jun 2020 04:36:28 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Jun 2020 19:36:28 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by orsmga001.jf.intel.com with ESMTP; 02 Jun 2020 19:36:26 -0700" ], "IronPort-SDR": [ "\n vlUaCTRx7QE1jy7k5CQ72SnxffBOxiAynJ42fxSYwnvUFU1XXL/QwIglzWhOi2KYh7eLQ6QUL3\n A4Kvha7QjU2w==", "\n KhtEtpDe0fg+JD3bJk5/3InBfat2ppoo1tMxEvB/q+1mSSwbr/HUwy1KCsRrDdKt2aqU6B79lP\n +t9aJ+3o8Auw==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,466,1583222400\"; d=\"scan'208\";a=\"347613879\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Bruce Allan <bruce.w.allan@intel.com>,\n \"Paul M . Stillwell Jr\" <paul.m.stillwell.jr@intel.com>", "Date": "Wed, 3 Jun 2020 10:39:28 +0800", "Message-Id": "<20200603024016.30636-5-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "References": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 04/52] net/ice/base: avoid undefined behavior", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When writing the driver's struct ice_tlan_ctx structure, do not write the\n8-bit element int_q_state with the associated internal-to-hardware field\nwhich is 122-bits, otherwise the helper function ice_write_byte() will use\nundefined behavior when setting the mask used for that write. This should\nnot cause any functional change and will avoid use of undefined behavior.\nAlso, update a comment to highlight this structure element is not written.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 17 +++++++++++++----\n drivers/net/ice/base/ice_common.h | 4 +++-\n drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-\n drivers/net/ice/ice_rxtx.c | 4 ++--\n 4 files changed, 19 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 17ffdee00..4b4555f6f 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -996,7 +996,7 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n \n \trlan_ctx->prefena = 1;\n \n-\tice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);\n+\tice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);\n \treturn ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);\n }\n \n@@ -1119,7 +1119,7 @@ ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,\n {\n \tu8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n \n-\tice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);\n+\tice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);\n \treturn ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);\n }\n \n@@ -1210,7 +1210,8 @@ ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n {\n \tu8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n \n-\tice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);\n+\tice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf,\n+\t\t ice_tx_drbell_q_ctx_info);\n \treturn ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);\n }\n \n@@ -3565,12 +3566,14 @@ ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n \n /**\n * ice_set_ctx - set context bits in packed structure\n+ * @hw: pointer to the hardware structure\n * @src_ctx: pointer to a generic non-packed context structure\n * @dest_ctx: pointer to memory for the packed structure\n * @ce_info: a description of the structure to be transformed\n */\n enum ice_status\n-ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,\n+\t const struct ice_ctx_ele *ce_info)\n {\n \tint f;\n \n@@ -3579,6 +3582,12 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n \t\t * using the correct size so that we are correct regardless\n \t\t * of the endianness of the machine.\n \t\t */\n+\t\tif (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {\n+\t\t\tice_debug(hw, ICE_DBG_QCTX,\n+\t\t\t\t \"Field %d width of %d bits larger than size of %d byte(s) ... skipping write\\n\",\n+\t\t\t\t f, ce_info[f].width, ce_info[f].size_of);\n+\t\t\tcontinue;\n+\t\t}\n \t\tswitch (ce_info[f].size_of) {\n \t\tcase sizeof(u8):\n \t\t\tice_write_byte(src_ctx, dest_ctx, &ce_info[f]);\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex 2a1077b90..6d971a644 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -114,7 +114,9 @@ enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);\n void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);\n extern const struct ice_ctx_ele ice_tlan_ctx_info[];\n enum ice_status\n-ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);\n+ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,\n+\t const struct ice_ctx_ele *ce_info);\n+\n enum ice_status\n ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,\n \t\tvoid *buf, u16 buf_size, struct ice_sq_cd *cd);\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex 99edcc8ae..012d129df 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -1135,7 +1135,7 @@ struct ice_tlan_ctx {\n \tu8 drop_ena;\n \tu8 cache_prof_idx;\n \tu8 pkt_shaper_prof_idx;\n-\tu8 int_q_state;\t/* width not needed - internal do not write */\n+\tu8 int_q_state;\t/* width not needed - internal - DO NOT WRITE!!! */\n };\n \n /* LAN Tx Completion Queue data */\ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex 1c9f31efd..5d6f693c5 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -481,7 +481,7 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \ttx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */\n \ttx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */\n \n-\tice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,\n+\tice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,\n \t\t ice_tlan_ctx_info);\n \n \ttxq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);\n@@ -653,7 +653,7 @@ ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \ttx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */\n \ttx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */\n \n-\tice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,\n+\tice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,\n \t\t ice_tlan_ctx_info);\n \n \ttxq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);\n", "prefixes": [ "04/52" ] }