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GET /api/patches/70764/?format=api
{ "id": 70764, "url": "https://patches.dpdk.org/api/patches/70764/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-3-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200603024016.30636-3-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200603024016.30636-3-qi.z.zhang@intel.com", "date": "2020-06-03T02:39:26", "name": "[02/52] net/ice/base: add FDIR program status WB macro", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "292652ef9f2c8500338ff01e6a399d8f8659f4a2", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200603024016.30636-3-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 10300, "url": "https://patches.dpdk.org/api/series/10300/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10300", "date": "2020-06-03T02:39:24", "name": "net/ice: base code update", "version": 1, "mbox": "https://patches.dpdk.org/series/10300/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/70764/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/70764/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 338E4A04EF;\n\tWed, 3 Jun 2020 04:36:43 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 606301C042;\n\tWed, 3 Jun 2020 04:36:27 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 34C901BF60\n for <dev@dpdk.org>; Wed, 3 Jun 2020 04:36:25 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Jun 2020 19:36:24 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by orsmga001.jf.intel.com with ESMTP; 02 Jun 2020 19:36:22 -0700" ], "IronPort-SDR": [ "\n bYyqOLDSVLEAMQMIprAtPrIoiYHA9kwoYzPZHUmI6+xz6T59CSOl5BevN37Ssl2QLwkJPUrL8f\n MtIpREXcv9lQ==", "\n 7n9sWgF2PjEcCC7WYZ6k2L43C4Qxr//bgs3omRiViDBicW/4jGLwvE0sCt76hBns/aB0eLqVSI\n 7DRvKviBcKoA==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,466,1583222400\"; d=\"scan'208\";a=\"347613866\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Yahui Cao <yahui.cao@intel.com>,\n \"Paul M . Stillwell Jr\" <paul.m.stillwell.jr@intel.com>", "Date": "Wed, 3 Jun 2020 10:39:26 +0800", "Message-Id": "<20200603024016.30636-3-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "References": "<20200603024016.30636-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 02/52] net/ice/base: add FDIR program status WB\n\tmacro", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add descriptor field offset and mask definition. It is used to parse\nFDIR rx descriptor field value.\n\nSigned-off-by: Yahui Cao <yahui.cao@intel.com>\nSigned-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_lan_tx_rx.h | 44 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 44 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex a0e284a8d..99edcc8ae 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -175,6 +175,50 @@ struct ice_fltr_desc {\n \t\t\t(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)\n #define ICE_FXD_FLTR_QW1_FDID_ZERO\t0x0ULL\n \n+/* definition for FD filter programming status descriptor WB format */\n+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S\t28\n+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M\t\\\n+\t\t\t(0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S)\n+\n+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S\t32\n+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M\t\\\n+\t\t\t(0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S)\n+\n+#define ICE_FXD_FLTR_WB_QW1_DD_S\t0\n+#define ICE_FXD_FLTR_WB_QW1_DD_M\t(0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)\n+#define ICE_FXD_FLTR_WB_QW1_DD_YES\t0x1ULL\n+\n+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S\t1\n+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M\t\\\n+\t\t\t\t(0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)\n+#define ICE_FXD_FLTR_WB_QW1_PROG_ADD\t0x0ULL\n+#define ICE_FXD_FLTR_WB_QW1_PROG_DEL\t0x1ULL\n+\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_S\t4\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_M\t(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_YES\t0x1ULL\n+\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S\t5\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M\t\\\n+\t\t\t\t(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES\t0x1ULL\n+\n+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S\t8\n+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M\t\\\n+\t\t\t\t(0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S)\n+\n+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S\t28\n+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M\t\\\n+\t\t\t\t(0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S)\n+\n+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S\t38\n+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M\t\\\n+\t\t\t\t(0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S)\n+\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M\t\\\n+\t\t\t\t(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)\n+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES\t0x1ULL\n+\n enum ice_rx_desc_status_bits {\n \t/* Note: These are predefined bit offsets */\n \tICE_RX_DESC_STATUS_DD_S\t\t\t= 0,\n", "prefixes": [ "02/52" ] }