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GET /api/patches/70741/?format=api
{ "id": 70741, "url": "https://patches.dpdk.org/api/patches/70741/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1591112869-78828-3-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1591112869-78828-3-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1591112869-78828-3-git-send-email-matan@mellanox.com", "date": "2020-06-02T15:47:47", "name": "[v3,2/4] common/mlx5: support DevX virtq stats operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a3f17a80f7432345f6c7f1aed854bd17f4345226", "submitter": { "id": 796, "url": "https://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1591112869-78828-3-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 10294, "url": "https://patches.dpdk.org/api/series/10294/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10294", "date": "2020-06-02T15:47:45", "name": "vhost: support vDPA virtio queue statistics", "version": 3, "mbox": "https://patches.dpdk.org/series/10294/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/70741/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/70741/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0B932A0514;\n\tTue, 2 Jun 2020 17:48:26 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E551B1BFE6;\n\tTue, 2 Jun 2020 17:48:25 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 5DC721BFE5\n for <dev@dpdk.org>; Tue, 2 Jun 2020 17:48:23 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 2 Jun 2020 18:48:19 +0300", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 052Fm1YH012921;\n Tue, 2 Jun 2020 18:48:19 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>", "Cc": "dev@dpdk.org, Shahaf Shuler <shahafs@mellanox.com>", "Date": "Tue, 2 Jun 2020 15:47:47 +0000", "Message-Id": "<1591112869-78828-3-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1591112869-78828-1-git-send-email-matan@mellanox.com>", "References": "<1588694084-381748-1-git-send-email-matan@mellanox.com>\n <1591112869-78828-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v3 2/4] common/mlx5: support DevX virtq stats\n\toperations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add DevX API to create and query virtio queue statistics from the HW.\nThe next counters are supported by the HW per virtio queue:\n\treceived_desc.\n\tcompleted_desc.\n\terror_cqes.\n\tbad_desc_errors.\n\texceed_max_chain.\n\tinvalid_buffer.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 73 +++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 38 +++++++++++++\n drivers/common/mlx5/mlx5_prm.h | 26 ++++++++-\n drivers/common/mlx5/rte_common_mlx5_version.map | 2 +\n 4 files changed, 138 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex fba485e..4bf22ce 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -464,6 +464,9 @@ struct mlx5_devx_obj *\n \tattr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n \t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);\n+\tattr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t\tgeneral_obj_types) &\n+\t\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\n@@ -1258,6 +1261,7 @@ struct mlx5_devx_obj *\n \tMLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);\n \tMLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);\n \tMLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);\n+\tMLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);\n \tMLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);\n \tvirtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n \t\t\t\t\t\t sizeof(out));\n@@ -1532,3 +1536,72 @@ struct mlx5_devx_obj *\n \t}\n \treturn ret;\n }\n+\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_virtio_q_counters(void *ctx)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tstruct mlx5_devx_obj *couners_obj = rte_zmalloc(__func__,\n+\t\t\t\t\t\t sizeof(*couners_obj), 0);\n+\tvoid *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);\n+\n+\tif (!couners_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate virtio queue counters data.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);\n+\tcouners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n+\t\t\t\t\t\t sizeof(out));\n+\tif (!couners_obj->obj) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create virtio queue counters Obj using\"\n+\t\t\t\" DevX.\");\n+\t\trte_free(couners_obj);\n+\t\treturn NULL;\n+\t}\n+\tcouners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\treturn couners_obj;\n+}\n+\n+int\n+mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,\n+\t\t\t\t struct mlx5_devx_virtio_q_couners_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};\n+\tvoid *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);\n+\tvoid *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,\n+\t\t\t\t\t virtio_q_counters);\n+\tint ret;\n+\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_QUERY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);\n+\tret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,\n+\t\t\t\t\tsizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to query virtio q counters using DevX.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\tattr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t\t received_desc);\n+\tattr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t\t completed_desc);\n+\tattr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t error_cqes);\n+\tattr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t\t bad_desc_errors);\n+\tattr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t\t exceed_max_chain);\n+\tattr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,\n+\t\t\t\t\tinvalid_buffer);\n+\treturn ret;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 49b174a..59a70a0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -64,6 +64,7 @@ struct mlx5_hca_vdpa_attr {\n \tuint32_t event_mode:3;\n \tuint32_t log_doorbell_stride:5;\n \tuint32_t log_doorbell_bar_size:5;\n+\tuint32_t queue_counters_valid:1;\n \tuint32_t max_num_virtio_queues;\n \tstruct {\n \t\tuint32_t a;\n@@ -272,6 +273,7 @@ struct mlx5_devx_virtq_attr {\n \tuint32_t qp_id;\n \tuint32_t queue_index;\n \tuint32_t tis_id;\n+\tuint32_t counters_obj_id;\n \tuint64_t dirty_bitmap_addr;\n \tuint64_t type;\n \tuint64_t desc_addr;\n@@ -300,6 +302,15 @@ struct mlx5_devx_qp_attr {\n \tuint64_t wq_umem_offset;\n };\n \n+struct mlx5_devx_virtio_q_couners_attr {\n+\tuint64_t received_desc;\n+\tuint64_t completed_desc;\n+\tuint32_t error_cqes;\n+\tuint32_t bad_desc_errors;\n+\tuint32_t exceed_max_chain;\n+\tuint32_t invalid_buffer;\n+};\n+\n /* mlx5_devx_cmds.c */\n \n __rte_internal\n@@ -374,4 +385,31 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,\n int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,\n \t\t\t struct mlx5_devx_rqt_attr *rqt_attr);\n \n+/**\n+ * Create virtio queue counters object DevX API.\n+ *\n+ * @param[in] ctx\n+ * Device context.\n+\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+__rte_internal\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);\n+\n+/**\n+ * Query virtio queue counters object using DevX API.\n+ *\n+ * @param[in] couners_obj\n+ * Pointer to virtq object structure.\n+ * @param [in/out] attr\n+ * Pointer to virtio queue counters attributes structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+__rte_internal\n+int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,\n+\t\t\t\t struct mlx5_devx_virtio_q_couners_attr *attr);\n+\n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex e4ef2ac..5fc10d6 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -949,6 +949,7 @@ enum {\n \n enum {\n \tMLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),\n+\tMLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),\n };\n \n enum {\n@@ -2006,6 +2007,7 @@ struct mlx5_ifc_create_cq_in_bits {\n \n enum {\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n+\tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n@@ -2024,6 +2026,27 @@ struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+struct mlx5_ifc_virtio_q_counters_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x40];\n+\tu8 received_desc[0x40];\n+\tu8 completed_desc[0x40];\n+\tu8 error_cqes[0x20];\n+\tu8 bad_desc_errors[0x20];\n+\tu8 exceed_max_chain[0x20];\n+\tu8 invalid_buffer[0x20];\n+\tu8 reserved_at_180[0x50];\n+};\n+\n+struct mlx5_ifc_create_virtio_q_counters_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n+};\n+\n+struct mlx5_ifc_query_virtio_q_counters_out_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n+};\n enum {\n \tMLX5_VIRTQ_STATE_INIT = 0,\n \tMLX5_VIRTQ_STATE_RDY = 1,\n@@ -2064,7 +2087,8 @@ struct mlx5_ifc_virtio_q_bits {\n \tu8 umem_3_id[0x20];\n \tu8 umem_3_size[0x20];\n \tu8 umem_3_offset[0x40];\n-\tu8 reserved_at_300[0x100];\n+\tu8 counter_set_id[0x20];\n+\tu8 reserved_at_320[0xe0];\n };\n \n struct mlx5_ifc_virtio_net_q_bits {\ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex 350e771..b3410df 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -15,6 +15,7 @@ INTERNAL {\n \tmlx5_devx_cmd_create_tir;\n \tmlx5_devx_cmd_create_td;\n \tmlx5_devx_cmd_create_tis;\n+\tmlx5_devx_cmd_create_virtio_q_counters;\n \tmlx5_devx_cmd_create_virtq;\n \tmlx5_devx_cmd_destroy;\n \tmlx5_devx_cmd_flow_counter_alloc;\n@@ -28,6 +29,7 @@ INTERNAL {\n \tmlx5_devx_cmd_modify_virtq;\n \tmlx5_devx_cmd_qp_query_tis_td;\n \tmlx5_devx_cmd_query_hca_attr;\n+\tmlx5_devx_cmd_query_virtio_q_counters;\n \tmlx5_devx_cmd_query_virtq;\n \tmlx5_devx_get_out_command_status;\n \n", "prefixes": [ "v3", "2/4" ] }