Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/68528/?format=api
{ "id": 68528, "url": "https://patches.dpdk.org/api/patches/68528/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200415084810.20816-8-alvinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200415084810.20816-8-alvinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200415084810.20816-8-alvinx.zhang@intel.com", "date": "2020-04-15T08:48:06", "name": "[v4,07/11] net/igc: implement flow control ops", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "963c7aeed5abb21cb2b76c199dd9326884e9f1f4", "submitter": { "id": 1398, "url": "https://patches.dpdk.org/api/people/1398/?format=api", "name": "Alvin Zhang", "email": "alvinx.zhang@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200415084810.20816-8-alvinx.zhang@intel.com/mbox/", "series": [ { "id": 9387, "url": "https://patches.dpdk.org/api/series/9387/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9387", "date": "2020-04-15T08:47:59", "name": "igc PMD", "version": 4, "mbox": "https://patches.dpdk.org/series/9387/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/68528/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/68528/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B3FEAA0563;\n\tWed, 15 Apr 2020 10:50:45 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 239081D5DF;\n\tWed, 15 Apr 2020 10:49:17 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id D83601D5DA\n for <dev@dpdk.org>; Wed, 15 Apr 2020 10:49:10 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Apr 2020 01:49:10 -0700", "from shwdenpg235.ccr.corp.intel.com ([10.240.182.60])\n by fmsmga001.fm.intel.com with ESMTP; 15 Apr 2020 01:49:08 -0700" ], "IronPort-SDR": [ "\n YIlgzanrApQpqHaNt7YJv9bl3meIv8vq4TZ8lqAtHNhrtWriXTdEYiBotVqcJZfbrs4oXuJ1zs\n Ol58v6eclppQ==", "\n MlLPzhLraoW7Kw1960vCvDVYMrH6tNhxSVNcSDC+EaERmkfn1S49JKMQTuIdUlz/psJuufnax6\n 5DqxZIHFiEQA==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,386,1580803200\"; d=\"scan'208\";a=\"363616116\"", "From": "alvinx.zhang@intel.com", "To": "dev@dpdk.org", "Cc": "xiaolong.ye@intel.com", "Date": "Wed, 15 Apr 2020 16:48:06 +0800", "Message-Id": "<20200415084810.20816-8-alvinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20200415084810.20816-1-alvinx.zhang@intel.com>", "References": "<20200413063037.13728-2-alvinx.zhang@intel.com>\n <20200415084810.20816-1-alvinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 07/11] net/igc: implement flow control ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Alvin Zhang <alvinx.zhang@intel.com>\n\nUpdate feature list too.\n\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\n\nV4: Modify codes according to comments.\n---\n doc/guides/nics/features/igc.ini | 1 +\n drivers/net/igc/igc_ethdev.c | 121 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 122 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/igc.ini b/doc/guides/nics/features/igc.ini\nindex e0bef82..a364e04 100644\n--- a/doc/guides/nics/features/igc.ini\n+++ b/doc/guides/nics/features/igc.ini\n@@ -27,6 +27,7 @@ Basic stats = Y\n Extended stats = Y\n Stats per queue = Y\n Rx interrupt = Y\n+Flow control = Y\n Linux UIO = Y\n Linux VFIO = Y\n x86-64 = Y\ndiff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c\nindex becac98..c31c3eb 100644\n--- a/drivers/net/igc/igc_ethdev.c\n+++ b/drivers/net/igc/igc_ethdev.c\n@@ -213,6 +213,10 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);\n static int\n eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);\n+static int\n+eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);\n+static int\n+eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);\n \n static const struct eth_dev_ops eth_igc_ops = {\n \t.dev_configure\t\t= eth_igc_configure,\n@@ -259,6 +263,8 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t.queue_stats_mapping_set = eth_igc_queue_stats_mapping_set,\n \t.rx_queue_intr_enable\t= eth_igc_rx_queue_intr_enable,\n \t.rx_queue_intr_disable\t= eth_igc_rx_queue_intr_disable,\n+\t.flow_ctrl_get\t\t= eth_igc_flow_ctrl_get,\n+\t.flow_ctrl_set\t\t= eth_igc_flow_ctrl_set,\n };\n \n /*\n@@ -2067,6 +2073,121 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n }\n \n static int\n+eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint32_t ctrl;\n+\tint tx_pause;\n+\tint rx_pause;\n+\n+\tfc_conf->pause_time = hw->fc.pause_time;\n+\tfc_conf->high_water = hw->fc.high_water;\n+\tfc_conf->low_water = hw->fc.low_water;\n+\tfc_conf->send_xon = hw->fc.send_xon;\n+\tfc_conf->autoneg = hw->mac.autoneg;\n+\n+\t/*\n+\t * Return rx_pause and tx_pause status according to actual setting of\n+\t * the TFCE and RFCE bits in the CTRL register.\n+\t */\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tif (ctrl & IGC_CTRL_TFCE)\n+\t\ttx_pause = 1;\n+\telse\n+\t\ttx_pause = 0;\n+\n+\tif (ctrl & IGC_CTRL_RFCE)\n+\t\trx_pause = 1;\n+\telse\n+\t\trx_pause = 0;\n+\n+\tif (rx_pause && tx_pause)\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\telse if (rx_pause)\n+\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n+\telse if (tx_pause)\n+\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n+\telse\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\n+\treturn 0;\n+}\n+\n+static int\n+eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint32_t rx_buf_size;\n+\tuint32_t max_high_water;\n+\tuint32_t rctl;\n+\tint err;\n+\n+\tif (fc_conf->autoneg != hw->mac.autoneg)\n+\t\treturn -ENOTSUP;\n+\n+\trx_buf_size = igc_get_rx_buffer_size(hw);\n+\tPMD_DRV_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n+\n+\t/* At least reserve one Ethernet frame for watermark */\n+\tmax_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;\n+\tif (fc_conf->high_water > max_high_water ||\n+\t\tfc_conf->high_water < fc_conf->low_water) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Incorrect high(%u)/low(%u) water value, max is %u\",\n+\t\t\tfc_conf->high_water, fc_conf->low_water,\n+\t\t\tmax_high_water);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (fc_conf->mode) {\n+\tcase RTE_FC_NONE:\n+\t\thw->fc.requested_mode = igc_fc_none;\n+\t\tbreak;\n+\tcase RTE_FC_RX_PAUSE:\n+\t\thw->fc.requested_mode = igc_fc_rx_pause;\n+\t\tbreak;\n+\tcase RTE_FC_TX_PAUSE:\n+\t\thw->fc.requested_mode = igc_fc_tx_pause;\n+\t\tbreak;\n+\tcase RTE_FC_FULL:\n+\t\thw->fc.requested_mode = igc_fc_full;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unsupported fc mode: %u\", fc_conf->mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->fc.pause_time = fc_conf->pause_time;\n+\thw->fc.high_water = fc_conf->high_water;\n+\thw->fc.low_water = fc_conf->low_water;\n+\thw->fc.send_xon\t = fc_conf->send_xon;\n+\n+\terr = igc_setup_link_generic(hw);\n+\tif (err == IGC_SUCCESS) {\n+\t\t/**\n+\t\t * check if we want to forward MAC frames - driver doesn't have\n+\t\t * native capability to do that, so we'll write the registers\n+\t\t * ourselves\n+\t\t **/\n+\t\trctl = IGC_READ_REG(hw, IGC_RCTL);\n+\n+\t\t/* set or clear MFLCN.PMCF bit depending on configuration */\n+\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n+\t\t\trctl |= IGC_RCTL_PMCF;\n+\t\telse\n+\t\t\trctl &= ~IGC_RCTL_PMCF;\n+\n+\t\tIGC_WRITE_REG(hw, IGC_RCTL, rctl);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tPMD_DRV_LOG(ERR, \"igc_setup_link_generic = 0x%x\", err);\n+\treturn -EIO;\n+}\n+\n+static int\n eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tstruct rte_pci_device *pci_dev)\n {\n", "prefixes": [ "v4", "07/11" ] }