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GET /api/patches/68159/?format=api
{ "id": 68159, "url": "https://patches.dpdk.org/api/patches/68159/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200410164127.54229-1-gavin.hu@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200410164127.54229-1-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200410164127.54229-1-gavin.hu@arm.com", "date": "2020-04-10T16:41:20", "name": "[RFC,v2,0/7] introduce new barrier class and use it for mlx5 PMD", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 1018, "url": "https://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200410164127.54229-1-gavin.hu@arm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/68159/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/68159/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C732CA0598;\n\tFri, 10 Apr 2020 18:41:44 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 35AC61D5A9;\n\tFri, 10 Apr 2020 18:41:44 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 3EB611D595\n for <dev@dpdk.org>; Fri, 10 Apr 2020 18:41:42 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0C9030E;\n Fri, 10 Apr 2020 09:41:41 -0700 (PDT)", "from net-arm-thunderx2-01.shanghai.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7E4683F52E;\n Fri, 10 Apr 2020 09:41:37 -0700 (PDT)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,\n rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com,\n viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com,\n ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com,\n steve.capper@arm.com", "Date": "Sat, 11 Apr 2020 00:41:20 +0800", "Message-Id": "<20200410164127.54229-1-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200213123854.203566-1-gavin.hu@arm.com>", "References": "<20200213123854.203566-1-gavin.hu@arm.com>", "Subject": "[dpdk-dev] [PATCH RFC v2 0/7] introduce new barrier class and use\n\tit for mlx5 PMD", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "To order writes to various memory types, 'sfence' is required for x86,\nand 'dmb oshst' is required for aarch64. \n\nBut within DPDK, there is no abstracted barriers covers this\ncombination: sfence(x86)/dmb(aarch64).\n\nSo introduce a new barrier class - rte_dma_*mb for this combination, \n\nDoorbell rings are typical use cases of this new barrier class, which\nrequires something ready in the memory before letting HW aware.\n\nAs a note, rte_io_wmb and rte_cio_wmb are compiler barriers for x86, while\nrte_wmb is 'dsb' for aarch64.\n\nIn the joint preliminary testing between Arm and Ampere, 8%~13%\nperformance boost was measured.\n\nAs there is no functionality changes, it will not impact x86. \n\nGavin Hu (6):\n eal: introduce new class of barriers for DMA use cases\n net/mlx5: dmb for immediate doorbell ring on aarch64\n net/mlx5: relax barrier to order UAR writes on aarch64\n net/mlx5: relax barrier for aarch64\n net/mlx5: add descriptive comment for a barrier\n doc: clarify one configuration in mlx5 guide\n\nPhil Yang (1):\n net/mlx5: relax ordering for multi-packet RQ buffer refcnt\n\n doc/guides/nics/mlx5.rst | 6 ++--\n drivers/net/mlx5/mlx5_rxq.c | 2 +-\n drivers/net/mlx5/mlx5_rxtx.c | 16 ++++++-----\n drivers/net/mlx5/mlx5_rxtx.h | 14 ++++++----\n lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++\n lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++\n lib/librte_eal/include/generic/rte_atomic.h | 31 +++++++++++++++++++++\n lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++\n lib/librte_eal/x86/include/rte_atomic.h | 6 ++++\n 9 files changed, 78 insertions(+), 15 deletions(-)", "diff": null, "prefixes": [ "RFC", "v2", "0/7" ] }