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GET /api/patches/67985/?format=api
{ "id": 67985, "url": "https://patches.dpdk.org/api/patches/67985/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200408082921.31000-20-mk@semihalf.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200408082921.31000-20-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200408082921.31000-20-mk@semihalf.com", "date": "2020-04-08T08:29:10", "name": "[v3,19/30] net/ena: add support for large LLQ headers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3ddcde2c5047abd75f5def85bd51d905595369ee", "submitter": { "id": 786, "url": "https://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200408082921.31000-20-mk@semihalf.com/mbox/", "series": [ { "id": 9246, "url": "https://patches.dpdk.org/api/series/9246/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9246", "date": "2020-04-08T08:28:51", "name": "Update ENA driver to v2.1.0", "version": 3, "mbox": "https://patches.dpdk.org/series/9246/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67985/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/67985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E02F1A0597;\n\tWed, 8 Apr 2020 10:32:45 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E76FE1C1B5;\n\tWed, 8 Apr 2020 10:29:55 +0200 (CEST)", "from mail-lf1-f68.google.com (mail-lf1-f68.google.com\n [209.85.167.68]) by dpdk.org (Postfix) with ESMTP id F15071C192\n for <dev@dpdk.org>; Wed, 8 Apr 2020 10:29:49 +0200 (CEST)", "by mail-lf1-f68.google.com with SMTP id k28so4466226lfe.10\n for <dev@dpdk.org>; Wed, 08 Apr 2020 01:29:49 -0700 (PDT)", "from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl.\n [193.106.246.138])\n by smtp.gmail.com with ESMTPSA id e8sm765685lja.3.2020.04.08.01.29.47\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 08 Apr 2020 01:29:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20150623.gappssmtp.com; s=20150623;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=lpv95Elv/MKF4d3EuMJ1iuhEwO5iW/FYRbl57Xpd4xo=;\n b=Tcaj2n9vaxIHAUlhr9d+zjYqN76ugR+sXkEPxPThY7cel+LnbgHMjrunOZwyGqVIUj\n tTva3UJ1bkJD3PNxGcyTpJGJBWCeoUXzvmtTBFj4WlAEDA12KW04/NjetUm5n6zVoSM2\n Q6I+nJMjtj3uQD2VR5+c2BnZNpt8omyAtTAw43ZaGZ9f0zw7nCrqR1dKoPyoULRpFTHl\n rwCkxF/DwbInWJmTM+WpcWByJ9t6QVPIRB1myGTVmSgIbw4Fy9nnCVmbWPUbNAmDdoKK\n c3oPpu5MYeUskBvx/hzdRySuDAdvEd51umNyT5xk3PK/hF9rp9DEP1pPhwJ5J7877wI1\n lSHw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=lpv95Elv/MKF4d3EuMJ1iuhEwO5iW/FYRbl57Xpd4xo=;\n b=dZLRjDNG8zNRWoEvV2IB3UG1lfBmn8pm2fgIwUQF0lBlUYhp7B6ogMrmYFMCgnfTwb\n 4K33Udq0zwWOLcHCu6yEhbhpZRTPRa8bKr+nQE+zJhXJCLngkNwcm5wdv0RwSVFtZpNf\n MXH3/EByrM5qmWmQ8VBAzRmrxSLNCj1TswNQcpcZztvDXcSunAgcg9SJQ8EUhIs8d1oi\n EzDRja2I0sGaUYcbIZ397sVXJZ1+UwUvsxax2sKl5psexZqfeo7RjL0pINAUqIxLU3yp\n RqcvLZ+yQiES1Wi3XWEHMXvuhFE9Zq3fJd02D+m14gBE3R8lcj/H3ZrpMLZxOR7a2E1r\n tw3A==", "X-Gm-Message-State": "AGi0PuZJhNJY/20jCtjJH7Vet6DObsXkq2lq4hPPDOshkBacYvMvFOn7\n kZNTnBsD50y/VN1UHc9obNBugZTD+MY=", "X-Google-Smtp-Source": "\n APiQypL8l6x5XaSsMtD1OKGhd4vODPX7aV66c8bJDL+jZSDt4cgoevqYmGAO6ArELg/S2fXIgTp1ag==", "X-Received": "by 2002:a05:6512:6cf:: with SMTP id\n u15mr3783726lff.98.1586334589102;\n Wed, 08 Apr 2020 01:29:49 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com,\n igorch@amazon.com, ferruh.yigit@intel.com, arybchenko@solarflare.com,\n Michal Krawczyk <mk@semihalf.com>", "Date": "Wed, 8 Apr 2020 10:29:10 +0200", "Message-Id": "<20200408082921.31000-20-mk@semihalf.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20200408082921.31000-1-mk@semihalf.com>", "References": "<20200408082921.31000-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 19/30] net/ena: add support for large LLQ\n\theaders", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Default LLQ (Low-latency queue) maximum header size is 96 bytes and can\nbe too small for some types of packets - like IPv6 packets with multiple\nextension. This can be fixed, by using large LLQ headers.\n\nIf the device supports larger LLQ headers, the user can activate them by\nusing device argument 'large_llq_hdr' with value '1'.\n\nIf the device isn't supporting this feature, the default value (96B)\nwill be used.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Guy Tzalik <gtzalik@amazon.com>\n---\nv2:\n * Use devargs instead of compilation options\n\nv3:\n * Fix commit log - explain LLQ abbreviation, motivation behind this\n change and mention about new device argument\n * Update copyright date of the modified file\n * Add release notes\n\n doc/guides/nics/ena.rst | 10 ++-\n doc/guides/rel_notes/release_20_05.rst | 6 ++\n drivers/net/ena/ena_ethdev.c | 110 +++++++++++++++++++++++--\n drivers/net/ena/ena_ethdev.h | 2 +\n 4 files changed, 121 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst\nindex bbf27f235a..0b9622ac85 100644\n--- a/doc/guides/nics/ena.rst\n+++ b/doc/guides/nics/ena.rst\n@@ -1,5 +1,5 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n- Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.\n+ Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.\n All rights reserved.\n \n ENA Poll Mode Driver\n@@ -95,6 +95,14 @@ Configuration information\n * **CONFIG_RTE_LIBRTE_ENA_COM_DEBUG** (default n): Enables or disables debug\n logging of low level tx/rx logic in ena_com(base) within the ENA PMD driver.\n \n+**Runtime Configuration Parameters**\n+\n+ * **large_llq_hdr** (default 0)\n+\n+ Enables or disables usage of large LLQ headers. This option will have\n+ effect only if the device also supports large LLQ headers. Otherwise, the\n+ default value will be used.\n+\n **ENA Configuration Parameters**\n \n * **Number of Queues**\ndiff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst\nindex 2596269da5..7c73fe8fd5 100644\n--- a/doc/guides/rel_notes/release_20_05.rst\n+++ b/doc/guides/rel_notes/release_20_05.rst\n@@ -78,6 +78,12 @@ New Features\n * Hierarchial Scheduling with DWRR and SP.\n * Single rate - Two color, Two rate - Three color shaping.\n \n+* **Updated Amazon ena driver.**\n+\n+ Updated ena PMD with new features and improvements, including:\n+\n+ * Added support for large LLQ (Low-latency queue) headers.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex d0cd0e49c8..fdcbe53c1c 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -13,6 +13,7 @@\n #include <rte_errno.h>\n #include <rte_version.h>\n #include <rte_net.h>\n+#include <rte_kvargs.h>\n \n #include \"ena_ethdev.h\"\n #include \"ena_logs.h\"\n@@ -82,6 +83,9 @@ struct ena_stats {\n #define ENA_STAT_GLOBAL_ENTRY(stat) \\\n \tENA_STAT_ENTRY(stat, dev)\n \n+/* Device arguments */\n+#define ENA_DEVARG_LARGE_LLQ_HDR \"large_llq_hdr\"\n+\n /*\n * Each rte_memzone should have unique name.\n * To satisfy it, count number of allocation and add it to name.\n@@ -231,6 +235,11 @@ static int ena_xstats_get_by_id(struct rte_eth_dev *dev,\n \t\t\t\tconst uint64_t *ids,\n \t\t\t\tuint64_t *values,\n \t\t\t\tunsigned int n);\n+static int ena_process_bool_devarg(const char *key,\n+\t\t\t\t const char *value,\n+\t\t\t\t void *opaque);\n+static int ena_parse_devargs(struct ena_adapter *adapter,\n+\t\t\t struct rte_devargs *devargs);\n \n static const struct eth_dev_ops ena_dev_ops = {\n \t.dev_configure = ena_dev_configure,\n@@ -842,7 +851,8 @@ static int ena_check_valid_conf(struct ena_adapter *adapter)\n }\n \n static int\n-ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx)\n+ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,\n+\t\t bool use_large_llq_hdr)\n {\n \tstruct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;\n \tstruct ena_com_dev *ena_dev = ctx->ena_dev;\n@@ -895,6 +905,21 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx)\n \tmax_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);\n \tmax_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);\n \n+\tif (use_large_llq_hdr) {\n+\t\tif ((llq->entry_size_ctrl_supported &\n+\t\t ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&\n+\t\t (ena_dev->tx_mem_queue_type ==\n+\t\t ENA_ADMIN_PLACEMENT_POLICY_DEV)) {\n+\t\t\tmax_tx_queue_size /= 2;\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Forcing large headers and decreasing maximum TX queue size to %d\\n\",\n+\t\t\t\tmax_tx_queue_size);\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"Forcing large headers failed: LLQ is disabled or device does not support large headers\\n\");\n+\t\t}\n+\t}\n+\n \tif (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {\n \t\tPMD_INIT_LOG(ERR, \"Invalid queue size\");\n \t\treturn -EFAULT;\n@@ -1594,14 +1619,25 @@ static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,\n }\n \n static inline void\n-set_default_llq_configurations(struct ena_llq_configurations *llq_config)\n+set_default_llq_configurations(struct ena_llq_configurations *llq_config,\n+\t\t\t struct ena_admin_feature_llq_desc *llq,\n+\t\t\t bool use_large_llq_hdr)\n {\n \tllq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;\n-\tllq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;\n \tllq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;\n \tllq_config->llq_num_decs_before_header =\n \t\tENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;\n-\tllq_config->llq_ring_entry_size_value = 128;\n+\n+\tif (use_large_llq_hdr &&\n+\t (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {\n+\t\tllq_config->llq_ring_entry_size =\n+\t\t\tENA_ADMIN_LIST_ENTRY_SIZE_256B;\n+\t\tllq_config->llq_ring_entry_size_value = 256;\n+\t} else {\n+\t\tllq_config->llq_ring_entry_size =\n+\t\t\tENA_ADMIN_LIST_ENTRY_SIZE_128B;\n+\t\tllq_config->llq_ring_entry_size_value = 128;\n+\t}\n }\n \n static int\n@@ -1740,6 +1776,12 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \tsnprintf(adapter->name, ENA_NAME_MAX_LEN, \"ena_%d\",\n \t\t adapter->id_number);\n \n+\trc = ena_parse_devargs(adapter, pci_dev->device.devargs);\n+\tif (rc != 0) {\n+\t\tPMD_INIT_LOG(CRIT, \"Failed to parse devargs\\n\");\n+\t\tgoto err;\n+\t}\n+\n \t/* device specific initialization routine */\n \trc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);\n \tif (rc) {\n@@ -1748,7 +1790,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \tadapter->wd_state = wd_state;\n \n-\tset_default_llq_configurations(&llq_config);\n+\tset_default_llq_configurations(&llq_config, &get_feat_ctx.llq,\n+\t\tadapter->use_large_llq_hdr);\n \trc = ena_set_queues_placement_policy(adapter, ena_dev,\n \t\t\t\t\t &get_feat_ctx.llq, &llq_config);\n \tif (unlikely(rc)) {\n@@ -1766,7 +1809,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \tcalc_queue_ctx.get_feat_ctx = &get_feat_ctx;\n \n \tmax_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);\n-\trc = ena_calc_io_queue_size(&calc_queue_ctx);\n+\trc = ena_calc_io_queue_size(&calc_queue_ctx,\n+\t\tadapter->use_large_llq_hdr);\n \tif (unlikely((rc != 0) || (max_num_io_queues == 0))) {\n \t\trc = -EFAULT;\n \t\tgoto err_device_destroy;\n@@ -2582,6 +2626,59 @@ static int ena_xstats_get_by_id(struct rte_eth_dev *dev,\n \treturn valid;\n }\n \n+static int ena_process_bool_devarg(const char *key,\n+\t\t\t\t const char *value,\n+\t\t\t\t void *opaque)\n+{\n+\tstruct ena_adapter *adapter = opaque;\n+\tbool bool_value;\n+\n+\t/* Parse the value. */\n+\tif (strcmp(value, \"1\") == 0) {\n+\t\tbool_value = true;\n+\t} else if (strcmp(value, \"0\") == 0) {\n+\t\tbool_value = false;\n+\t} else {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\\n\",\n+\t\t\tvalue, key);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Now, assign it to the proper adapter field. */\n+\tif (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))\n+\t\tadapter->use_large_llq_hdr = bool_value;\n+\n+\treturn 0;\n+}\n+\n+static int ena_parse_devargs(struct ena_adapter *adapter,\n+\t\t\t struct rte_devargs *devargs)\n+{\n+\tstatic const char * const allowed_args[] = {\n+\t\tENA_DEVARG_LARGE_LLQ_HDR,\n+\t};\n+\tstruct rte_kvargs *kvlist;\n+\tint rc;\n+\n+\tif (devargs == NULL)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, allowed_args);\n+\tif (kvlist == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid device arguments: %s\\n\",\n+\t\t\tdevargs->args);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,\n+\t\tena_process_bool_devarg, adapter);\n+\n+\trte_kvargs_free(kvlist);\n+\n+\treturn rc;\n+}\n+\n /*********************************************************************\n * PMD configuration\n *********************************************************************/\n@@ -2608,6 +2705,7 @@ static struct rte_pci_driver rte_ena_pmd = {\n RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);\n RTE_PMD_REGISTER_KMOD_DEP(net_ena, \"* igb_uio | uio_pci_generic | vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR \"=<0|1>\");\n \n RTE_INIT(ena_init_log)\n {\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex 1f320088ac..ed3674b202 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -200,6 +200,8 @@ struct ena_adapter {\n \tbool trigger_reset;\n \n \tbool wd_state;\n+\n+\tbool use_large_llq_hdr;\n };\n \n #endif /* _ENA_ETHDEV_H_ */\n", "prefixes": [ "v3", "19/30" ] }