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GET /api/patches/67601/?format=api
{ "id": 67601, "url": "https://patches.dpdk.org/api/patches/67601/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200401142127.13715-17-mk@semihalf.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200401142127.13715-17-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200401142127.13715-17-mk@semihalf.com", "date": "2020-04-01T14:21:14", "name": "[v2,16/29] net/ena: refactor getting IO queues capabilities", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a9e87d79be7b609e5dfb5ef5e3fb511ce082181f", "submitter": { "id": 786, "url": "https://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200401142127.13715-17-mk@semihalf.com/mbox/", "series": [ { "id": 9153, "url": "https://patches.dpdk.org/api/series/9153/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9153", "date": "2020-04-01T14:20:58", "name": "Update ENA driver to v2.1.0", "version": 2, "mbox": "https://patches.dpdk.org/series/9153/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67601/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/67601/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C2D06A057B;\n\tWed, 1 Apr 2020 16:24:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7B2231C0C6;\n\tWed, 1 Apr 2020 16:22:02 +0200 (CEST)", "from mail-lj1-f177.google.com (mail-lj1-f177.google.com\n [209.85.208.177]) by dpdk.org (Postfix) with ESMTP id E62981C0B9\n for <dev@dpdk.org>; Wed, 1 Apr 2020 16:21:59 +0200 (CEST)", "by mail-lj1-f177.google.com with SMTP id i20so25942555ljn.6\n for <dev@dpdk.org>; Wed, 01 Apr 2020 07:21:59 -0700 (PDT)", "from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl.\n [193.106.246.138])\n by smtp.gmail.com with ESMTPSA id r21sm1435961ljp.29.2020.04.01.07.21.57\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 01 Apr 2020 07:21:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20150623.gappssmtp.com; s=20150623;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=hDGCzM1oIFg1NlFR5A9HCpLpVF6z8RS+UEWSJ0JRBNw=;\n b=lq5avyxo3HObBCPiD9QUlmKNVcN+lhcLntqGZkPY3zwiWn+3dzzd9bUObio7rYBLvm\n 9qMbGR6QVKr7MdXsIZNSREETbTT9ie0tb4VQlRBxeIQN0Qs/rRvSyxvc3GEbRuXRc3Sb\n U/BGoSnJJy61UuRAXr9WQ7QBwkxnzVQX8unuGGTCACYmUOpyx2NwfbTWyQft8W9ewKDp\n 8AR6UItJSWRxEuKc0ljdBm3BW5exk5IeBvCl/KIu2M5hK93xh6gbaQpuotuE8jYq1OaW\n AM4gja0B8UYmvnrLK7/vKaGgvCdPrWjw3esIDy/+k86ZVX9CfvHXbdcJDn15wW3bVLFW\n AP9g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=hDGCzM1oIFg1NlFR5A9HCpLpVF6z8RS+UEWSJ0JRBNw=;\n b=GU2h8z0/GvioeilLayxaGRuVwnU4mpXLs+oVMxAgj7UmdmUosmwcyxiAPK4y7Sfd6I\n AFw76pf4yMGl3nHdcHJsiYAI4Zz/lZmtMp8xUAviuF8mMx09sP6L63fFyI+2xsjwgGKY\n f2yA66IGdCsf8tMf/uLZWX/fUMC5DzBq9MsMXJeMUiQUjkQOIUfoRX3HfeSIA277y4mR\n fjIq5bCM6aK/3MGmLhv1CV2NtIgxPk37MqoxYgO5gOaf8nF8zJgOh0qXBoJ54kPIXFes\n Bll8NYEOBZJo1axP14lpV+5JhuHjhoDRErOa3IP8VkI+eYnztE1PNPn2YwbivytJvWfN\n akLQ==", "X-Gm-Message-State": "AGi0PuZAlWOcM/CZOb9LHnu4cQv7pWh+CSCci6kRVWudBNucVqp9ZTRD\n XzvlqqsbFY+IJMuGZmLDVlibcw3SQ4o=", "X-Google-Smtp-Source": "\n APiQypIw9B0VCPTkz0hTrg9puswikCGFqnS/iRNgufimT2Dm2WkkBoCR5QapkmDmhgW6xMrtlX1SqQ==", "X-Received": "by 2002:a2e:6809:: with SMTP id c9mr13013120lja.251.1585750919069;\n Wed, 01 Apr 2020 07:21:59 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com,\n igorch@amazon.com, Michal Krawczyk <mk@semihalf.com>", "Date": "Wed, 1 Apr 2020 16:21:14 +0200", "Message-Id": "<20200401142127.13715-17-mk@semihalf.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20200401142127.13715-1-mk@semihalf.com>", "References": "<20200401142127.13715-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 16/29] net/ena: refactor getting IO queues\n\tcapabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Reading values from the device is about the maximum capabilities of the\ndevice. Because of that, the names of the fields storing those values,\nfunctions and temporary variables, should be more descriptive in order\nto improve self documentation fo the code.\n\nIn connection with this, the way of getting maximum queue size could be\nsimplified - no hardcoded values are needed, as the device is going to\nsend it's capabilities anyway.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Guy Tzalik <gtzalik@amazon.com>\n---\n drivers/net/ena/ena_ethdev.c | 101 ++++++++++++++++-------------------\n drivers/net/ena/ena_ethdev.h | 11 ++--\n 2 files changed, 52 insertions(+), 60 deletions(-)", "diff": "diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex 13a016227c..d5f700093f 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -82,9 +82,6 @@ struct ena_stats {\n #define ENA_STAT_GLOBAL_ENTRY(stat) \\\n \tENA_STAT_ENTRY(stat, dev)\n \n-#define ENA_MAX_RING_SIZE_RX 8192\n-#define ENA_MAX_RING_SIZE_TX 1024\n-\n /*\n * Each rte_memzone should have unique name.\n * To satisfy it, count number of allocation and add it to name.\n@@ -845,29 +842,26 @@ static int ena_check_valid_conf(struct ena_adapter *adapter)\n }\n \n static int\n-ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)\n+ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx)\n {\n \tstruct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;\n \tstruct ena_com_dev *ena_dev = ctx->ena_dev;\n-\tuint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;\n-\tuint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;\n+\tuint32_t max_tx_queue_size;\n+\tuint32_t max_rx_queue_size;\n \n \tif (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {\n \t\tstruct ena_admin_queue_ext_feature_fields *max_queue_ext =\n \t\t\t&ctx->get_feat_ctx->max_queue_ext.max_queue_ext;\n-\t\trx_queue_size = RTE_MIN(rx_queue_size,\n-\t\t\tmax_queue_ext->max_rx_cq_depth);\n-\t\trx_queue_size = RTE_MIN(rx_queue_size,\n+\t\tmax_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,\n \t\t\tmax_queue_ext->max_rx_sq_depth);\n-\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n-\t\t\tmax_queue_ext->max_tx_cq_depth);\n+\t\tmax_tx_queue_size = max_queue_ext->max_tx_cq_depth;\n \n \t\tif (ena_dev->tx_mem_queue_type ==\n \t\t ENA_ADMIN_PLACEMENT_POLICY_DEV) {\n-\t\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n+\t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tllq->max_llq_depth);\n \t\t} else {\n-\t\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n+\t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tmax_queue_ext->max_tx_sq_depth);\n \t\t}\n \n@@ -878,39 +872,36 @@ ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)\n \t} else {\n \t\tstruct ena_admin_queue_feature_desc *max_queues =\n \t\t\t&ctx->get_feat_ctx->max_queues;\n-\t\trx_queue_size = RTE_MIN(rx_queue_size,\n-\t\t\tmax_queues->max_cq_depth);\n-\t\trx_queue_size = RTE_MIN(rx_queue_size,\n+\t\tmax_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,\n \t\t\tmax_queues->max_sq_depth);\n-\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n-\t\t\tmax_queues->max_cq_depth);\n+\t\tmax_tx_queue_size = max_queues->max_cq_depth;\n \n \t\tif (ena_dev->tx_mem_queue_type ==\n \t\t ENA_ADMIN_PLACEMENT_POLICY_DEV) {\n-\t\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n+\t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tllq->max_llq_depth);\n \t\t} else {\n-\t\t\ttx_queue_size = RTE_MIN(tx_queue_size,\n+\t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tmax_queues->max_sq_depth);\n \t\t}\n \n \t\tctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,\n-\t\t\tmax_queues->max_packet_tx_descs);\n-\t\tctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,\n \t\t\tmax_queues->max_packet_rx_descs);\n+\t\tctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,\n+\t\t\tmax_queues->max_packet_tx_descs);\n \t}\n \n \t/* Round down to the nearest power of 2 */\n-\trx_queue_size = rte_align32prevpow2(rx_queue_size);\n-\ttx_queue_size = rte_align32prevpow2(tx_queue_size);\n+\tmax_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);\n+\tmax_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);\n \n-\tif (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {\n+\tif (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {\n \t\tPMD_INIT_LOG(ERR, \"Invalid queue size\");\n \t\treturn -EFAULT;\n \t}\n \n-\tctx->rx_queue_size = rx_queue_size;\n-\tctx->tx_queue_size = tx_queue_size;\n+\tctx->max_tx_queue_size = max_tx_queue_size;\n+\tctx->max_rx_queue_size = max_rx_queue_size;\n \n \treturn 0;\n }\n@@ -1230,15 +1221,15 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (nb_desc > adapter->tx_ring_size) {\n+\tif (nb_desc > adapter->max_tx_ring_size) {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t\"Unsupported size of TX queue (max size: %d)\\n\",\n-\t\t\tadapter->tx_ring_size);\n+\t\t\tadapter->max_tx_ring_size);\n \t\treturn -EINVAL;\n \t}\n \n \tif (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)\n-\t\tnb_desc = adapter->tx_ring_size;\n+\t\tnb_desc = adapter->max_tx_ring_size;\n \n \ttxq->port_id = dev->data->port_id;\n \ttxq->next_to_clean = 0;\n@@ -1310,7 +1301,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,\n \t}\n \n \tif (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)\n-\t\tnb_desc = adapter->rx_ring_size;\n+\t\tnb_desc = adapter->max_rx_ring_size;\n \n \tif (!rte_is_power_of_2(nb_desc)) {\n \t\tPMD_DRV_LOG(ERR,\n@@ -1319,10 +1310,10 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (nb_desc > adapter->rx_ring_size) {\n+\tif (nb_desc > adapter->max_rx_ring_size) {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t\"Unsupported size of RX queue (max size: %d)\\n\",\n-\t\t\tadapter->rx_ring_size);\n+\t\t\tadapter->max_rx_ring_size);\n \t\treturn -EINVAL;\n \t}\n \n@@ -1654,10 +1645,10 @@ ena_set_queues_placement_policy(struct ena_adapter *adapter,\n \treturn 0;\n }\n \n-static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,\n-\t\t\t\t struct ena_com_dev_get_features_ctx *get_feat_ctx)\n+static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,\n+\tstruct ena_com_dev_get_features_ctx *get_feat_ctx)\n {\n-\tuint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;\n+\tuint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;\n \n \t/* Regular queues capabilities */\n \tif (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {\n@@ -1679,16 +1670,16 @@ static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,\n \tif (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)\n \t\tio_tx_sq_num = get_feat_ctx->llq.max_llq_num;\n \n-\tio_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);\n-\tio_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);\n-\tio_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);\n+\tmax_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);\n+\tmax_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);\n+\tmax_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);\n \n-\tif (unlikely(io_queue_num == 0)) {\n+\tif (unlikely(max_num_io_queues == 0)) {\n \t\tPMD_DRV_LOG(ERR, \"Number of IO queues should not be 0\\n\");\n \t\treturn -EFAULT;\n \t}\n \n-\treturn io_queue_num;\n+\treturn max_num_io_queues;\n }\n \n static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n@@ -1701,6 +1692,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \tstruct ena_com_dev_get_features_ctx get_feat_ctx;\n \tstruct ena_llq_configurations llq_config;\n \tconst char *queue_type_str;\n+\tuint32_t max_num_io_queues;\n \tint rc;\n \n \tstatic int adapters_found;\n@@ -1772,20 +1764,19 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \n \tcalc_queue_ctx.ena_dev = ena_dev;\n \tcalc_queue_ctx.get_feat_ctx = &get_feat_ctx;\n-\tadapter->num_queues = ena_calc_io_queue_num(ena_dev,\n-\t\t\t\t\t\t &get_feat_ctx);\n \n-\trc = ena_calc_queue_size(&calc_queue_ctx);\n-\tif (unlikely((rc != 0) || (adapter->num_queues <= 0))) {\n+\tmax_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);\n+\trc = ena_calc_io_queue_size(&calc_queue_ctx);\n+\tif (unlikely((rc != 0) || (max_num_io_queues == 0))) {\n \t\trc = -EFAULT;\n \t\tgoto err_device_destroy;\n \t}\n \n-\tadapter->tx_ring_size = calc_queue_ctx.tx_queue_size;\n-\tadapter->rx_ring_size = calc_queue_ctx.rx_queue_size;\n-\n+\tadapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;\n+\tadapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;\n \tadapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;\n \tadapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;\n+\tadapter->max_num_io_queues = max_num_io_queues;\n \n \t/* prepare ring structures */\n \tena_init_rings(adapter);\n@@ -1904,9 +1895,9 @@ static int ena_dev_configure(struct rte_eth_dev *dev)\n \n static void ena_init_rings(struct ena_adapter *adapter)\n {\n-\tint i;\n+\tsize_t i;\n \n-\tfor (i = 0; i < adapter->num_queues; i++) {\n+\tfor (i = 0; i < adapter->max_num_io_queues; i++) {\n \t\tstruct ena_ring *ring = &adapter->tx_ring[i];\n \n \t\tring->configured = 0;\n@@ -1918,7 +1909,7 @@ static void ena_init_rings(struct ena_adapter *adapter)\n \t\tring->sgl_size = adapter->max_tx_sgl_size;\n \t}\n \n-\tfor (i = 0; i < adapter->num_queues; i++) {\n+\tfor (i = 0; i < adapter->max_num_io_queues; i++) {\n \t\tstruct ena_ring *ring = &adapter->rx_ring[i];\n \n \t\tring->configured = 0;\n@@ -1982,21 +1973,21 @@ static int ena_infos_get(struct rte_eth_dev *dev,\n \tdev_info->max_rx_pktlen = adapter->max_mtu;\n \tdev_info->max_mac_addrs = 1;\n \n-\tdev_info->max_rx_queues = adapter->num_queues;\n-\tdev_info->max_tx_queues = adapter->num_queues;\n+\tdev_info->max_rx_queues = adapter->max_num_io_queues;\n+\tdev_info->max_tx_queues = adapter->max_num_io_queues;\n \tdev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;\n \n \tadapter->tx_supported_offloads = tx_feat;\n \tadapter->rx_supported_offloads = rx_feat;\n \n-\tdev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;\n+\tdev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;\n \tdev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;\n \tdev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,\n \t\t\t\t\tadapter->max_rx_sgl_size);\n \tdev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,\n \t\t\t\t\tadapter->max_rx_sgl_size);\n \n-\tdev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;\n+\tdev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;\n \tdev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;\n \tdev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,\n \t\t\t\t\tadapter->max_tx_sgl_size);\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex c1457defeb..99d1fba64d 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -21,6 +21,7 @@\n #define ENA_NAME_MAX_LEN\t20\n #define ENA_PKT_MAX_BUFS\t17\n #define ENA_RX_BUF_MIN_SIZE\t1400\n+#define ENA_DEFAULT_RING_SIZE\t1024\n \n #define ENA_MIN_MTU\t\t128\n \n@@ -46,8 +47,8 @@ struct ena_tx_buffer {\n struct ena_calc_queue_size_ctx {\n \tstruct ena_com_dev_get_features_ctx *get_feat_ctx;\n \tstruct ena_com_dev *ena_dev;\n-\tu16 rx_queue_size;\n-\tu16 tx_queue_size;\n+\tu32 max_rx_queue_size;\n+\tu32 max_tx_queue_size;\n \tu16 max_tx_sgl_size;\n \tu16 max_rx_sgl_size;\n };\n@@ -159,15 +160,15 @@ struct ena_adapter {\n \n \t/* TX */\n \tstruct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;\n-\tint tx_ring_size;\n+\tu32 max_tx_ring_size;\n \tu16 max_tx_sgl_size;\n \n \t/* RX */\n \tstruct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;\n-\tint rx_ring_size;\n+\tu32 max_rx_ring_size;\n \tu16 max_rx_sgl_size;\n \n-\tu16 num_queues;\n+\tu32 max_num_io_queues;\n \tu16 max_mtu;\n \tstruct ena_offloads offloads;\n \n", "prefixes": [ "v2", "16/29" ] }