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GET /api/patches/67378/?format=api
{ "id": 67378, "url": "https://patches.dpdk.org/api/patches/67378/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-13-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1585526580-113508-13-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1585526580-113508-13-git-send-email-nicolas.chautru@intel.com", "date": "2020-03-30T00:02:59", "name": "[v2,12/13] baseband/fpga_5gnr_fec: add interrupt support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "23545bfb17452a21780f514993b0db8c203ed1ca", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-13-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9086, "url": "https://patches.dpdk.org/api/series/9086/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9086", "date": "2020-03-30T00:02:47", "name": "drivers/baseband: add PMD for FPGA 5GNR FEC", "version": 2, "mbox": "https://patches.dpdk.org/series/9086/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67378/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/67378/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 87E28A0562;\n\tMon, 30 Mar 2020 02:05:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 76A221C0C6;\n\tMon, 30 Mar 2020 02:04:11 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 7684B2BBE\n for <dev@dpdk.org>; Mon, 30 Mar 2020 02:03:54 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Mar 2020 17:03:52 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:52 -0700" ], "IronPort-SDR": [ "\n rIihX5OEY5QGpPCzxswWnFpRkXKUD8MxGKCCEkXk67oSjQjGvYwh5XmUB7lN7KIvumzKC9qiJp\n xX7ugG7FhRgg==", "\n 3lyvdh25B5buGY29mdlFZbumJWPhZx0wHR/QF/XSHCZfvp5ezz5mOLsho/+00dBbiQQowPPtQJ\n tTCvxyUD537w==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,322,1580803200\"; d=\"scan'208\";a=\"248455366\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Sun, 29 Mar 2020 17:02:59 -0700", "Message-Id": "<1585526580-113508-13-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 12/13] baseband/fpga_5gnr_fec: add interrupt\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding support for interrupt capability in the PMD\nand the related operations.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 156 +++++++++++++++++++++\n 1 file changed, 156 insertions(+)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex b8cad1a..45a3126 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -110,6 +110,23 @@\n \treturn rte_le_to_cpu_32(ret);\n }\n \n+/* Read a register of FPGA 5GNR FEC device */\n+static uint8_t\n+fpga_reg_read_8(void *mmio_base, uint32_t offset)\n+{\n+\tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n+\treturn *((volatile uint8_t *)(reg_addr));\n+}\n+\n+/* Read a register of FPGA 5GNR FEC device */\n+static uint64_t\n+fpga_reg_read_64(void *mmio_base, uint32_t offset)\n+{\n+\tvoid *reg_addr = RTE_PTR_ADD(mmio_base, offset);\n+\tuint64_t ret = *((volatile uint64_t *)(reg_addr));\n+\treturn rte_le_to_cpu_64(ret);\n+}\n+\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \n /* Read a register of FPGA 5GNR FEC device */\n@@ -418,6 +435,7 @@\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK |\n+\t\t\t\tRTE_BBDEV_LDPC_DEC_INTERRUPTS |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,\n \t\t\t.llr_size = 6,\n \t\t\t.llr_decimals = 2,\n@@ -729,14 +747,152 @@\n \treturn 0;\n }\n \n+static inline uint16_t\n+get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)\n+{\n+\tuint16_t queue_id;\n+\n+\tfor (queue_id = 0; queue_id < data->num_queues; ++queue_id) {\n+\t\tstruct fpga_queue *q = data->queues[queue_id].queue_private;\n+\t\tif (q != NULL && q->q_idx == q_idx)\n+\t\t\treturn queue_id;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+/* Interrupt handler triggered by FPGA dev for handling specific interrupt */\n+static void\n+fpga_dev_interrupt_handler(void *cb_arg)\n+{\n+\tstruct rte_bbdev *dev = cb_arg;\n+\tstruct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;\n+\tstruct fpga_queue *q;\n+\tuint64_t ring_head;\n+\tuint64_t q_idx;\n+\tuint16_t queue_id;\n+\tuint8_t i;\n+\n+\t/* Scan queue assigned to this device */\n+\tfor (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {\n+\t\tq_idx = 1ULL << i;\n+\t\tif (fpga_dev->q_bound_bit_map & q_idx) {\n+\t\t\tqueue_id = get_queue_id(dev->data, i);\n+\t\t\tif (queue_id == (uint16_t) -1)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Check if completion head was changed */\n+\t\t\tq = dev->data->queues[queue_id].queue_private;\n+\t\t\tring_head = *q->ring_head_addr;\n+\t\t\tif (q->shadow_completion_head != ring_head &&\n+\t\t\t\tq->irq_enable == 1) {\n+\t\t\t\tq->shadow_completion_head = ring_head;\n+\t\t\t\trte_bbdev_pmd_callback_process(\n+\t\t\t\t\t\tdev,\n+\t\t\t\t\t\tRTE_BBDEV_EVENT_DEQUEUE,\n+\t\t\t\t\t\t&queue_id);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+static int\n+fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)\n+{\n+\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\n+\tif (!rte_intr_cap_multiple(dev->intr_handle))\n+\t\treturn -ENOTSUP;\n+\n+\tq->irq_enable = 1;\n+\n+\treturn 0;\n+}\n+\n+static int\n+fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)\n+{\n+\tstruct fpga_queue *q = dev->data->queues[queue_id].queue_private;\n+\tq->irq_enable = 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+fpga_intr_enable(struct rte_bbdev *dev)\n+{\n+\tint ret;\n+\tuint8_t i;\n+\n+\tif (!rte_intr_cap_multiple(dev->intr_handle)) {\n+\t\trte_bbdev_log(ERR, \"Multiple intr vector is not supported by FPGA (%s)\",\n+\t\t\t\tdev->data->name);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Create event file descriptors for each of 64 queue. Event fds will be\n+\t * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where\n+\t * the IRQ number is a direct translation to the queue number.\n+\t *\n+\t * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()\n+\t * mapped the first IRQ to already created interrupt event file\n+\t * descriptor (intr_handle->fd).\n+\t */\n+\tif (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {\n+\t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\",\n+\t\t\t\tdev->data->num_queues);\n+\t\treturn -1;\n+\t}\n+\n+\t/* TODO Each event file descriptor is overwritten by interrupt event\n+\t * file descriptor. That descriptor is added to epoll observed list.\n+\t * It ensures that callback function assigned to that descriptor will\n+\t * invoked when any FPGA queue issues interrupt.\n+\t */\n+\tfor (i = 0; i < FPGA_NUM_INTR_VEC; ++i)\n+\t\tdev->intr_handle->efds[i] = dev->intr_handle->fd;\n+\n+\tif (!dev->intr_handle->intr_vec) {\n+\t\tdev->intr_handle->intr_vec = rte_zmalloc(\"intr_vec\",\n+\t\t\t\tdev->data->num_queues * sizeof(int), 0);\n+\t\tif (!dev->intr_handle->intr_vec) {\n+\t\t\trte_bbdev_log(ERR, \"Failed to allocate %u vectors\",\n+\t\t\t\t\tdev->data->num_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\tret = rte_intr_enable(dev->intr_handle);\n+\tif (ret < 0) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Couldn't enable interrupts for device: %s\",\n+\t\t\t\tdev->data->name);\n+\t\treturn ret;\n+\t}\n+\n+\tret = rte_intr_callback_register(dev->intr_handle,\n+\t\t\tfpga_dev_interrupt_handler, dev);\n+\tif (ret < 0) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Couldn't register interrupt callback for device: %s\",\n+\t\t\t\tdev->data->name);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static const struct rte_bbdev_ops fpga_ops = {\n \t.setup_queues = fpga_setup_queues,\n+\t.intr_enable = fpga_intr_enable,\n \t.close = fpga_dev_close,\n \t.info_get = fpga_dev_info_get,\n \t.queue_setup = fpga_queue_setup,\n \t.queue_stop = fpga_queue_stop,\n \t.queue_start = fpga_queue_start,\n \t.queue_release = fpga_queue_release,\n+\t.queue_intr_enable = fpga_queue_intr_enable,\n+\t.queue_intr_disable = fpga_queue_intr_disable\n };\n \n static inline void\n", "prefixes": [ "v2", "12/13" ] }