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GET /api/patches/67377/?format=api
{ "id": 67377, "url": "https://patches.dpdk.org/api/patches/67377/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-12-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1585526580-113508-12-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1585526580-113508-12-git-send-email-nicolas.chautru@intel.com", "date": "2020-03-30T00:02:58", "name": "[v2,11/13] baseband/fpga_5gnr_fec: add harq loopback capability", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2de88b1779c9588f75e4976f1161a8f9153a3bdd", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-12-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9086, "url": "https://patches.dpdk.org/api/series/9086/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9086", "date": "2020-03-30T00:02:47", "name": "drivers/baseband: add PMD for FPGA 5GNR FEC", "version": 2, "mbox": "https://patches.dpdk.org/series/9086/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67377/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/67377/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 35FC4A0562;\n\tMon, 30 Mar 2020 02:05:19 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3DB5C1C0C0;\n\tMon, 30 Mar 2020 02:04:10 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id 0EE234C93\n for <dev@dpdk.org>; Mon, 30 Mar 2020 02:03:53 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Mar 2020 17:03:52 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:51 -0700" ], "IronPort-SDR": [ "\n 6s4ukwrpoGe0QluOkkpIQ8ulHk2fPENrs9ahUbY6zhJFvWHcPVAl8/DH+mg9d6Vd7kISLaV4Pn\n 6TUpGz4GVmgQ==", "\n PvBNaK8fNeQdv6147XdmmKDR74xUX+2uotkAC39ccpoX7FCuxFg/tkU+Brd2YwG9mfgLm/bw3A\n xMpdslyHQb+g==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,322,1580803200\"; d=\"scan'208\";a=\"248455362\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Sun, 29 Mar 2020 17:02:58 -0700", "Message-Id": "<1585526580-113508-12-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 11/13] baseband/fpga_5gnr_fec: add harq\n\tloopback capability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding optional capability to support loopback preloading\nand check of the extern HARQ memory.\nThis function is required to run the HARQ bit exact test successfully.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 171 +++++++++++++++++++++\n 1 file changed, 171 insertions(+)", "diff": "diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nindex 2559da5..b8cad1a 100644\n--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -417,6 +417,7 @@\n \t\t\t\tRTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |\n+\t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK |\n \t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,\n \t\t\t.llr_size = 6,\n \t\t\t.llr_decimals = 2,\n@@ -1148,6 +1149,140 @@\n #endif\n \n static inline int\n+fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev,\n+\t\tstruct rte_mbuf *harq_input, uint16_t harq_in_length,\n+\t\tuint32_t harq_in_offset, uint32_t harq_out_offset)\n+{\n+\tuint32_t out_offset = harq_out_offset;\n+\tuint32_t in_offset = harq_in_offset;\n+\tuint32_t left_length = harq_in_length;\n+\tuint32_t reg_32, increment = 0;\n+\tuint64_t *input = NULL;\n+\tuint32_t last_transaction = left_length\n+\t\t\t% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\tuint64_t last_word;\n+\n+\tif (last_transaction > 0)\n+\t\tleft_length -= last_transaction;\n+\n+\t/*\n+\t * Get HARQ buffer size for each VF/PF: When 0x00, there is no\n+\t * available DDR space for the corresponding VF/PF.\n+\t */\n+\treg_32 = fpga_reg_read_32(fpga_dev->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n+\tif (reg_32 < harq_in_length) {\n+\t\tleft_length = reg_32;\n+\t\trte_bbdev_log(ERR, \"HARQ in length > HARQ buffer size\\n\");\n+\t}\n+\n+\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,\n+\t\t\tuint8_t *, in_offset);\n+\n+\twhile (left_length > 0) {\n+\t\tif (fpga_reg_read_8(fpga_dev->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {\n+\t\t\tfpga_reg_write_32(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,\n+\t\t\t\t\tout_offset);\n+\t\t\tfpga_reg_write_64(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS,\n+\t\t\t\t\tinput[increment]);\n+\t\t\tleft_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\t\tout_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\t\tincrement++;\n+\t\t\tfpga_reg_write_8(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n+\t\t}\n+\t}\n+\twhile (last_transaction > 0) {\n+\t\tif (fpga_reg_read_8(fpga_dev->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {\n+\t\t\tfpga_reg_write_32(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,\n+\t\t\t\t\tout_offset);\n+\t\t\tlast_word = input[increment];\n+\t\t\tlast_word &= (uint64_t)(1 << (last_transaction * 4))\n+\t\t\t\t\t- 1;\n+\t\t\tfpga_reg_write_64(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DATA_REGS,\n+\t\t\t\t\tlast_word);\n+\t\t\tfpga_reg_write_8(fpga_dev->mmio_base,\n+\t\t\t\t\tFPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);\n+\t\t\tlast_transaction = 0;\n+\t\t}\n+\t}\n+\treturn 1;\n+}\n+\n+static inline int\n+fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev,\n+\t\tstruct rte_mbuf *harq_output, uint16_t harq_in_length,\n+\t\tuint32_t harq_in_offset, uint32_t harq_out_offset)\n+{\n+\tuint32_t left_length, in_offset = harq_in_offset;\n+\tuint64_t reg;\n+\tuint32_t increment = 0;\n+\tuint64_t *input = NULL;\n+\tuint32_t last_transaction = harq_in_length\n+\t\t\t% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\n+\tif (last_transaction > 0)\n+\t\tharq_in_length += (8 - last_transaction);\n+\n+\treg = fpga_reg_read_32(fpga_dev->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);\n+\tif (reg < harq_in_length) {\n+\t\tharq_in_length = reg;\n+\t\trte_bbdev_log(ERR, \"HARQ in length > HARQ buffer size\\n\");\n+\t}\n+\n+\tif (!mbuf_append(harq_output, harq_output, harq_in_length)) {\n+\t\trte_bbdev_log(ERR, \"HARQ output buffer warning %d %d\\n\",\n+\t\t\t\tharq_output->buf_len -\n+\t\t\t\trte_pktmbuf_headroom(harq_output),\n+\t\t\t\tharq_in_length);\n+\t\tharq_in_length = harq_output->buf_len -\n+\t\t\t\trte_pktmbuf_headroom(harq_output);\n+\t\tif (!mbuf_append(harq_output, harq_output, harq_in_length)) {\n+\t\t\trte_bbdev_log(ERR, \"HARQ output buffer issue %d %d\\n\",\n+\t\t\t\t\tharq_output->buf_len, harq_in_length);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\tleft_length = harq_in_length;\n+\n+\tinput = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output,\n+\t\t\tuint8_t *, harq_out_offset);\n+\n+\twhile (left_length > 0) {\n+\t\tfpga_reg_write_32(fpga_dev->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset);\n+\t\tfpga_reg_write_8(fpga_dev->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);\n+\t\treg = fpga_reg_read_8(fpga_dev->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n+\t\twhile (reg != 1) {\n+\t\t\treg = fpga_reg_read_8(fpga_dev->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_RDY_REGS);\n+\t\t\tif (reg == FPGA_DDR_OVERFLOW) {\n+\t\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\t\"Read address is overflow!\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t\tinput[increment] = fpga_reg_read_64(fpga_dev->mmio_base,\n+\t\t\tFPGA_5GNR_FEC_DDR4_RD_DATA_REGS);\n+\t\tleft_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES;\n+\t\tin_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;\n+\t\tincrement++;\n+\t\tfpga_reg_write_8(fpga_dev->mmio_base,\n+\t\t\t\tFPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);\n+\t}\n+\treturn 1;\n+}\n+\n+static inline int\n enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,\n \t\tuint16_t desc_offset)\n {\n@@ -1275,6 +1410,42 @@\n \tring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);\n \tdesc = q->ring_addr + ring_offset;\n \n+\tif (check_bit(dec->op_flags,\n+\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {\n+\t\tstruct rte_mbuf *harq_in = dec->harq_combined_input.data;\n+\t\tstruct rte_mbuf *harq_out = dec->harq_combined_output.data;\n+\t\tharq_in_length = dec->harq_combined_input.length;\n+\t\tuint32_t harq_in_offset = dec->harq_combined_input.offset;\n+\t\tuint32_t harq_out_offset = dec->harq_combined_output.offset;\n+\n+\t\tif (check_bit(dec->op_flags,\n+\t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE\n+\t\t\t\t)) {\n+\t\t\tret = fpga_harq_write_loopback(q->d, harq_in,\n+\t\t\t\t\tharq_in_length, harq_in_offset,\n+\t\t\t\t\tharq_out_offset);\n+\t\t} else if (check_bit(dec->op_flags,\n+\t\t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE\n+\t\t\t\t)) {\n+\t\t\tret = fpga_harq_read_loopback(q->d, harq_out,\n+\t\t\t\tharq_in_length, harq_in_offset,\n+\t\t\t\tharq_out_offset);\n+\t\t\tdec->harq_combined_output.length = harq_in_length;\n+\t\t} else {\n+\t\t\trte_bbdev_log(ERR, \"OP flag Err!\");\n+\t\t\tret = -1;\n+\t\t}\n+\t\t/* Set descriptor for dequeue */\n+\t\tdesc->dec_req.done = 1;\n+\t\tdesc->dec_req.error = 0;\n+\t\tdesc->dec_req.op_addr = op;\n+\t\tdesc->dec_req.cbs_in_op = 1;\n+\t\t/* Mark this dummy descriptor to be dropped by HW */\n+\t\tdesc->dec_req.desc_idx = (ring_offset + 1)\n+\t\t\t\t& q->sw_ring_wrap_mask;\n+\t\treturn ret; /* Error or number of CB */\n+\t}\n+\n \tif (m_in == NULL || m_out == NULL) {\n \t\trte_bbdev_log(ERR, \"Invalid mbuf pointer\");\n \t\top->status = 1 << RTE_BBDEV_DATA_ERROR;\n", "prefixes": [ "v2", "11/13" ] }