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GET /api/patches/66986/?format=api
{ "id": 66986, "url": "https://patches.dpdk.org/api/patches/66986/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1584936978-11899-1-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1584936978-11899-1-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1584936978-11899-1-git-send-email-phil.yang@arm.com", "date": "2020-03-23T04:16:17", "name": "[1/2] test/mcslock: move performance test to perf tests", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0d9cc64c5b1e2c6b68c37c20215c90e3a3ff3f19", "submitter": { "id": 833, "url": "https://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 24651, "url": "https://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1584936978-11899-1-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 9003, "url": "https://patches.dpdk.org/api/series/9003/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9003", "date": "2020-03-23T04:16:17", "name": "[1/2] test/mcslock: move performance test to perf tests", "version": 1, "mbox": "https://patches.dpdk.org/series/9003/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/66986/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/66986/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A108AA0563;\n\tMon, 23 Mar 2020 05:16:34 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F3BD11BF71;\n\tMon, 23 Mar 2020 05:16:33 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 806931BF6D\n for <dev@dpdk.org>; Mon, 23 Mar 2020 05:16:32 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4B351FB;\n Sun, 22 Mar 2020 21:16:31 -0700 (PDT)", "from phil-VirtualBox.arm.com (unknown [10.170.243.36])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 26BCF3F52E;\n Sun, 22 Mar 2020 21:16:28 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "aconole@redhat.com,\n\tmaicolgabriel@hotmail.com,\n\tdev@dpdk.org", "Cc": "david.marchand@redhat.com, drc@linux.vnet.ibm.com, gavin.hu@arm.com,\n Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, nd@arm.com", "Date": "Mon, 23 Mar 2020 12:16:17 +0800", "Message-Id": "<1584936978-11899-1-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "Subject": "[dpdk-dev] [PATCH 1/2] test/mcslock: move performance test to perf\n\ttests", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The MCS lock performance test takes more than 10 seconds and leads\nto meson test timeout on some platforms. Move the performance test\ninto perf tests.\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\n---\n MAINTAINERS | 1 +\n app/test/Makefile | 1 +\n app/test/autotest_data.py | 6 +++\n app/test/meson.build | 2 +\n app/test/test_mcslock.c | 88 -------------------------------\n app/test/test_mcslock_perf.c | 121 +++++++++++++++++++++++++++++++++++++++++++\n 6 files changed, 131 insertions(+), 88 deletions(-)\n create mode 100644 app/test/test_mcslock_perf.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex db235c2..411bdeb 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -247,6 +247,7 @@ MCSlock - EXPERIMENTAL\n M: Phil Yang <phil.yang@arm.com>\n F: lib/librte_eal/common/include/generic/rte_mcslock.h\n F: app/test/test_mcslock.c\n+F: app/test/test_mcslock_perf.c\n \n Ticketlock\n M: Joyce Kong <joyce.kong@arm.com>\ndiff --git a/app/test/Makefile b/app/test/Makefile\nindex 1f080d1..97de3ac 100644\n--- a/app/test/Makefile\n+++ b/app/test/Makefile\n@@ -65,6 +65,7 @@ SRCS-y += test_barrier.c\n SRCS-y += test_malloc.c\n SRCS-y += test_cycles.c\n SRCS-y += test_mcslock.c\n+SRCS-y += test_mcslock_perf.c\n SRCS-y += test_spinlock.c\n SRCS-y += test_ticketlock.c\n SRCS-y += test_memory.c\ndiff --git a/app/test/autotest_data.py b/app/test/autotest_data.py\nindex 7b1d013..2a4619d 100644\n--- a/app/test/autotest_data.py\n+++ b/app/test/autotest_data.py\n@@ -784,6 +784,12 @@\n \"Func\": default_autotest,\n \"Report\": None,\n },\n+ {\n+ \"Name\": \"MCS Lock performance autotest\",\n+ \"Command\": \"mcslock_perf_autotest\",\n+ \"Func\": default_autotest,\n+ \"Report\": None,\n+ },\n #\n # Please always make sure that ring_perf is the last test!\n #\ndiff --git a/app/test/meson.build b/app/test/meson.build\nindex 0a2ce71..335a869 100644\n--- a/app/test/meson.build\n+++ b/app/test/meson.build\n@@ -82,6 +82,7 @@ test_sources = files('commands.c',\n \t'test_meter.c',\n \t'test_metrics.c',\n \t'test_mcslock.c',\n+\t'test_mcslock_perf.c',\n \t'test_mp_secondary.c',\n \t'test_per_lcore.c',\n \t'test_pmd_perf.c',\n@@ -270,6 +271,7 @@ perf_test_names = [\n 'rand_perf_autotest',\n 'hash_readwrite_perf_autotest',\n 'hash_readwrite_lf_perf_autotest',\n+\t'mcslock_perf_autotest',\n ]\n \n driver_test_names = [\ndiff --git a/app/test/test_mcslock.c b/app/test/test_mcslock.c\nindex e9359df..15f9751 100644\n--- a/app/test/test_mcslock.c\n+++ b/app/test/test_mcslock.c\n@@ -32,23 +32,16 @@\n *\n * - The function takes the global lock, display something, then releases\n * the global lock on each core.\n- *\n- * - A load test is carried out, with all cores attempting to lock a single\n- * lock multiple times.\n */\n \n RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_me);\n RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_try_me);\n-RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_perf_me);\n \n rte_mcslock_t *p_ml;\n rte_mcslock_t *p_ml_try;\n-rte_mcslock_t *p_ml_perf;\n \n static unsigned int count;\n \n-static rte_atomic32_t synchro;\n-\n static int\n test_mcslock_per_core(__attribute__((unused)) void *arg)\n {\n@@ -63,85 +56,8 @@ test_mcslock_per_core(__attribute__((unused)) void *arg)\n \treturn 0;\n }\n \n-static uint64_t time_count[RTE_MAX_LCORE] = {0};\n-\n #define MAX_LOOP 1000000\n \n-static int\n-load_loop_fn(void *func_param)\n-{\n-\tuint64_t time_diff = 0, begin;\n-\tuint64_t hz = rte_get_timer_hz();\n-\tvolatile uint64_t lcount = 0;\n-\tconst int use_lock = *(int *)func_param;\n-\tconst unsigned int lcore = rte_lcore_id();\n-\n-\t/**< Per core me node. */\n-\trte_mcslock_t ml_perf_me = RTE_PER_LCORE(_ml_perf_me);\n-\n-\t/* wait synchro */\n-\twhile (rte_atomic32_read(&synchro) == 0)\n-\t\t;\n-\n-\tbegin = rte_get_timer_cycles();\n-\twhile (lcount < MAX_LOOP) {\n-\t\tif (use_lock)\n-\t\t\trte_mcslock_lock(&p_ml_perf, &ml_perf_me);\n-\n-\t\tlcount++;\n-\t\tif (use_lock)\n-\t\t\trte_mcslock_unlock(&p_ml_perf, &ml_perf_me);\n-\t}\n-\ttime_diff = rte_get_timer_cycles() - begin;\n-\ttime_count[lcore] = time_diff * 1000000 / hz;\n-\treturn 0;\n-}\n-\n-static int\n-test_mcslock_perf(void)\n-{\n-\tunsigned int i;\n-\tuint64_t total = 0;\n-\tint lock = 0;\n-\tconst unsigned int lcore = rte_lcore_id();\n-\n-\tprintf(\"\\nTest with no lock on single core...\\n\");\n-\trte_atomic32_set(&synchro, 1);\n-\tload_loop_fn(&lock);\n-\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n-\t\t\tlcore, time_count[lcore]);\n-\tmemset(time_count, 0, sizeof(time_count));\n-\n-\tprintf(\"\\nTest with lock on single core...\\n\");\n-\tlock = 1;\n-\trte_atomic32_set(&synchro, 1);\n-\tload_loop_fn(&lock);\n-\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n-\t\t\tlcore, time_count[lcore]);\n-\tmemset(time_count, 0, sizeof(time_count));\n-\n-\tprintf(\"\\nTest with lock on %u cores...\\n\", (rte_lcore_count()));\n-\n-\trte_atomic32_set(&synchro, 0);\n-\trte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER);\n-\n-\t/* start synchro and launch test on master */\n-\trte_atomic32_set(&synchro, 1);\n-\tload_loop_fn(&lock);\n-\n-\trte_eal_mp_wait_lcore();\n-\n-\tRTE_LCORE_FOREACH(i) {\n-\t\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n-\t\t\t\ti, time_count[i]);\n-\t\ttotal += time_count[i];\n-\t}\n-\n-\tprintf(\"Total Cost Time = %\"PRIu64\" us\\n\", total);\n-\n-\treturn 0;\n-}\n-\n /*\n * Use rte_mcslock_trylock() to trylock a mcs lock object,\n * If it could not lock the object successfully, it would\n@@ -240,10 +156,6 @@ test_mcslock(void)\n \t\tret = -1;\n \trte_mcslock_unlock(&p_ml, &ml_me);\n \n-\t/* mcs lock perf test */\n-\tif (test_mcslock_perf() < 0)\n-\t\treturn -1;\n-\n \treturn ret;\n }\n \ndiff --git a/app/test/test_mcslock_perf.c b/app/test/test_mcslock_perf.c\nnew file mode 100644\nindex 0000000..6948344\n--- /dev/null\n+++ b/app/test/test_mcslock_perf.c\n@@ -0,0 +1,121 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Arm Limited\n+ */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <inttypes.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <sys/queue.h>\n+\n+#include <rte_common.h>\n+#include <rte_memory.h>\n+#include <rte_per_lcore.h>\n+#include <rte_launch.h>\n+#include <rte_eal.h>\n+#include <rte_lcore.h>\n+#include <rte_cycles.h>\n+#include <rte_mcslock.h>\n+#include <rte_atomic.h>\n+\n+#include \"test.h\"\n+\n+/*\n+ * RTE MCS lock perf test\n+ * ======================\n+ *\n+ * These tests are derived from spin lock perf test cases.\n+ *\n+ * - A load test is carried out, with all cores attempting to lock a single\n+ * lock multiple times.\n+ */\n+\n+RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_perf_me);\n+rte_mcslock_t *p_ml_perf;\n+\n+static rte_atomic32_t synchro;\n+static uint64_t time_count[RTE_MAX_LCORE] = {0};\n+\n+#define MAX_LOOP 1000000\n+\n+static int\n+load_loop_fn(void *func_param)\n+{\n+\tuint64_t time_diff = 0, begin;\n+\tuint64_t hz = rte_get_timer_hz();\n+\tvolatile uint64_t lcount = 0;\n+\tconst int use_lock = *(int *)func_param;\n+\tconst unsigned int lcore = rte_lcore_id();\n+\n+\t/**< Per core me node. */\n+\trte_mcslock_t ml_perf_me = RTE_PER_LCORE(_ml_perf_me);\n+\n+\t/* wait synchro */\n+\twhile (rte_atomic32_read(&synchro) == 0)\n+\t\t;\n+\n+\tbegin = rte_get_timer_cycles();\n+\twhile (lcount < MAX_LOOP) {\n+\t\tif (use_lock)\n+\t\t\trte_mcslock_lock(&p_ml_perf, &ml_perf_me);\n+\n+\t\tlcount++;\n+\t\tif (use_lock)\n+\t\t\trte_mcslock_unlock(&p_ml_perf, &ml_perf_me);\n+\t}\n+\ttime_diff = rte_get_timer_cycles() - begin;\n+\ttime_count[lcore] = time_diff * 1000000 / hz;\n+\treturn 0;\n+}\n+\n+/*\n+ * Test rte_eal_get_lcore_state() in addition to mcs locks\n+ * as we have \"waiting\" then \"running\" lcores.\n+ */\n+static int\n+test_mcslock_perf(void)\n+{\n+\tunsigned int i;\n+\tuint64_t total = 0;\n+\tint lock = 0;\n+\tconst unsigned int lcore = rte_lcore_id();\n+\n+\tprintf(\"\\nTest with no lock on single core...\\n\");\n+\trte_atomic32_set(&synchro, 1);\n+\tload_loop_fn(&lock);\n+\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n+\t\t\tlcore, time_count[lcore]);\n+\tmemset(time_count, 0, sizeof(time_count));\n+\n+\tprintf(\"\\nTest with lock on single core...\\n\");\n+\tlock = 1;\n+\trte_atomic32_set(&synchro, 1);\n+\tload_loop_fn(&lock);\n+\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n+\t\t\tlcore, time_count[lcore]);\n+\tmemset(time_count, 0, sizeof(time_count));\n+\n+\tprintf(\"\\nTest with lock on %u cores...\\n\", (rte_lcore_count()));\n+\n+\trte_atomic32_set(&synchro, 0);\n+\trte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER);\n+\n+\t/* start synchro and launch test on master */\n+\trte_atomic32_set(&synchro, 1);\n+\tload_loop_fn(&lock);\n+\n+\trte_eal_mp_wait_lcore();\n+\n+\tRTE_LCORE_FOREACH(i) {\n+\t\tprintf(\"Core [%u] Cost Time = %\"PRIu64\" us\\n\",\n+\t\t\t\ti, time_count[i]);\n+\t\ttotal += time_count[i];\n+\t}\n+\n+\tprintf(\"Total Cost Time = %\"PRIu64\" us\\n\", total);\n+\n+\treturn 0;\n+}\n+\n+REGISTER_TEST_COMMAND(mcslock_perf_autotest, test_mcslock_perf);\n", "prefixes": [ "1/2" ] }