Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 66985,
    "url": "https://patches.dpdk.org/api/patches/66985/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1584672375-376187-3-git-send-email-alvinx.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1584672375-376187-3-git-send-email-alvinx.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1584672375-376187-3-git-send-email-alvinx.zhang@intel.com",
    "date": "2020-03-20T02:46:03",
    "name": "[v2,02/14] net/igc: support device initialization",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "c910c5402bfa73a30d4e9f2c71b9e7eaf5a1fc35",
    "submitter": {
        "id": 1398,
        "url": "https://patches.dpdk.org/api/people/1398/?format=api",
        "name": "Alvin Zhang",
        "email": "alvinx.zhang@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1584672375-376187-3-git-send-email-alvinx.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 8992,
            "url": "https://patches.dpdk.org/api/series/8992/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=8992",
            "date": "2020-03-20T02:46:01",
            "name": "igc PMD",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/8992/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/66985/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/66985/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 313CAA0563;\n\tSun, 22 Mar 2020 18:06:52 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E4AF11C027;\n\tSun, 22 Mar 2020 18:06:41 +0100 (CET)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id F343329D6\n for <dev@dpdk.org>; Fri, 20 Mar 2020 03:50:54 +0100 (CET)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Mar 2020 19:50:53 -0700",
            "from unknown (HELO dpdk-zhangalvin-dev.sh.intel.com)\n ([10.240.183.54])\n by fmsmga002.fm.intel.com with ESMTP; 19 Mar 2020 19:50:47 -0700"
        ],
        "IronPort-SDR": [
            "\n FRsZlPMk7TYdd9xDQ3CN7itSH5lP7k/KhyxpB/s3FetV8d2KBC/YhcMGpPZH9Y94FDpNTycTBb\n KilRdiINPDMg==",
            "\n cx1Wf8vTC42vrJIrHnCfbI7ib9/7H0YX6Vf2zkvqzPL1jBZlxXkHdJa8LBdd7JCabNs2jOsS6O\n imNeuUt4KBkA=="
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.72,283,1580803200\"; d=\"scan'208\";a=\"280290103\"",
        "From": "alvinx.zhang@intel.com",
        "To": "dev@dpdk.org, xiaolong.ye@intel.com, haiyue.wang@intel.com,\n qi.z.zhang@intel.com, beilei.xing@intel.com",
        "Date": "Fri, 20 Mar 2020 10:46:03 +0800",
        "Message-Id": "<1584672375-376187-3-git-send-email-alvinx.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1584672375-376187-1-git-send-email-alvinx.zhang@intel.com>",
        "References": "<1583742247-370386-1-git-send-email-alvinx.zhang@intel.com>\n <1584672375-376187-1-git-send-email-alvinx.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\\",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Approved-At": "Sun, 22 Mar 2020 18:06:38 +0100",
        "Subject": "[dpdk-dev] [PATCH v2 02/14] net/igc: support device initialization",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Alvin Zhang <alvinx.zhang@intel.com>\n\nUpdate base share codes, add readme.\nAdd OS specific functions and definitions.\nAdd device initialization codes.\n\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\n\nv2:\n- Modify codes according to comments.\n- Fix share codes style issues.\n- Merge patch[03] \"add device initialization\" into patch[02] \"update\n  base share codes\", which is more reasonable.\n- Update the release notes.\n---\n drivers/net/igc/Makefile             |   45 +\n drivers/net/igc/base/README          |   29 +\n drivers/net/igc/base/e1000_82571.h   |   36 +\n drivers/net/igc/base/e1000_82575.h   |  351 +++\n drivers/net/igc/base/e1000_api.c     | 1845 ++++++++++++++\n drivers/net/igc/base/e1000_api.h     |  111 +\n drivers/net/igc/base/e1000_base.c    |  190 ++\n drivers/net/igc/base/e1000_base.h    |  127 +\n drivers/net/igc/base/e1000_defines.h | 1649 +++++++++++++\n drivers/net/igc/base/e1000_hw.h      | 1051 ++++++++\n drivers/net/igc/base/e1000_i225.c    | 1378 +++++++++++\n drivers/net/igc/base/e1000_i225.h    |  110 +\n drivers/net/igc/base/e1000_ich8lan.h |  296 +++\n drivers/net/igc/base/e1000_mac.c     | 2100 ++++++++++++++++\n drivers/net/igc/base/e1000_mac.h     |   64 +\n drivers/net/igc/base/e1000_manage.c  |  547 +++++\n drivers/net/igc/base/e1000_manage.h  |   65 +\n drivers/net/igc/base/e1000_nvm.c     | 1324 ++++++++++\n drivers/net/igc/base/e1000_nvm.h     |   69 +\n drivers/net/igc/base/e1000_osdep.c   |   64 +\n drivers/net/igc/base/e1000_osdep.h   |  163 ++\n drivers/net/igc/base/e1000_phy.c     | 4422 ++++++++++++++++++++++++++++++++++\n drivers/net/igc/base/e1000_phy.h     |  337 +++\n drivers/net/igc/base/e1000_regs.h    |  724 ++++++\n drivers/net/igc/base/meson.build     |   28 +\n drivers/net/igc/igc_ethdev.c         |  264 +-\n drivers/net/igc/igc_ethdev.h         |   19 +\n drivers/net/igc/meson.build          |    5 +\n 28 files changed, 17403 insertions(+), 10 deletions(-)\n create mode 100644 drivers/net/igc/base/README\n create mode 100644 drivers/net/igc/base/e1000_82571.h\n create mode 100644 drivers/net/igc/base/e1000_82575.h\n create mode 100644 drivers/net/igc/base/e1000_api.c\n create mode 100644 drivers/net/igc/base/e1000_api.h\n create mode 100644 drivers/net/igc/base/e1000_base.c\n create mode 100644 drivers/net/igc/base/e1000_base.h\n create mode 100644 drivers/net/igc/base/e1000_defines.h\n create mode 100644 drivers/net/igc/base/e1000_hw.h\n create mode 100644 drivers/net/igc/base/e1000_i225.c\n create mode 100644 drivers/net/igc/base/e1000_i225.h\n create mode 100644 drivers/net/igc/base/e1000_ich8lan.h\n create mode 100644 drivers/net/igc/base/e1000_mac.c\n create mode 100644 drivers/net/igc/base/e1000_mac.h\n create mode 100644 drivers/net/igc/base/e1000_manage.c\n create mode 100644 drivers/net/igc/base/e1000_manage.h\n create mode 100644 drivers/net/igc/base/e1000_nvm.c\n create mode 100644 drivers/net/igc/base/e1000_nvm.h\n create mode 100644 drivers/net/igc/base/e1000_osdep.c\n create mode 100644 drivers/net/igc/base/e1000_osdep.h\n create mode 100644 drivers/net/igc/base/e1000_phy.c\n create mode 100644 drivers/net/igc/base/e1000_phy.h\n create mode 100644 drivers/net/igc/base/e1000_regs.h\n create mode 100644 drivers/net/igc/base/meson.build",
    "diff": "diff --git a/drivers/net/igc/Makefile b/drivers/net/igc/Makefile\nindex 7b51daf..815ea62 100644\n--- a/drivers/net/igc/Makefile\n+++ b/drivers/net/igc/Makefile\n@@ -13,12 +13,57 @@ CFLAGS += $(WERROR_FLAGS)\n LDLIBS += -lrte_eal\n LDLIBS += -lrte_ethdev\n LDLIBS += -lrte_bus_pci\n+LDLIBS += -lrte_mbuf\n+LDLIBS += -lrte_mempool\n \n EXPORT_MAP := rte_pmd_igc_version.map\n \n #\n+# Add extra flags for base driver files (also known as shared code)\n+# to disable warnings\n+#\n+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)\n+#\n+# CFLAGS for icc\n+#\n+CFLAGS_BASE_DRIVER  = -diag-disable 177 -diag-disable 181\n+CFLAGS_BASE_DRIVER += -diag-disable 869 -diag-disable 2259\n+else\n+#\n+# CFLAGS for gcc/clang\n+#\n+CFLAGS_BASE_DRIVER = -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-unused-variable\n+ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\n+ifeq ($(shell test $(GCC_VERSION) -ge 60 && echo 1), 1)\n+CFLAGS_BASE_DRIVER += -Wno-misleading-indentation\n+ifeq ($(shell test $(GCC_VERSION) -ge 70 && echo 1), 1)\n+CFLAGS_BASE_DRIVER += -Wno-implicit-fallthrough\n+endif\n+endif\n+endif\n+endif\n+\n+#\n+# Add extra flags for base driver files (also known as shared code)\n+# to disable warnings in them\n+#\n+BASE_DRIVER_OBJS=$(sort $(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c))))\n+$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n+\n+VPATH += $(SRCDIR)/base\n+\n+#\n # all source are stored in SRCS-y\n #\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_api.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_base.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_i225.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_mac.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_manage.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_nvm.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_osdep.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += e1000_phy.c\n SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_logs.c\n SRCS-$(CONFIG_RTE_LIBRTE_IGC_PMD) += igc_ethdev.c\n \ndiff --git a/drivers/net/igc/base/README b/drivers/net/igc/base/README\nnew file mode 100644\nindex 0000000..68db0c1\n--- /dev/null\n+++ b/drivers/net/igc/base/README\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+Intel® IGC driver\n+==================\n+\n+This directory contains source code of FreeBSD igc driver of version\n+2019.10.18 released by the team which develops basic drivers for any\n+i225 NIC.\n+The directory of base/ contains the original source package.\n+This driver is valid for the product(s) listed below\n+\n+* Intel® Ethernet Network Adapters I225\n+\n+Updating the driver\n+===================\n+\n+NOTE:\n+- To avoid namespace issues with e1000 PMD, all prefix e1000_ or E1000_\n+of the definition and macro names ware replaced with igc_ or IGC_.\n+- Since some codes are not required, they have been removed from the\n+base codes, such as the I350 and I210 series NICs related codes.\n+- Some registers are used by the base codes but not defined in the base\n+codes, so they ware added to them.\n+- OS and DPDK specified definitions and macros ware added in following\n+files:\n+  e1000_osdep.h\n+  e1000_osdep.c\ndiff --git a/drivers/net/igc/base/e1000_82571.h b/drivers/net/igc/base/e1000_82571.h\nnew file mode 100644\nindex 0000000..6d1f8ac\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_82571.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_82571_H_\n+#define _IGC_82571_H_\n+\n+#define ID_LED_RESERVED_F746\t0xF746\n+#define ID_LED_DEFAULT_82573\t((ID_LED_DEF1_DEF2 << 12) | \\\n+\t\t\t\t (ID_LED_OFF1_ON2  <<  8) | \\\n+\t\t\t\t (ID_LED_DEF1_DEF2 <<  4) | \\\n+\t\t\t\t (ID_LED_DEF1_DEF2))\n+\n+#define IGC_GCR_L1_ACT_WITHOUT_L0S_RX\t0x08000000\n+#define AN_RETRY_COUNT\t\t5 /* Autoneg Retry Count value */\n+\n+/* Intr Throttling - RW */\n+#define IGC_EITR_82574(_n)\t(0x000E8 + (0x4 * (_n)))\n+\n+#define IGC_EIAC_82574\t0x000DC /* Ext. Interrupt Auto Clear - RW */\n+#define IGC_EIAC_MASK_82574\t0x01F00000\n+\n+#define IGC_IVAR_INT_ALLOC_VALID\t0x8\n+\n+/* Manageability Operation Mode mask */\n+#define IGC_NVM_INIT_CTRL2_MNGM\t0x6000\n+\n+#define IGC_BASE1000T_STATUS\t\t10\n+#define IGC_IDLE_ERROR_COUNT_MASK\t0xFF\n+#define IGC_RECEIVE_ERROR_COUNTER\t21\n+#define IGC_RECEIVE_ERROR_MAX\t\t0xFFFF\n+bool igc_check_phy_82574(struct igc_hw *hw);\n+bool igc_get_laa_state_82571(struct igc_hw *hw);\n+void igc_set_laa_state_82571(struct igc_hw *hw, bool state);\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_82575.h b/drivers/net/igc/base/e1000_82575.h\nnew file mode 100644\nindex 0000000..9cd74cf\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_82575.h\n@@ -0,0 +1,351 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_82575_H_\n+#define _IGC_82575_H_\n+\n+#define ID_LED_DEFAULT_82575_SERDES\t((ID_LED_DEF1_DEF2 << 12) | \\\n+\t\t\t\t\t (ID_LED_DEF1_DEF2 <<  8) | \\\n+\t\t\t\t\t (ID_LED_DEF1_DEF2 <<  4) | \\\n+\t\t\t\t\t (ID_LED_OFF1_ON2))\n+/*\n+ * Receive Address Register Count\n+ * Number of high/low register pairs in the RAR.  The RAR (Receive Address\n+ * Registers) holds the directed and multicast addresses that we monitor.\n+ * These entries are also used for MAC-based filtering.\n+ */\n+/*\n+ * For 82576, there are an additional set of RARs that begin at an offset\n+ * separate from the first set of RARs.\n+ */\n+#define IGC_RAR_ENTRIES_82575\t16\n+#define IGC_RAR_ENTRIES_82576\t24\n+#define IGC_RAR_ENTRIES_82580\t24\n+#define IGC_RAR_ENTRIES_I350\t32\n+#define IGC_SW_SYNCH_MB\t0x00000100\n+#define IGC_STAT_DEV_RST_SET\t0x00100000\n+\n+struct igc_adv_data_desc {\n+\t__le64 buffer_addr;    /* Address of the descriptor's data buffer */\n+\tunion {\n+\t\tu32 data;\n+\t\tstruct {\n+\t\t\tu32 datalen:16; /* Data buffer length */\n+\t\t\tu32 rsvd:4;\n+\t\t\tu32 dtyp:4;  /* Descriptor type */\n+\t\t\tu32 dcmd:8;  /* Descriptor command */\n+\t\t} config;\n+\t} lower;\n+\tunion {\n+\t\tu32 data;\n+\t\tstruct {\n+\t\t\tu32 status:4;  /* Descriptor status */\n+\t\t\tu32 idx:4;\n+\t\t\tu32 popts:6;  /* Packet Options */\n+\t\t\tu32 paylen:18; /* Payload length */\n+\t\t} options;\n+\t} upper;\n+};\n+\n+#define IGC_TXD_DTYP_ADV_C\t0x2  /* Advanced Context Descriptor */\n+#define IGC_TXD_DTYP_ADV_D\t0x3  /* Advanced Data Descriptor */\n+#define IGC_ADV_TXD_CMD_DEXT\t0x20 /* Descriptor extension (0 = legacy) */\n+#define IGC_ADV_TUCMD_IPV4\t0x2  /* IP Packet Type: 1=IPv4 */\n+#define IGC_ADV_TUCMD_IPV6\t0x0  /* IP Packet Type: 0=IPv6 */\n+#define IGC_ADV_TUCMD_L4T_UDP\t0x0  /* L4 Packet TYPE of UDP */\n+#define IGC_ADV_TUCMD_L4T_TCP\t0x4  /* L4 Packet TYPE of TCP */\n+#define IGC_ADV_TUCMD_MKRREQ\t0x10 /* Indicates markers are required */\n+#define IGC_ADV_DCMD_EOP\t0x1  /* End of Packet */\n+#define IGC_ADV_DCMD_IFCS\t0x2  /* Insert FCS (Ethernet CRC) */\n+#define IGC_ADV_DCMD_RS\t0x8  /* Report Status */\n+#define IGC_ADV_DCMD_VLE\t0x40 /* Add VLAN tag */\n+#define IGC_ADV_DCMD_TSE\t0x80 /* TCP Seg enable */\n+/* Extended Device Control */\n+#define IGC_CTRL_EXT_NSICR\t0x00000001 /* Disable Intr Clear all on read */\n+\n+struct igc_adv_context_desc {\n+\tunion {\n+\t\tu32 ip_config;\n+\t\tstruct {\n+\t\t\tu32 iplen:9;\n+\t\t\tu32 maclen:7;\n+\t\t\tu32 vlan_tag:16;\n+\t\t} fields;\n+\t} ip_setup;\n+\tu32 seq_num;\n+\tunion {\n+\t\tu64 l4_config;\n+\t\tstruct {\n+\t\t\tu32 mkrloc:9;\n+\t\t\tu32 tucmd:11;\n+\t\t\tu32 dtyp:4;\n+\t\t\tu32 adv:8;\n+\t\t\tu32 rsvd:4;\n+\t\t\tu32 idx:4;\n+\t\t\tu32 l4len:8;\n+\t\t\tu32 mss:16;\n+\t\t} fields;\n+\t} l4_setup;\n+};\n+\n+/* SRRCTL bit definitions */\n+#define IGC_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n+#define IGC_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n+#define IGC_SRRCTL_DESCTYPE_MASK\t\t0x0E000000\n+#define IGC_SRRCTL_TIMESTAMP\t\t\t0x40000000\n+#define IGC_SRRCTL_DROP_EN\t\t\t0x80000000\n+\n+#define IGC_SRRCTL_BSIZEPKT_MASK\t\t0x0000007F\n+#define IGC_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n+\n+#define IGC_TX_HEAD_WB_ENABLE\t\t0x1\n+#define IGC_TX_SEQNUM_WB_ENABLE\t0x2\n+\n+#define IGC_MRQC_ENABLE_RSS_4Q\t\t0x00000002\n+#define IGC_MRQC_ENABLE_VMDQ\t\t\t0x00000003\n+#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q\t\t0x00000005\n+#define IGC_MRQC_RSS_FIELD_IPV4_UDP\t\t0x00400000\n+#define IGC_MRQC_RSS_FIELD_IPV6_UDP\t\t0x00800000\n+#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX\t0x01000000\n+#define IGC_MRQC_ENABLE_RSS_8Q\t\t0x00000002\n+\n+#define IGC_VMRCTL_MIRROR_PORT_SHIFT\t\t8\n+#define IGC_VMRCTL_MIRROR_DSTPORT_MASK\t(7 << \\\n+\t\t\t\t\t\t IGC_VMRCTL_MIRROR_PORT_SHIFT)\n+#define IGC_VMRCTL_POOL_MIRROR_ENABLE\t\t(1 << 0)\n+#define IGC_VMRCTL_UPLINK_MIRROR_ENABLE\t(1 << 1)\n+#define IGC_VMRCTL_DOWNLINK_MIRROR_ENABLE\t(1 << 2)\n+\n+#define IGC_EICR_TX_QUEUE ( \\\n+\tIGC_EICR_TX_QUEUE0 |    \\\n+\tIGC_EICR_TX_QUEUE1 |    \\\n+\tIGC_EICR_TX_QUEUE2 |    \\\n+\tIGC_EICR_TX_QUEUE3)\n+\n+#define IGC_EICR_RX_QUEUE ( \\\n+\tIGC_EICR_RX_QUEUE0 |    \\\n+\tIGC_EICR_RX_QUEUE1 |    \\\n+\tIGC_EICR_RX_QUEUE2 |    \\\n+\tIGC_EICR_RX_QUEUE3)\n+\n+#define IGC_EIMS_RX_QUEUE\tIGC_EICR_RX_QUEUE\n+#define IGC_EIMS_TX_QUEUE\tIGC_EICR_TX_QUEUE\n+\n+#define EIMS_ENABLE_MASK ( \\\n+\tIGC_EIMS_RX_QUEUE  | \\\n+\tIGC_EIMS_TX_QUEUE  | \\\n+\tIGC_EIMS_TCP_TIMER | \\\n+\tIGC_EIMS_OTHER)\n+\n+/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n+#define IGC_IMIR_PORT_IM_EN\t0x00010000  /* TCP port enable */\n+#define IGC_IMIR_PORT_BP\t0x00020000  /* TCP port check bypass */\n+#define IGC_IMIREXT_CTRL_URG\t0x00002000  /* Check URG bit in header */\n+#define IGC_IMIREXT_CTRL_ACK\t0x00004000  /* Check ACK bit in header */\n+#define IGC_IMIREXT_CTRL_PSH\t0x00008000  /* Check PSH bit in header */\n+#define IGC_IMIREXT_CTRL_RST\t0x00010000  /* Check RST bit in header */\n+#define IGC_IMIREXT_CTRL_SYN\t0x00020000  /* Check SYN bit in header */\n+#define IGC_IMIREXT_CTRL_FIN\t0x00040000  /* Check FIN bit in header */\n+\n+#define IGC_RXDADV_RSSTYPE_MASK\t0x0000000F\n+#define IGC_RXDADV_RSSTYPE_SHIFT\t12\n+#define IGC_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n+#define IGC_RXDADV_HDRBUFLEN_SHIFT\t5\n+#define IGC_RXDADV_SPLITHEADER_EN\t0x00001000\n+#define IGC_RXDADV_SPH\t\t0x8000\n+#define IGC_RXDADV_STAT_TS\t\t0x10000 /* Pkt was time stamped */\n+#define IGC_RXDADV_ERR_HBO\t\t0x00800000\n+\n+/* RSS Hash results */\n+#define IGC_RXDADV_RSSTYPE_NONE\t0x00000000\n+#define IGC_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n+#define IGC_RXDADV_RSSTYPE_IPV4\t0x00000002\n+#define IGC_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n+#define IGC_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n+#define IGC_RXDADV_RSSTYPE_IPV6\t0x00000005\n+#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n+#define IGC_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n+#define IGC_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n+#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n+\n+/* RSS Packet Types as indicated in the receive descriptor */\n+#define IGC_RXDADV_PKTTYPE_ILMASK\t0x000000F0\n+#define IGC_RXDADV_PKTTYPE_TLMASK\t0x00000F00\n+#define IGC_RXDADV_PKTTYPE_NONE\t0x00000000\n+#define IGC_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPV4 hdr present */\n+#define IGC_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPV4 hdr + extensions */\n+#define IGC_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPV6 hdr present */\n+#define IGC_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPV6 hdr + extensions */\n+#define IGC_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n+#define IGC_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n+#define IGC_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n+#define IGC_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n+\n+#define IGC_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n+#define IGC_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n+#define IGC_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n+#define IGC_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n+#define IGC_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n+#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n+\n+/* LinkSec results */\n+/* Security Processing bit Indication */\n+#define IGC_RXDADV_LNKSEC_STATUS_SECP\t\t0x00020000\n+#define IGC_RXDADV_LNKSEC_ERROR_BIT_MASK\t0x18000000\n+#define IGC_RXDADV_LNKSEC_ERROR_NO_SA_MATCH\t0x08000000\n+#define IGC_RXDADV_LNKSEC_ERROR_REPLAY_ERROR\t0x10000000\n+#define IGC_RXDADV_LNKSEC_ERROR_BAD_SIG\t0x18000000\n+\n+#define IGC_RXDADV_IPSEC_STATUS_SECP\t\t\t0x00020000\n+#define IGC_RXDADV_IPSEC_ERROR_BIT_MASK\t\t0x18000000\n+#define IGC_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL\t0x08000000\n+#define IGC_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t\t0x10000000\n+#define IGC_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED\t0x18000000\n+\n+#define IGC_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wbk flushing */\n+/* Tx Queue Arbitration Priority 0=low, 1=high */\n+#define IGC_TXDCTL_PRIORITY\t\t0x08000000\n+\n+#define IGC_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc. wbk flushing */\n+\n+/* Direct Cache Access (DCA) definitions */\n+#define IGC_DCA_CTRL_DCA_ENABLE\t0x00000000 /* DCA Enable */\n+#define IGC_DCA_CTRL_DCA_DISABLE\t0x00000001 /* DCA Disable */\n+\n+#define IGC_DCA_CTRL_DCA_MODE_CB1\t0x00 /* DCA Mode CB1 */\n+#define IGC_DCA_CTRL_DCA_MODE_CB2\t0x02 /* DCA Mode CB2 */\n+\n+#define IGC_DCA_RXCTRL_CPUID_MASK\t0x0000001F /* Rx CPUID Mask */\n+#define IGC_DCA_RXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Rx Desc enable */\n+#define IGC_DCA_RXCTRL_HEAD_DCA_EN\t(1 << 6) /* DCA Rx Desc header ena */\n+#define IGC_DCA_RXCTRL_DATA_DCA_EN\t(1 << 7) /* DCA Rx Desc payload ena */\n+#define IGC_DCA_RXCTRL_DESC_RRO_EN\t(1 << 9) /* DCA Rx Desc Relax Order */\n+\n+#define IGC_DCA_TXCTRL_CPUID_MASK\t0x0000001F /* Tx CPUID Mask */\n+#define IGC_DCA_TXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Tx Desc enable */\n+#define IGC_DCA_TXCTRL_DESC_RRO_EN\t(1 << 9) /* Tx rd Desc Relax Order */\n+#define IGC_DCA_TXCTRL_TX_WB_RO_EN\t(1 << 11) /* Tx Desc writeback RO bit */\n+#define IGC_DCA_TXCTRL_DATA_RRO_EN\t(1 << 13) /* Tx rd data Relax Order */\n+\n+#define IGC_DCA_TXCTRL_CPUID_MASK_82576\t0xFF000000 /* Tx CPUID Mask */\n+#define IGC_DCA_RXCTRL_CPUID_MASK_82576\t0xFF000000 /* Rx CPUID Mask */\n+#define IGC_DCA_TXCTRL_CPUID_SHIFT_82576\t24 /* Tx CPUID */\n+#define IGC_DCA_RXCTRL_CPUID_SHIFT_82576\t24 /* Rx CPUID */\n+\n+/* Additional interrupt register bit definitions */\n+#define IGC_ICR_LSECPNS\t0x00000020 /* PN threshold - server */\n+#define IGC_IMS_LSECPNS\tIGC_ICR_LSECPNS /* PN threshold - server */\n+#define IGC_ICS_LSECPNS\tIGC_ICR_LSECPNS /* PN threshold - server */\n+\n+/* ETQF register bit definitions */\n+#define IGC_ETQF_FILTER_ENABLE\t(1 << 26)\n+#define IGC_ETQF_IMM_INT\t\t(1 << 29)\n+#define IGC_ETQF_QUEUE_ENABLE\t\t(1 << 31)\n+/*\n+ * ETQF filter list: one static filter per filter consumer. This is\n+ *                   to avoid filter collisions later. Add new filters\n+ *                   here!!\n+ *\n+ * Current filters:\n+ *    EAPOL 802.1x (0x888e): Filter 0\n+ */\n+#define IGC_ETQF_FILTER_EAPOL\t\t0\n+\n+#define IGC_FTQF_MASK_SOURCE_ADDR_BP\t0x20000000\n+#define IGC_FTQF_MASK_DEST_ADDR_BP\t0x40000000\n+#define IGC_FTQF_MASK_SOURCE_PORT_BP\t0x80000000\n+\n+#define IGC_NVM_APME_82575\t\t0x0400\n+#define MAX_NUM_VFS\t\t\t7\n+\n+#define IGC_DTXSWC_MAC_SPOOF_MASK\t0x000000FF /* Per VF MAC spoof cntrl */\n+#define IGC_DTXSWC_VLAN_SPOOF_MASK\t0x0000FF00 /* Per VF VLAN spoof cntrl */\n+#define IGC_DTXSWC_LLE_MASK\t\t0x00FF0000 /* Per VF Local LB enables */\n+#define IGC_DTXSWC_VLAN_SPOOF_SHIFT\t8\n+#define IGC_DTXSWC_LLE_SHIFT\t\t16\n+#define IGC_DTXSWC_VMDQ_LOOPBACK_EN\t(1 << 31)  /* global VF LB enable */\n+\n+/* Easy defines for setting default pool, would normally be left a zero */\n+#define IGC_VT_CTL_DEFAULT_POOL_SHIFT\t7\n+#define IGC_VT_CTL_DEFAULT_POOL_MASK\t(0x7 << IGC_VT_CTL_DEFAULT_POOL_SHIFT)\n+\n+/* Other useful VMD_CTL register defines */\n+#define IGC_VT_CTL_IGNORE_MAC\t\t(1 << 28)\n+#define IGC_VT_CTL_DISABLE_DEF_POOL\t(1 << 29)\n+#define IGC_VT_CTL_VM_REPL_EN\t\t(1 << 30)\n+\n+/* Per VM Offload register setup */\n+#define IGC_VMOLR_RLPML_MASK\t0x00003FFF /* Long Packet Maximum Length mask */\n+#define IGC_VMOLR_LPE\t\t0x00010000 /* Accept Long packet */\n+#define IGC_VMOLR_RSSE\t0x00020000 /* Enable RSS */\n+#define IGC_VMOLR_AUPE\t0x01000000 /* Accept untagged packets */\n+#define IGC_VMOLR_ROMPE\t0x02000000 /* Accept overflow multicast */\n+#define IGC_VMOLR_ROPE\t0x04000000 /* Accept overflow unicast */\n+#define IGC_VMOLR_BAM\t\t0x08000000 /* Accept Broadcast packets */\n+#define IGC_VMOLR_MPME\t0x10000000 /* Multicast promiscuous mode */\n+#define IGC_VMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n+#define IGC_VMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n+\n+#define IGC_VMOLR_VPE\t\t0x00800000 /* VLAN promiscuous enable */\n+#define IGC_VMOLR_UPE\t\t0x20000000 /* Unicast promisuous enable */\n+#define IGC_DVMOLR_HIDVLAN\t0x20000000 /* Vlan hiding enable */\n+#define IGC_DVMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n+#define IGC_DVMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n+\n+#define IGC_PBRWAC_WALPB\t0x00000007 /* Wrap around event on LAN Rx PB */\n+#define IGC_PBRWAC_PBE\t0x00000008 /* Rx packet buffer empty */\n+\n+#define IGC_VLVF_ARRAY_SIZE\t\t32\n+#define IGC_VLVF_VLANID_MASK\t\t0x00000FFF\n+#define IGC_VLVF_POOLSEL_SHIFT\t12\n+#define IGC_VLVF_POOLSEL_MASK\t\t(0xFF << IGC_VLVF_POOLSEL_SHIFT)\n+#define IGC_VLVF_LVLAN\t\t0x00100000\n+#define IGC_VLVF_VLANID_ENABLE\t0x80000000\n+\n+#define IGC_VMVIR_VLANA_DEFAULT\t0x40000000 /* Always use default VLAN */\n+#define IGC_VMVIR_VLANA_NEVER\t\t0x80000000 /* Never insert VLAN tag */\n+\n+#define IGC_VF_INIT_TIMEOUT\t200 /* Number of retries to clear RSTI */\n+\n+#define IGC_IOVCTL\t\t0x05BBC\n+#define IGC_IOVCTL_REUSE_VFQ\t0x00000001\n+\n+#define IGC_RPLOLR_STRVLAN\t0x40000000\n+#define IGC_RPLOLR_STRCRC\t0x80000000\n+\n+#define IGC_TCTL_EXT_COLD\t0x000FFC00\n+#define IGC_TCTL_EXT_COLD_SHIFT\t10\n+\n+#define IGC_DTXCTL_8023LL\t0x0004\n+#define IGC_DTXCTL_VLAN_ADDED\t0x0008\n+#define IGC_DTXCTL_OOS_ENABLE\t0x0010\n+#define IGC_DTXCTL_MDP_EN\t0x0020\n+#define IGC_DTXCTL_SPOOF_INT\t0x0040\n+\n+#define IGC_EEPROM_PCS_AUTONEG_DISABLE_BIT\t(1 << 14)\n+\n+#define ALL_QUEUES\t\t0xFFFF\n+\n+s32 igc_reset_init_script_82575(struct igc_hw *hw);\n+s32 igc_init_nvm_params_82575(struct igc_hw *hw);\n+\n+/* Rx packet buffer size defines */\n+#define IGC_RXPBS_SIZE_MASK_82576\t0x0000007F\n+void igc_vmdq_set_loopback_pf(struct igc_hw *hw, bool enable);\n+void igc_vmdq_set_anti_spoofing_pf(struct igc_hw *hw, bool enable, int pf);\n+void igc_vmdq_set_replication_pf(struct igc_hw *hw, bool enable);\n+\n+enum igc_promisc_type {\n+\tigc_promisc_disabled = 0,   /* all promisc modes disabled */\n+\tigc_promisc_unicast = 1,    /* unicast promiscuous enabled */\n+\tigc_promisc_multicast = 2,  /* multicast promiscuous enabled */\n+\tigc_promisc_enabled = 3,    /* both uni and multicast promisc */\n+\tigc_num_promisc_types\n+};\n+\n+#endif /* _IGC_82575_H_ */\ndiff --git a/drivers/net/igc/base/e1000_api.c b/drivers/net/igc/base/e1000_api.c\nnew file mode 100644\nindex 0000000..70620e2\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_api.c\n@@ -0,0 +1,1845 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+/**\n+ *  igc_get_i2c_data - Reads the I2C SDA data bit\n+ *  @i2cctl: Current value of I2CCTL register\n+ *\n+ *  Returns the I2C data bit value\n+ **/\n+static bool igc_get_i2c_data(u32 *i2cctl)\n+{\n+\tbool data;\n+\n+\tDEBUGFUNC(\"igc_get_i2c_data\");\n+\n+\tif (*i2cctl & IGC_I2C_DATA_IN)\n+\t\tdata = 1;\n+\telse\n+\t\tdata = 0;\n+\n+\treturn data;\n+}\n+\n+/**\n+ *  igc_set_i2c_data - Sets the I2C data bit\n+ *  @hw: pointer to hardware structure\n+ *  @i2cctl: Current value of I2CCTL register\n+ *  @data: I2C data value (0 or 1) to set\n+ *\n+ *  Sets the I2C data bit\n+ **/\n+static s32 igc_set_i2c_data(struct igc_hw *hw, u32 *i2cctl, bool data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_set_i2c_data\");\n+\n+\tif (data)\n+\t\t*i2cctl |= IGC_I2C_DATA_OUT;\n+\telse\n+\t\t*i2cctl &= ~IGC_I2C_DATA_OUT;\n+\n+\t*i2cctl &= ~IGC_I2C_DATA_OE_N;\n+\t*i2cctl |= IGC_I2C_CLK_OE_N;\n+\tIGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n+\tusec_delay(IGC_I2C_T_RISE + IGC_I2C_T_FALL + IGC_I2C_T_SU_DATA);\n+\n+\t*i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\tif (data != igc_get_i2c_data(i2cctl)) {\n+\t\tstatus = IGC_ERR_I2C;\n+\t\tDEBUGOUT1(\"Error - I2C data was not set to %X.\\n\", data);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_raise_i2c_clk - Raises the I2C SCL clock\n+ *  @hw: pointer to hardware structure\n+ *  @i2cctl: Current value of I2CCTL register\n+ *\n+ *  Raises the I2C clock line '0'->'1'\n+ **/\n+static void igc_raise_i2c_clk(struct igc_hw *hw, u32 *i2cctl)\n+{\n+\tDEBUGFUNC(\"igc_raise_i2c_clk\");\n+\n+\t*i2cctl |= IGC_I2C_CLK_OUT;\n+\t*i2cctl &= ~IGC_I2C_CLK_OE_N;\n+\tIGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\t/* SCL rise time (1000ns) */\n+\tusec_delay(IGC_I2C_T_RISE);\n+}\n+\n+/**\n+ *  igc_lower_i2c_clk - Lowers the I2C SCL clock\n+ *  @hw: pointer to hardware structure\n+ *  @i2cctl: Current value of I2CCTL register\n+ *\n+ *  Lowers the I2C clock line '1'->'0'\n+ **/\n+static void igc_lower_i2c_clk(struct igc_hw *hw, u32 *i2cctl)\n+{\n+\tDEBUGFUNC(\"igc_lower_i2c_clk\");\n+\n+\t*i2cctl &= ~IGC_I2C_CLK_OUT;\n+\t*i2cctl &= ~IGC_I2C_CLK_OE_N;\n+\tIGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\t/* SCL fall time (300ns) */\n+\tusec_delay(IGC_I2C_T_FALL);\n+}\n+\n+/**\n+ *  igc_i2c_start - Sets I2C start condition\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Sets I2C start condition (High -> Low on SDA while SCL is High)\n+ **/\n+static void igc_i2c_start(struct igc_hw *hw)\n+{\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\n+\tDEBUGFUNC(\"igc_i2c_start\");\n+\n+\t/* Start condition must begin with data and clock high */\n+\tigc_set_i2c_data(hw, &i2cctl, 1);\n+\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t/* Setup time for start condition (4.7us) */\n+\tusec_delay(IGC_I2C_T_SU_STA);\n+\n+\tigc_set_i2c_data(hw, &i2cctl, 0);\n+\n+\t/* Hold time for start condition (4us) */\n+\tusec_delay(IGC_I2C_T_HD_STA);\n+\n+\tigc_lower_i2c_clk(hw, &i2cctl);\n+\n+\t/* Minimum low period of clock is 4.7 us */\n+\tusec_delay(IGC_I2C_T_LOW);\n+}\n+\n+/**\n+ *  igc_i2c_stop - Sets I2C stop condition\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Sets I2C stop condition (Low -> High on SDA while SCL is High)\n+ **/\n+static void igc_i2c_stop(struct igc_hw *hw)\n+{\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\n+\tDEBUGFUNC(\"igc_i2c_stop\");\n+\n+\t/* Stop condition must begin with data low and clock high */\n+\tigc_set_i2c_data(hw, &i2cctl, 0);\n+\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t/* Setup time for stop condition (4us) */\n+\tusec_delay(IGC_I2C_T_SU_STO);\n+\n+\tigc_set_i2c_data(hw, &i2cctl, 1);\n+\n+\t/* bus free time between stop and start (4.7us)*/\n+\tusec_delay(IGC_I2C_T_BUF);\n+}\n+\n+/**\n+ *  igc_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n+ *  @hw: pointer to hardware structure\n+ *  @data: read data value\n+ *\n+ *  Clocks in one bit via I2C data/clock\n+ **/\n+static void igc_clock_in_i2c_bit(struct igc_hw *hw, bool *data)\n+{\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\n+\tDEBUGFUNC(\"igc_clock_in_i2c_bit\");\n+\n+\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t/* Minimum high period of clock is 4us */\n+\tusec_delay(IGC_I2C_T_HIGH);\n+\n+\ti2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\t*data = igc_get_i2c_data(&i2cctl);\n+\n+\tigc_lower_i2c_clk(hw, &i2cctl);\n+\n+\t/* Minimum low period of clock is 4.7 us */\n+\tusec_delay(IGC_I2C_T_LOW);\n+}\n+\n+/**\n+ *  igc_clock_in_i2c_byte - Clocks in one byte via I2C\n+ *  @hw: pointer to hardware structure\n+ *  @data: data byte to clock in\n+ *\n+ *  Clocks in one byte data via I2C data/clock\n+ **/\n+static void igc_clock_in_i2c_byte(struct igc_hw *hw, u8 *data)\n+{\n+\ts32 i;\n+\tbool bit = 0;\n+\n+\tDEBUGFUNC(\"igc_clock_in_i2c_byte\");\n+\n+\t*data = 0;\n+\tfor (i = 7; i >= 0; i--) {\n+\t\tigc_clock_in_i2c_bit(hw, &bit);\n+\t\t*data |= bit << i;\n+\t}\n+}\n+\n+/**\n+ *  igc_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n+ *  @hw: pointer to hardware structure\n+ *  @data: data value to write\n+ *\n+ *  Clocks out one bit via I2C data/clock\n+ **/\n+static s32 igc_clock_out_i2c_bit(struct igc_hw *hw, bool data)\n+{\n+\ts32 status;\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\n+\tDEBUGFUNC(\"igc_clock_out_i2c_bit\");\n+\n+\tstatus = igc_set_i2c_data(hw, &i2cctl, data);\n+\tif (status == IGC_SUCCESS) {\n+\t\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t\t/* Minimum high period of clock is 4us */\n+\t\tusec_delay(IGC_I2C_T_HIGH);\n+\n+\t\tigc_lower_i2c_clk(hw, &i2cctl);\n+\n+\t\t/* Minimum low period of clock is 4.7 us.\n+\t\t * This also takes care of the data hold time.\n+\t\t */\n+\t\tusec_delay(IGC_I2C_T_LOW);\n+\t} else {\n+\t\tstatus = IGC_ERR_I2C;\n+\t\tDEBUGOUT1(\"I2C data was not set to %X\\n\", data);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_clock_out_i2c_byte - Clocks out one byte via I2C\n+ *  @hw: pointer to hardware structure\n+ *  @data: data byte clocked out\n+ *\n+ *  Clocks out one byte data via I2C data/clock\n+ **/\n+static s32 igc_clock_out_i2c_byte(struct igc_hw *hw, u8 data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\ts32 i;\n+\tu32 i2cctl;\n+\tbool bit = 0;\n+\n+\tDEBUGFUNC(\"igc_clock_out_i2c_byte\");\n+\n+\tfor (i = 7; i >= 0; i--) {\n+\t\tbit = (data >> i) & 0x1;\n+\t\tstatus = igc_clock_out_i2c_bit(hw, bit);\n+\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* Release SDA line (set high) */\n+\ti2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\n+\ti2cctl |= IGC_I2C_DATA_OE_N;\n+\tIGC_WRITE_REG(hw, IGC_I2CPARAMS, i2cctl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_get_i2c_ack - Polls for I2C ACK\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Clocks in/out one bit via I2C data/clock\n+ **/\n+static s32 igc_get_i2c_ack(struct igc_hw *hw)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\tu32 i = 0;\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\tu32 timeout = 10;\n+\tbool ack = true;\n+\n+\tDEBUGFUNC(\"igc_get_i2c_ack\");\n+\n+\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t/* Minimum high period of clock is 4us */\n+\tusec_delay(IGC_I2C_T_HIGH);\n+\n+\t/* Wait until SCL returns high */\n+\tfor (i = 0; i < timeout; i++) {\n+\t\tusec_delay(1);\n+\t\ti2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\t\tif (i2cctl & IGC_I2C_CLK_IN)\n+\t\t\tbreak;\n+\t}\n+\tif (!(i2cctl & IGC_I2C_CLK_IN))\n+\t\treturn IGC_ERR_I2C;\n+\n+\tack = igc_get_i2c_data(&i2cctl);\n+\tif (ack) {\n+\t\tDEBUGOUT(\"I2C ack was not received.\\n\");\n+\t\tstatus = IGC_ERR_I2C;\n+\t}\n+\n+\tigc_lower_i2c_clk(hw, &i2cctl);\n+\n+\t/* Minimum low period of clock is 4.7 us */\n+\tusec_delay(IGC_I2C_T_LOW);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_set_i2c_bb - Enable I2C bit-bang\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Enable I2C bit-bang interface\n+ *\n+ **/\n+s32 igc_set_i2c_bb(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu32 ctrl_ext, i2cparams;\n+\n+\tDEBUGFUNC(\"igc_set_i2c_bb\");\n+\n+\tctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);\n+\tctrl_ext |= IGC_CTRL_I2C_ENA;\n+\tIGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\ti2cparams = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\ti2cparams |= IGC_I2CBB_EN;\n+\ti2cparams |= IGC_I2C_DATA_OE_N;\n+\ti2cparams |= IGC_I2C_CLK_OE_N;\n+\tIGC_WRITE_REG(hw, IGC_I2CPARAMS, i2cparams);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_i2c_byte_generic - Reads 8 bit word over I2C\n+ *  @hw: pointer to hardware structure\n+ *  @byte_offset: byte offset to read\n+ *  @dev_addr: device address\n+ *  @data: value read\n+ *\n+ *  Performs byte read operation over I2C interface at\n+ *  a specified device address.\n+ **/\n+s32 igc_read_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 dev_addr, u8 *data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\tu32 max_retry = 10;\n+\tu32 retry = 1;\n+\tu16 swfw_mask = 0;\n+\n+\tbool nack = true;\n+\n+\tDEBUGFUNC(\"igc_read_i2c_byte_generic\");\n+\n+\tswfw_mask = IGC_SWFW_PHY0_SM;\n+\n+\tdo {\n+\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n+\t\t    != IGC_SUCCESS) {\n+\t\t\tstatus = IGC_ERR_SWFW_SYNC;\n+\t\t\tgoto read_byte_out;\n+\t\t}\n+\n+\t\tigc_i2c_start(hw);\n+\n+\t\t/* Device Address and write indication */\n+\t\tstatus = igc_clock_out_i2c_byte(hw, dev_addr);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_clock_out_i2c_byte(hw, byte_offset);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tigc_i2c_start(hw);\n+\n+\t\t/* Device Address and read indication */\n+\t\tstatus = igc_clock_out_i2c_byte(hw, (dev_addr | 0x1));\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tigc_clock_in_i2c_byte(hw, data);\n+\n+\t\tstatus = igc_clock_out_i2c_bit(hw, nack);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tigc_i2c_stop(hw);\n+\t\tbreak;\n+\n+fail:\n+\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\t\tmsec_delay(100);\n+\t\tigc_i2c_bus_clear(hw);\n+\t\tretry++;\n+\t\tif (retry < max_retry)\n+\t\t\tDEBUGOUT(\"I2C byte read error - Retrying.\\n\");\n+\t\telse\n+\t\t\tDEBUGOUT(\"I2C byte read error.\\n\");\n+\n+\t} while (retry < max_retry);\n+\n+\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\n+read_byte_out:\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_write_i2c_byte_generic - Writes 8 bit word over I2C\n+ *  @hw: pointer to hardware structure\n+ *  @byte_offset: byte offset to write\n+ *  @dev_addr: device address\n+ *  @data: value to write\n+ *\n+ *  Performs byte write operation over I2C interface at\n+ *  a specified device address.\n+ **/\n+s32 igc_write_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t\t u8 dev_addr, u8 data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\tu32 max_retry = 1;\n+\tu32 retry = 0;\n+\tu16 swfw_mask = 0;\n+\n+\tDEBUGFUNC(\"igc_write_i2c_byte_generic\");\n+\n+\tswfw_mask = IGC_SWFW_PHY0_SM;\n+\n+\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IGC_SUCCESS) {\n+\t\tstatus = IGC_ERR_SWFW_SYNC;\n+\t\tgoto write_byte_out;\n+\t}\n+\n+\tdo {\n+\t\tigc_i2c_start(hw);\n+\n+\t\tstatus = igc_clock_out_i2c_byte(hw, dev_addr);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_clock_out_i2c_byte(hw, byte_offset);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_clock_out_i2c_byte(hw, data);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tstatus = igc_get_i2c_ack(hw);\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tgoto fail;\n+\n+\t\tigc_i2c_stop(hw);\n+\t\tbreak;\n+\n+fail:\n+\t\tigc_i2c_bus_clear(hw);\n+\t\tretry++;\n+\t\tif (retry < max_retry)\n+\t\t\tDEBUGOUT(\"I2C byte write error - Retrying.\\n\");\n+\t\telse\n+\t\t\tDEBUGOUT(\"I2C byte write error.\\n\");\n+\t} while (retry < max_retry);\n+\n+\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\n+write_byte_out:\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  igc_i2c_bus_clear - Clears the I2C bus\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Clears the I2C bus by sending nine clock pulses.\n+ *  Used when data line is stuck low.\n+ **/\n+void igc_i2c_bus_clear(struct igc_hw *hw)\n+{\n+\tu32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);\n+\tu32 i;\n+\n+\tDEBUGFUNC(\"igc_i2c_bus_clear\");\n+\n+\tigc_i2c_start(hw);\n+\n+\tigc_set_i2c_data(hw, &i2cctl, 1);\n+\n+\tfor (i = 0; i < 9; i++) {\n+\t\tigc_raise_i2c_clk(hw, &i2cctl);\n+\n+\t\t/* Min high period of clock is 4us */\n+\t\tusec_delay(IGC_I2C_T_HIGH);\n+\n+\t\tigc_lower_i2c_clk(hw, &i2cctl);\n+\n+\t\t/* Min low period of clock is 4.7us*/\n+\t\tusec_delay(IGC_I2C_T_LOW);\n+\t}\n+\n+\tigc_i2c_start(hw);\n+\n+\t/* Put the i2c bus back to default state */\n+\tigc_i2c_stop(hw);\n+}\n+\n+/**\n+ *  igc_init_mac_params - Initialize MAC function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function initializes the function pointers for the MAC\n+ *  set of functions.  Called by drivers or by igc_setup_init_funcs.\n+ **/\n+s32 igc_init_mac_params(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tif (hw->mac.ops.init_params) {\n+\t\tret_val = hw->mac.ops.init_params(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"MAC Initialization Error\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\tDEBUGOUT(\"mac.init_mac_params was NULL\\n\");\n+\t\tret_val = -IGC_ERR_CONFIG;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_init_nvm_params - Initialize NVM function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function initializes the function pointers for the NVM\n+ *  set of functions.  Called by drivers or by igc_setup_init_funcs.\n+ **/\n+s32 igc_init_nvm_params(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tif (hw->nvm.ops.init_params) {\n+\t\tret_val = hw->nvm.ops.init_params(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"NVM Initialization Error\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\tDEBUGOUT(\"nvm.init_nvm_params was NULL\\n\");\n+\t\tret_val = -IGC_ERR_CONFIG;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_init_phy_params - Initialize PHY function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function initializes the function pointers for the PHY\n+ *  set of functions.  Called by drivers or by igc_setup_init_funcs.\n+ **/\n+s32 igc_init_phy_params(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tif (hw->phy.ops.init_params) {\n+\t\tret_val = hw->phy.ops.init_params(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"PHY Initialization Error\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\tDEBUGOUT(\"phy.init_phy_params was NULL\\n\");\n+\t\tret_val =  -IGC_ERR_CONFIG;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_init_mbx_params - Initialize mailbox function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function initializes the function pointers for the PHY\n+ *  set of functions.  Called by drivers or by igc_setup_init_funcs.\n+ **/\n+s32 igc_init_mbx_params(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tif (hw->mbx.ops.init_params) {\n+\t\tret_val = hw->mbx.ops.init_params(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Mailbox Initialization Error\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\tDEBUGOUT(\"mbx.init_mbx_params was NULL\\n\");\n+\t\tret_val =  -IGC_ERR_CONFIG;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_set_mac_type - Sets MAC type\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function sets the mac type of the adapter based on the\n+ *  device ID stored in the hw structure.\n+ *  MUST BE FIRST FUNCTION CALLED (explicitly or through\n+ *  igc_setup_init_funcs()).\n+ **/\n+s32 igc_set_mac_type(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_set_mac_type\");\n+\n+\tswitch (hw->device_id) {\n+\tcase IGC_DEV_ID_82542:\n+\t\tmac->type = igc_82542;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82543GC_FIBER:\n+\tcase IGC_DEV_ID_82543GC_COPPER:\n+\t\tmac->type = igc_82543;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82544EI_COPPER:\n+\tcase IGC_DEV_ID_82544EI_FIBER:\n+\tcase IGC_DEV_ID_82544GC_COPPER:\n+\tcase IGC_DEV_ID_82544GC_LOM:\n+\t\tmac->type = igc_82544;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82540EM:\n+\tcase IGC_DEV_ID_82540EM_LOM:\n+\tcase IGC_DEV_ID_82540EP:\n+\tcase IGC_DEV_ID_82540EP_LOM:\n+\tcase IGC_DEV_ID_82540EP_LP:\n+\t\tmac->type = igc_82540;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82545EM_COPPER:\n+\tcase IGC_DEV_ID_82545EM_FIBER:\n+\t\tmac->type = igc_82545;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82545GM_COPPER:\n+\tcase IGC_DEV_ID_82545GM_FIBER:\n+\tcase IGC_DEV_ID_82545GM_SERDES:\n+\t\tmac->type = igc_82545_rev_3;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82546EB_COPPER:\n+\tcase IGC_DEV_ID_82546EB_FIBER:\n+\tcase IGC_DEV_ID_82546EB_QUAD_COPPER:\n+\t\tmac->type = igc_82546;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82546GB_COPPER:\n+\tcase IGC_DEV_ID_82546GB_FIBER:\n+\tcase IGC_DEV_ID_82546GB_SERDES:\n+\tcase IGC_DEV_ID_82546GB_PCIE:\n+\tcase IGC_DEV_ID_82546GB_QUAD_COPPER:\n+\tcase IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3:\n+\t\tmac->type = igc_82546_rev_3;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82541EI:\n+\tcase IGC_DEV_ID_82541EI_MOBILE:\n+\tcase IGC_DEV_ID_82541ER_LOM:\n+\t\tmac->type = igc_82541;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82541ER:\n+\tcase IGC_DEV_ID_82541GI:\n+\tcase IGC_DEV_ID_82541GI_LF:\n+\tcase IGC_DEV_ID_82541GI_MOBILE:\n+\t\tmac->type = igc_82541_rev_2;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82547EI:\n+\tcase IGC_DEV_ID_82547EI_MOBILE:\n+\t\tmac->type = igc_82547;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82547GI:\n+\t\tmac->type = igc_82547_rev_2;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82571EB_COPPER:\n+\tcase IGC_DEV_ID_82571EB_FIBER:\n+\tcase IGC_DEV_ID_82571EB_SERDES:\n+\tcase IGC_DEV_ID_82571EB_SERDES_DUAL:\n+\tcase IGC_DEV_ID_82571EB_SERDES_QUAD:\n+\tcase IGC_DEV_ID_82571EB_QUAD_COPPER:\n+\tcase IGC_DEV_ID_82571PT_QUAD_COPPER:\n+\tcase IGC_DEV_ID_82571EB_QUAD_FIBER:\n+\tcase IGC_DEV_ID_82571EB_QUAD_COPPER_LP:\n+\t\tmac->type = igc_82571;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82572EI:\n+\tcase IGC_DEV_ID_82572EI_COPPER:\n+\tcase IGC_DEV_ID_82572EI_FIBER:\n+\tcase IGC_DEV_ID_82572EI_SERDES:\n+\t\tmac->type = igc_82572;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82573E:\n+\tcase IGC_DEV_ID_82573E_IAMT:\n+\tcase IGC_DEV_ID_82573L:\n+\t\tmac->type = igc_82573;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82574L:\n+\tcase IGC_DEV_ID_82574LA:\n+\t\tmac->type = igc_82574;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82583V:\n+\t\tmac->type = igc_82583;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_80003ES2LAN_COPPER_DPT:\n+\tcase IGC_DEV_ID_80003ES2LAN_SERDES_DPT:\n+\tcase IGC_DEV_ID_80003ES2LAN_COPPER_SPT:\n+\tcase IGC_DEV_ID_80003ES2LAN_SERDES_SPT:\n+\t\tmac->type = igc_80003es2lan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_ICH8_IFE:\n+\tcase IGC_DEV_ID_ICH8_IFE_GT:\n+\tcase IGC_DEV_ID_ICH8_IFE_G:\n+\tcase IGC_DEV_ID_ICH8_IGP_M:\n+\tcase IGC_DEV_ID_ICH8_IGP_M_AMT:\n+\tcase IGC_DEV_ID_ICH8_IGP_AMT:\n+\tcase IGC_DEV_ID_ICH8_IGP_C:\n+\tcase IGC_DEV_ID_ICH8_82567V_3:\n+\t\tmac->type = igc_ich8lan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_ICH9_IFE:\n+\tcase IGC_DEV_ID_ICH9_IFE_GT:\n+\tcase IGC_DEV_ID_ICH9_IFE_G:\n+\tcase IGC_DEV_ID_ICH9_IGP_M:\n+\tcase IGC_DEV_ID_ICH9_IGP_M_AMT:\n+\tcase IGC_DEV_ID_ICH9_IGP_M_V:\n+\tcase IGC_DEV_ID_ICH9_IGP_AMT:\n+\tcase IGC_DEV_ID_ICH9_BM:\n+\tcase IGC_DEV_ID_ICH9_IGP_C:\n+\tcase IGC_DEV_ID_ICH10_R_BM_LM:\n+\tcase IGC_DEV_ID_ICH10_R_BM_LF:\n+\tcase IGC_DEV_ID_ICH10_R_BM_V:\n+\t\tmac->type = igc_ich9lan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_ICH10_D_BM_LM:\n+\tcase IGC_DEV_ID_ICH10_D_BM_LF:\n+\tcase IGC_DEV_ID_ICH10_D_BM_V:\n+\t\tmac->type = igc_ich10lan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_PCH_D_HV_DM:\n+\tcase IGC_DEV_ID_PCH_D_HV_DC:\n+\tcase IGC_DEV_ID_PCH_M_HV_LM:\n+\tcase IGC_DEV_ID_PCH_M_HV_LC:\n+\t\tmac->type = igc_pchlan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_PCH2_LV_LM:\n+\tcase IGC_DEV_ID_PCH2_LV_V:\n+\t\tmac->type = igc_pch2lan;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_PCH_LPT_I217_LM:\n+\tcase IGC_DEV_ID_PCH_LPT_I217_V:\n+\tcase IGC_DEV_ID_PCH_LPTLP_I218_LM:\n+\tcase IGC_DEV_ID_PCH_LPTLP_I218_V:\n+\tcase IGC_DEV_ID_PCH_I218_LM2:\n+\tcase IGC_DEV_ID_PCH_I218_V2:\n+\tcase IGC_DEV_ID_PCH_I218_LM3:\n+\tcase IGC_DEV_ID_PCH_I218_V3:\n+\t\tmac->type = igc_pch_lpt;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_PCH_SPT_I219_LM:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_V:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_LM2:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_V2:\n+\tcase IGC_DEV_ID_PCH_LBG_I219_LM3:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_LM4:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_V4:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_LM5:\n+\tcase IGC_DEV_ID_PCH_SPT_I219_V5:\n+\t\tmac->type = igc_pch_spt;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_PCH_CNP_I219_LM6:\n+\tcase IGC_DEV_ID_PCH_CNP_I219_V6:\n+\tcase IGC_DEV_ID_PCH_CNP_I219_LM7:\n+\tcase IGC_DEV_ID_PCH_CNP_I219_V7:\n+\tcase IGC_DEV_ID_PCH_ICP_I219_LM8:\n+\tcase IGC_DEV_ID_PCH_ICP_I219_V8:\n+\tcase IGC_DEV_ID_PCH_ICP_I219_LM9:\n+\tcase IGC_DEV_ID_PCH_ICP_I219_V9:\n+\t\tmac->type = igc_pch_cnp;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82575EB_COPPER:\n+\tcase IGC_DEV_ID_82575EB_FIBER_SERDES:\n+\tcase IGC_DEV_ID_82575GB_QUAD_COPPER:\n+\t\tmac->type = igc_82575;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82576:\n+\tcase IGC_DEV_ID_82576_FIBER:\n+\tcase IGC_DEV_ID_82576_SERDES:\n+\tcase IGC_DEV_ID_82576_QUAD_COPPER:\n+\tcase IGC_DEV_ID_82576_QUAD_COPPER_ET2:\n+\tcase IGC_DEV_ID_82576_NS:\n+\tcase IGC_DEV_ID_82576_NS_SERDES:\n+\tcase IGC_DEV_ID_82576_SERDES_QUAD:\n+\t\tmac->type = igc_82576;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82576_VF:\n+\tcase IGC_DEV_ID_82576_VF_HV:\n+\t\tmac->type = igc_vfadapt;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_82580_COPPER:\n+\tcase IGC_DEV_ID_82580_FIBER:\n+\tcase IGC_DEV_ID_82580_SERDES:\n+\tcase IGC_DEV_ID_82580_SGMII:\n+\tcase IGC_DEV_ID_82580_COPPER_DUAL:\n+\tcase IGC_DEV_ID_82580_QUAD_FIBER:\n+\tcase IGC_DEV_ID_DH89XXCC_SGMII:\n+\tcase IGC_DEV_ID_DH89XXCC_SERDES:\n+\tcase IGC_DEV_ID_DH89XXCC_BACKPLANE:\n+\tcase IGC_DEV_ID_DH89XXCC_SFP:\n+\t\tmac->type = igc_82580;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I350_COPPER:\n+\tcase IGC_DEV_ID_I350_FIBER:\n+\tcase IGC_DEV_ID_I350_SERDES:\n+\tcase IGC_DEV_ID_I350_SGMII:\n+\tcase IGC_DEV_ID_I350_DA4:\n+\t\tmac->type = igc_i350;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I210_COPPER_FLASHLESS:\n+\tcase IGC_DEV_ID_I210_SERDES_FLASHLESS:\n+\tcase IGC_DEV_ID_I210_SGMII_FLASHLESS:\n+\tcase IGC_DEV_ID_I210_COPPER:\n+\tcase IGC_DEV_ID_I210_COPPER_OEM1:\n+\tcase IGC_DEV_ID_I210_COPPER_IT:\n+\tcase IGC_DEV_ID_I210_FIBER:\n+\tcase IGC_DEV_ID_I210_SERDES:\n+\tcase IGC_DEV_ID_I210_SGMII:\n+\t\tmac->type = igc_i210;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I211_COPPER:\n+\t\tmac->type = igc_i211;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I225_LM:\n+\tcase IGC_DEV_ID_I225_V:\n+\tcase IGC_DEV_ID_I225_K:\n+\tcase IGC_DEV_ID_I225_I:\n+\tcase IGC_DEV_ID_I220_V:\n+\tcase IGC_DEV_ID_I225_BLANK_NVM:\n+\t\tmac->type = igc_i225;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I350_VF:\n+\tcase IGC_DEV_ID_I350_VF_HV:\n+\t\tmac->type = igc_vfadapt_i350;\n+\t\tbreak;\n+\tcase IGC_DEV_ID_I354_BACKPLANE_1GBPS:\n+\tcase IGC_DEV_ID_I354_SGMII:\n+\tcase IGC_DEV_ID_I354_BACKPLANE_2_5GBPS:\n+\t\tmac->type = igc_i354;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Should never have loaded on this device */\n+\t\tret_val = -IGC_ERR_MAC_INIT;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_setup_init_funcs - Initializes function pointers\n+ *  @hw: pointer to the HW structure\n+ *  @init_device: true will initialize the rest of the function pointers\n+ *\t\t  getting the device ready for use.  false will only set\n+ *\t\t  MAC type and the function pointers for the other init\n+ *\t\t  functions.  Passing false will not generate any hardware\n+ *\t\t  reads or writes.\n+ *\n+ *  This function must be called by a driver in order to use the rest\n+ *  of the 'shared' code files. Called by drivers only.\n+ **/\n+s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device)\n+{\n+\ts32 ret_val;\n+\n+\t/* Can't do much good without knowing the MAC type. */\n+\tret_val = igc_set_mac_type(hw);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"ERROR: MAC type could not be set properly.\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (!hw->hw_addr) {\n+\t\tDEBUGOUT(\"ERROR: Registers not mapped\\n\");\n+\t\tret_val = -IGC_ERR_CONFIG;\n+\t\tgoto out;\n+\t}\n+\n+\t/*\n+\t * Init function pointers to generic implementations. We do this first\n+\t * allowing a driver module to override it afterward.\n+\t */\n+\tigc_init_mac_ops_generic(hw);\n+\tigc_init_phy_ops_generic(hw);\n+\tigc_init_nvm_ops_generic(hw);\n+\n+\t/*\n+\t * Set up the init function pointers. These are functions within the\n+\t * adapter family file that sets up function pointers for the rest of\n+\t * the functions in that family.\n+\t */\n+\tswitch (hw->mac.type) {\n+\tcase igc_i225:\n+\t\tigc_init_function_pointers_i225(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tDEBUGOUT(\"Hardware not supported\\n\");\n+\t\tret_val = -IGC_ERR_CONFIG;\n+\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * Initialize the rest of the function pointers. These require some\n+\t * register reads/writes in some cases.\n+\t */\n+\tif (!(ret_val) && init_device) {\n+\t\tret_val = igc_init_mac_params(hw);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n+\n+\t\tret_val = igc_init_nvm_params(hw);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n+\n+\t\tret_val = igc_init_phy_params(hw);\n+\t\tif (ret_val)\n+\t\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_bus_info - Obtain bus information for adapter\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This will obtain information about the HW bus for which the\n+ *  adapter is attached and stores it in the hw structure. This is a\n+ *  function pointer entry point called by drivers.\n+ **/\n+s32 igc_get_bus_info(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.get_bus_info)\n+\t\treturn hw->mac.ops.get_bus_info(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_clear_vfta - Clear VLAN filter table\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This clears the VLAN filter table on the adapter. This is a function\n+ *  pointer entry point called by drivers.\n+ **/\n+void igc_clear_vfta(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.clear_vfta)\n+\t\thw->mac.ops.clear_vfta(hw);\n+}\n+\n+/**\n+ *  igc_write_vfta - Write value to VLAN filter table\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the 32-bit offset in which to write the value to.\n+ *  @value: the 32-bit value to write at location offset.\n+ *\n+ *  This writes a 32-bit value to a 32-bit offset in the VLAN filter\n+ *  table. This is a function pointer entry point called by drivers.\n+ **/\n+void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value)\n+{\n+\tif (hw->mac.ops.write_vfta)\n+\t\thw->mac.ops.write_vfta(hw, offset, value);\n+}\n+\n+/**\n+ *  igc_update_mc_addr_list - Update Multicast addresses\n+ *  @hw: pointer to the HW structure\n+ *  @mc_addr_list: array of multicast addresses to program\n+ *  @mc_addr_count: number of multicast addresses to program\n+ *\n+ *  Updates the Multicast Table Array.\n+ *  The caller must have a packed mc_addr_list of multicast addresses.\n+ **/\n+void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,\n+\t\t\t       u32 mc_addr_count)\n+{\n+\tif (hw->mac.ops.update_mc_addr_list)\n+\t\thw->mac.ops.update_mc_addr_list(hw, mc_addr_list,\n+\t\t\t\t\t\tmc_addr_count);\n+}\n+\n+/**\n+ *  igc_force_mac_fc - Force MAC flow control\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Force the MAC's flow control settings. Currently no func pointer exists\n+ *  and all implementations are handled in the generic version of this\n+ *  function.\n+ **/\n+s32 igc_force_mac_fc(struct igc_hw *hw)\n+{\n+\treturn igc_force_mac_fc_generic(hw);\n+}\n+\n+/**\n+ *  igc_check_for_link - Check/Store link connection\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This checks the link condition of the adapter and stores the\n+ *  results in the hw->mac structure. This is a function pointer entry\n+ *  point called by drivers.\n+ **/\n+s32 igc_check_for_link(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.check_for_link)\n+\t\treturn hw->mac.ops.check_for_link(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_check_mng_mode - Check management mode\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This checks if the adapter has manageability enabled.\n+ *  This is a function pointer entry point called by drivers.\n+ **/\n+bool igc_check_mng_mode(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.check_mng_mode)\n+\t\treturn hw->mac.ops.check_mng_mode(hw);\n+\n+\treturn false;\n+}\n+\n+/**\n+ *  igc_mng_write_dhcp_info - Writes DHCP info to host interface\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: pointer to the host interface\n+ *  @length: size of the buffer\n+ *\n+ *  Writes the DHCP information to the host interface.\n+ **/\n+s32 igc_mng_write_dhcp_info(struct igc_hw *hw, u8 *buffer, u16 length)\n+{\n+\treturn igc_mng_write_dhcp_info_generic(hw, buffer, length);\n+}\n+\n+/**\n+ *  igc_reset_hw - Reset hardware\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This resets the hardware into a known state. This is a function pointer\n+ *  entry point called by drivers.\n+ **/\n+s32 igc_reset_hw(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.reset_hw)\n+\t\treturn hw->mac.ops.reset_hw(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_init_hw - Initialize hardware\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This inits the hardware readying it for operation. This is a function\n+ *  pointer entry point called by drivers.\n+ **/\n+s32 igc_init_hw(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.init_hw)\n+\t\treturn hw->mac.ops.init_hw(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_setup_link - Configures link and flow control\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This configures link and flow control settings for the adapter. This\n+ *  is a function pointer entry point called by drivers. While modules can\n+ *  also call this, they probably call their own version of this function.\n+ **/\n+s32 igc_setup_link(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.setup_link)\n+\t\treturn hw->mac.ops.setup_link(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_get_speed_and_duplex - Returns current speed and duplex\n+ *  @hw: pointer to the HW structure\n+ *  @speed: pointer to a 16-bit value to store the speed\n+ *  @duplex: pointer to a 16-bit value to store the duplex.\n+ *\n+ *  This returns the speed and duplex of the adapter in the two 'out'\n+ *  variables passed in. This is a function pointer entry point called\n+ *  by drivers.\n+ **/\n+s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex)\n+{\n+\tif (hw->mac.ops.get_link_up_info)\n+\t\treturn hw->mac.ops.get_link_up_info(hw, speed, duplex);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_setup_led - Configures SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This prepares the SW controllable LED for use and saves the current state\n+ *  of the LED so it can be later restored. This is a function pointer entry\n+ *  point called by drivers.\n+ **/\n+s32 igc_setup_led(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.setup_led)\n+\t\treturn hw->mac.ops.setup_led(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_cleanup_led - Restores SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This restores the SW controllable LED to the value saved off by\n+ *  igc_setup_led. This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_cleanup_led(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.cleanup_led)\n+\t\treturn hw->mac.ops.cleanup_led(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_blink_led - Blink SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This starts the adapter LED blinking. Request the LED to be setup first\n+ *  and cleaned up after. This is a function pointer entry point called by\n+ *  drivers.\n+ **/\n+s32 igc_blink_led(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.blink_led)\n+\t\treturn hw->mac.ops.blink_led(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_id_led_init - store LED configurations in SW\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Initializes the LED config in SW. This is a function pointer entry point\n+ *  called by drivers.\n+ **/\n+s32 igc_id_led_init(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.id_led_init)\n+\t\treturn hw->mac.ops.id_led_init(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_led_on - Turn on SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Turns the SW defined LED on. This is a function pointer entry point\n+ *  called by drivers.\n+ **/\n+s32 igc_led_on(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.led_on)\n+\t\treturn hw->mac.ops.led_on(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_led_off - Turn off SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Turns the SW defined LED off. This is a function pointer entry point\n+ *  called by drivers.\n+ **/\n+s32 igc_led_off(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.led_off)\n+\t\treturn hw->mac.ops.led_off(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_reset_adaptive - Reset adaptive IFS\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Resets the adaptive IFS. Currently no func pointer exists and all\n+ *  implementations are handled in the generic version of this function.\n+ **/\n+void igc_reset_adaptive(struct igc_hw *hw)\n+{\n+\tigc_reset_adaptive_generic(hw);\n+}\n+\n+/**\n+ *  igc_update_adaptive - Update adaptive IFS\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Updates adapter IFS. Currently no func pointer exists and all\n+ *  implementations are handled in the generic version of this function.\n+ **/\n+void igc_update_adaptive(struct igc_hw *hw)\n+{\n+\tigc_update_adaptive_generic(hw);\n+}\n+\n+/**\n+ *  igc_disable_pcie_master - Disable PCI-Express master access\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Disables PCI-Express master access and verifies there are no pending\n+ *  requests. Currently no func pointer exists and all implementations are\n+ *  handled in the generic version of this function.\n+ **/\n+s32 igc_disable_pcie_master(struct igc_hw *hw)\n+{\n+\treturn igc_disable_pcie_master_generic(hw);\n+}\n+\n+/**\n+ *  igc_config_collision_dist - Configure collision distance\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Configures the collision distance to the default value and is used\n+ *  during link setup.\n+ **/\n+void igc_config_collision_dist(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.config_collision_dist)\n+\t\thw->mac.ops.config_collision_dist(hw);\n+}\n+\n+/**\n+ *  igc_rar_set - Sets a receive address register\n+ *  @hw: pointer to the HW structure\n+ *  @addr: address to set the RAR to\n+ *  @index: the RAR to set\n+ *\n+ *  Sets a Receive Address Register (RAR) to the specified address.\n+ **/\n+int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)\n+{\n+\tif (hw->mac.ops.rar_set)\n+\t\treturn hw->mac.ops.rar_set(hw, addr, index);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_validate_mdi_setting - Ensures valid MDI/MDIX SW state\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Ensures that the MDI/MDIX SW state is valid.\n+ **/\n+s32 igc_validate_mdi_setting(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.validate_mdi_setting)\n+\t\treturn hw->mac.ops.validate_mdi_setting(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_hash_mc_addr - Determines address location in multicast table\n+ *  @hw: pointer to the HW structure\n+ *  @mc_addr: Multicast address to hash.\n+ *\n+ *  This hashes an address to determine its location in the multicast\n+ *  table. Currently no func pointer exists and all implementations\n+ *  are handled in the generic version of this function.\n+ **/\n+u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)\n+{\n+\treturn igc_hash_mc_addr_generic(hw, mc_addr);\n+}\n+\n+/**\n+ *  igc_enable_tx_pkt_filtering - Enable packet filtering on TX\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Enables packet filtering on transmit packets if manageability is enabled\n+ *  and host interface is enabled.\n+ *  Currently no func pointer exists and all implementations are handled in the\n+ *  generic version of this function.\n+ **/\n+bool igc_enable_tx_pkt_filtering(struct igc_hw *hw)\n+{\n+\treturn igc_enable_tx_pkt_filtering_generic(hw);\n+}\n+\n+/**\n+ *  igc_mng_host_if_write - Writes to the manageability host interface\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: pointer to the host interface buffer\n+ *  @length: size of the buffer\n+ *  @offset: location in the buffer to write to\n+ *  @sum: sum of the data (not checksum)\n+ *\n+ *  This function writes the buffer content at the offset given on the host if.\n+ *  It also does alignment considerations to do the writes in most efficient\n+ *  way.  Also fills up the sum of the buffer in *buffer parameter.\n+ **/\n+s32 igc_mng_host_if_write(struct igc_hw *hw, u8 *buffer, u16 length,\n+\t\t\t    u16 offset, u8 *sum)\n+{\n+\treturn igc_mng_host_if_write_generic(hw, buffer, length, offset, sum);\n+}\n+\n+/**\n+ *  igc_mng_write_cmd_header - Writes manageability command header\n+ *  @hw: pointer to the HW structure\n+ *  @hdr: pointer to the host interface command header\n+ *\n+ *  Writes the command header after does the checksum calculation.\n+ **/\n+s32 igc_mng_write_cmd_header(struct igc_hw *hw,\n+\t\t\t       struct igc_host_mng_command_header *hdr)\n+{\n+\treturn igc_mng_write_cmd_header_generic(hw, hdr);\n+}\n+\n+/**\n+ *  igc_mng_enable_host_if - Checks host interface is enabled\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Returns IGC_success upon success, else IGC_ERR_HOST_INTERFACE_COMMAND\n+ *\n+ *  This function checks whether the HOST IF is enabled for command operation\n+ *  and also checks whether the previous command is completed.  It busy waits\n+ *  in case of previous command is not completed.\n+ **/\n+s32 igc_mng_enable_host_if(struct igc_hw *hw)\n+{\n+\treturn igc_mng_enable_host_if_generic(hw);\n+}\n+\n+/**\n+ *  igc_check_reset_block - Verifies PHY can be reset\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks if the PHY is in a state that can be reset or if manageability\n+ *  has it tied up. This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_check_reset_block(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.check_reset_block)\n+\t\treturn hw->phy.ops.check_reset_block(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_phy_reg - Reads PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the register to read\n+ *  @data: the buffer to store the 16-bit read.\n+ *\n+ *  Reads the PHY register and returns the value in data.\n+ *  This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\tif (hw->phy.ops.read_reg)\n+\t\treturn hw->phy.ops.read_reg(hw, offset, data);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_phy_reg - Writes PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the register to write\n+ *  @data: the value to write.\n+ *\n+ *  Writes the PHY register at offset with the value in data.\n+ *  This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\tif (hw->phy.ops.write_reg)\n+\t\treturn hw->phy.ops.write_reg(hw, offset, data);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_release_phy - Generic release PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Return if silicon family does not require a semaphore when accessing the\n+ *  PHY.\n+ **/\n+void igc_release_phy(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.release)\n+\t\thw->phy.ops.release(hw);\n+}\n+\n+/**\n+ *  igc_acquire_phy - Generic acquire PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Return success if silicon family does not require a semaphore when\n+ *  accessing the PHY.\n+ **/\n+s32 igc_acquire_phy(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.acquire)\n+\t\treturn hw->phy.ops.acquire(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_cfg_on_link_up - Configure PHY upon link up\n+ *  @hw: pointer to the HW structure\n+ **/\n+s32 igc_cfg_on_link_up(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.cfg_on_link_up)\n+\t\treturn hw->phy.ops.cfg_on_link_up(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_kmrn_reg - Reads register using Kumeran interface\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the register to read\n+ *  @data: the location to store the 16-bit value read.\n+ *\n+ *  Reads a register out of the Kumeran interface. Currently no func pointer\n+ *  exists and all implementations are handled in the generic version of\n+ *  this function.\n+ **/\n+s32 igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn igc_read_kmrn_reg_generic(hw, offset, data);\n+}\n+\n+/**\n+ *  igc_write_kmrn_reg - Writes register using Kumeran interface\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the register to write\n+ *  @data: the value to write.\n+ *\n+ *  Writes a register to the Kumeran interface. Currently no func pointer\n+ *  exists and all implementations are handled in the generic version of\n+ *  this function.\n+ **/\n+s32 igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn igc_write_kmrn_reg_generic(hw, offset, data);\n+}\n+\n+/**\n+ *  igc_get_cable_length - Retrieves cable length estimation\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function estimates the cable length and stores them in\n+ *  hw->phy.min_length and hw->phy.max_length. This is a function pointer\n+ *  entry point called by drivers.\n+ **/\n+s32 igc_get_cable_length(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.get_cable_length)\n+\t\treturn hw->phy.ops.get_cable_length(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_phy_info - Retrieves PHY information from registers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function gets some information from various PHY registers and\n+ *  populates hw->phy values with it. This is a function pointer entry\n+ *  point called by drivers.\n+ **/\n+s32 igc_get_phy_info(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.get_info)\n+\t\treturn hw->phy.ops.get_info(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_hw_reset - Hard PHY reset\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Performs a hard PHY reset. This is a function pointer entry point called\n+ *  by drivers.\n+ **/\n+s32 igc_phy_hw_reset(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.reset)\n+\t\treturn hw->phy.ops.reset(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_commit - Soft PHY reset\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Performs a soft PHY reset on those that apply. This is a function pointer\n+ *  entry point called by drivers.\n+ **/\n+s32 igc_phy_commit(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.commit)\n+\t\treturn hw->phy.ops.commit(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_d0_lplu_state - Sets low power link up state for D0\n+ *  @hw: pointer to the HW structure\n+ *  @active: boolean used to enable/disable lplu\n+ *\n+ *  Success returns 0, Failure returns 1\n+ *\n+ *  The low power link up (lplu) state is set to the power management level D0\n+ *  and SmartSpeed is disabled when active is true, else clear lplu for D0\n+ *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU\n+ *  is used during Dx states where the power conservation is most important.\n+ *  During driver activity, SmartSpeed should be enabled so performance is\n+ *  maintained.  This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active)\n+{\n+\tif (hw->phy.ops.set_d0_lplu_state)\n+\t\treturn hw->phy.ops.set_d0_lplu_state(hw, active);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_d3_lplu_state - Sets low power link up state for D3\n+ *  @hw: pointer to the HW structure\n+ *  @active: boolean used to enable/disable lplu\n+ *\n+ *  Success returns 0, Failure returns 1\n+ *\n+ *  The low power link up (lplu) state is set to the power management level D3\n+ *  and SmartSpeed is disabled when active is true, else clear lplu for D3\n+ *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU\n+ *  is used during Dx states where the power conservation is most important.\n+ *  During driver activity, SmartSpeed should be enabled so performance is\n+ *  maintained.  This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active)\n+{\n+\tif (hw->phy.ops.set_d3_lplu_state)\n+\t\treturn hw->phy.ops.set_d3_lplu_state(hw, active);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_mac_addr - Reads MAC address\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the MAC address out of the adapter and stores it in the HW structure.\n+ *  Currently no func pointer exists and all implementations are handled in the\n+ *  generic version of this function.\n+ **/\n+s32 igc_read_mac_addr(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.read_mac_addr)\n+\t\treturn hw->mac.ops.read_mac_addr(hw);\n+\n+\treturn igc_read_mac_addr_generic(hw);\n+}\n+\n+/**\n+ *  igc_read_pba_string - Read device part number string\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num: pointer to device part number\n+ *  @pba_num_size: size of part number buffer\n+ *\n+ *  Reads the product board assembly (PBA) number from the EEPROM and stores\n+ *  the value in pba_num.\n+ *  Currently no func pointer exists and all implementations are handled in the\n+ *  generic version of this function.\n+ **/\n+s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size)\n+{\n+\treturn igc_read_pba_string_generic(hw, pba_num, pba_num_size);\n+}\n+\n+/**\n+ *  igc_read_pba_length - Read device part number string length\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num_size: size of part number buffer\n+ *\n+ *  Reads the product board assembly (PBA) number length from the EEPROM and\n+ *  stores the value in pba_num.\n+ *  Currently no func pointer exists and all implementations are handled in the\n+ *  generic version of this function.\n+ **/\n+s32 igc_read_pba_length(struct igc_hw *hw, u32 *pba_num_size)\n+{\n+\treturn igc_read_pba_length_generic(hw, pba_num_size);\n+}\n+\n+/**\n+ *  igc_read_pba_num - Read device part number\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num: pointer to device part number\n+ *\n+ *  Reads the product board assembly (PBA) number from the EEPROM and stores\n+ *  the value in pba_num.\n+ *  Currently no func pointer exists and all implementations are handled in the\n+ *  generic version of this function.\n+ **/\n+s32 igc_read_pba_num(struct igc_hw *hw, u32 *pba_num)\n+{\n+\treturn igc_read_pba_num_generic(hw, pba_num);\n+}\n+\n+/**\n+ *  igc_validate_nvm_checksum - Verifies NVM (EEPROM) checksum\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Validates the NVM checksum is correct. This is a function pointer entry\n+ *  point called by drivers.\n+ **/\n+s32 igc_validate_nvm_checksum(struct igc_hw *hw)\n+{\n+\tif (hw->nvm.ops.validate)\n+\t\treturn hw->nvm.ops.validate(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_update_nvm_checksum - Updates NVM (EEPROM) checksum\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Updates the NVM checksum. Currently no func pointer exists and all\n+ *  implementations are handled in the generic version of this function.\n+ **/\n+s32 igc_update_nvm_checksum(struct igc_hw *hw)\n+{\n+\tif (hw->nvm.ops.update)\n+\t\treturn hw->nvm.ops.update(hw);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_reload_nvm - Reloads EEPROM\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n+ *  extended control register.\n+ **/\n+void igc_reload_nvm(struct igc_hw *hw)\n+{\n+\tif (hw->nvm.ops.reload)\n+\t\thw->nvm.ops.reload(hw);\n+}\n+\n+/**\n+ *  igc_read_nvm - Reads NVM (EEPROM)\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the word offset to read\n+ *  @words: number of 16-bit words to read\n+ *  @data: pointer to the properly sized buffer for the data.\n+ *\n+ *  Reads 16-bit chunks of data from the NVM (EEPROM). This is a function\n+ *  pointer entry point called by drivers.\n+ **/\n+s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)\n+{\n+\tif (hw->nvm.ops.read)\n+\t\treturn hw->nvm.ops.read(hw, offset, words, data);\n+\n+\treturn -IGC_ERR_CONFIG;\n+}\n+\n+/**\n+ *  igc_write_nvm - Writes to NVM (EEPROM)\n+ *  @hw: pointer to the HW structure\n+ *  @offset: the word offset to read\n+ *  @words: number of 16-bit words to write\n+ *  @data: pointer to the properly sized buffer for the data.\n+ *\n+ *  Writes 16-bit chunks of data to the NVM (EEPROM). This is a function\n+ *  pointer entry point called by drivers.\n+ **/\n+s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)\n+{\n+\tif (hw->nvm.ops.write)\n+\t\treturn hw->nvm.ops.write(hw, offset, words, data);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_8bit_ctrl_reg - Writes 8bit Control register\n+ *  @hw: pointer to the HW structure\n+ *  @reg: 32bit register offset\n+ *  @offset: the register to write\n+ *  @data: the value to write.\n+ *\n+ *  Writes the PHY register at offset with the value in data.\n+ *  This is a function pointer entry point called by drivers.\n+ **/\n+s32 igc_write_8bit_ctrl_reg(struct igc_hw *hw, u32 reg, u32 offset,\n+\t\t\t      u8 data)\n+{\n+\treturn igc_write_8bit_ctrl_reg_generic(hw, reg, offset, data);\n+}\n+\n+/**\n+ * igc_power_up_phy - Restores link in case of PHY power down\n+ * @hw: pointer to the HW structure\n+ *\n+ * The phy may be powered down to save power, to turn off link when the\n+ * driver is unloaded, or wake on lan is not enabled (among others).\n+ **/\n+void igc_power_up_phy(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.power_up)\n+\t\thw->phy.ops.power_up(hw);\n+\n+\tigc_setup_link(hw);\n+}\n+\n+/**\n+ * igc_power_down_phy - Power down PHY\n+ * @hw: pointer to the HW structure\n+ *\n+ * The phy may be powered down to save power, to turn off link when the\n+ * driver is unloaded, or wake on lan is not enabled (among others).\n+ **/\n+void igc_power_down_phy(struct igc_hw *hw)\n+{\n+\tif (hw->phy.ops.power_down)\n+\t\thw->phy.ops.power_down(hw);\n+}\n+\n+/**\n+ *  igc_power_up_fiber_serdes_link - Power up serdes link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Power on the optics and PCS.\n+ **/\n+void igc_power_up_fiber_serdes_link(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.power_up_serdes)\n+\t\thw->mac.ops.power_up_serdes(hw);\n+}\n+\n+/**\n+ *  igc_shutdown_fiber_serdes_link - Remove link during power down\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Shutdown the optics and PCS on driver unload.\n+ **/\n+void igc_shutdown_fiber_serdes_link(struct igc_hw *hw)\n+{\n+\tif (hw->mac.ops.shutdown_serdes)\n+\t\thw->mac.ops.shutdown_serdes(hw);\n+}\ndiff --git a/drivers/net/igc/base/e1000_api.h b/drivers/net/igc/base/e1000_api.h\nnew file mode 100644\nindex 0000000..befb412\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_api.h\n@@ -0,0 +1,111 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_API_H_\n+#define _IGC_API_H_\n+\n+#include \"e1000_hw.h\"\n+\n+/* I2C SDA and SCL timing parameters for standard mode */\n+#define IGC_I2C_T_HD_STA\t4\n+#define IGC_I2C_T_LOW\t\t5\n+#define IGC_I2C_T_HIGH\t\t4\n+#define IGC_I2C_T_SU_STA\t5\n+#define IGC_I2C_T_HD_DATA\t5\n+#define IGC_I2C_T_SU_DATA\t1\n+#define IGC_I2C_T_RISE\t\t1\n+#define IGC_I2C_T_FALL\t\t1\n+#define IGC_I2C_T_SU_STO\t4\n+#define IGC_I2C_T_BUF\t\t5\n+\n+s32 igc_set_i2c_bb(struct igc_hw *hw);\n+s32 igc_read_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 dev_addr, u8 *data);\n+s32 igc_write_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t\t u8 dev_addr, u8 data);\n+void igc_i2c_bus_clear(struct igc_hw *hw);\n+\n+void igc_init_function_pointers_82542(struct igc_hw *hw);\n+void igc_init_function_pointers_82543(struct igc_hw *hw);\n+void igc_init_function_pointers_82540(struct igc_hw *hw);\n+void igc_init_function_pointers_82571(struct igc_hw *hw);\n+void igc_init_function_pointers_82541(struct igc_hw *hw);\n+void igc_init_function_pointers_80003es2lan(struct igc_hw *hw);\n+void igc_init_function_pointers_ich8lan(struct igc_hw *hw);\n+void igc_init_function_pointers_82575(struct igc_hw *hw);\n+void igc_init_function_pointers_vf(struct igc_hw *hw);\n+void igc_power_up_fiber_serdes_link(struct igc_hw *hw);\n+void igc_shutdown_fiber_serdes_link(struct igc_hw *hw);\n+void igc_init_function_pointers_i210(struct igc_hw *hw);\n+void igc_init_function_pointers_i225(struct igc_hw *hw);\n+\n+s32 igc_set_obff_timer(struct igc_hw *hw, u32 itr);\n+s32 igc_set_mac_type(struct igc_hw *hw);\n+s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device);\n+s32 igc_init_mac_params(struct igc_hw *hw);\n+s32 igc_init_nvm_params(struct igc_hw *hw);\n+s32 igc_init_phy_params(struct igc_hw *hw);\n+s32 igc_init_mbx_params(struct igc_hw *hw);\n+s32 igc_get_bus_info(struct igc_hw *hw);\n+void igc_clear_vfta(struct igc_hw *hw);\n+void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value);\n+s32 igc_force_mac_fc(struct igc_hw *hw);\n+s32 igc_check_for_link(struct igc_hw *hw);\n+s32 igc_reset_hw(struct igc_hw *hw);\n+s32 igc_init_hw(struct igc_hw *hw);\n+s32 igc_setup_link(struct igc_hw *hw);\n+s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex);\n+s32 igc_disable_pcie_master(struct igc_hw *hw);\n+void igc_config_collision_dist(struct igc_hw *hw);\n+int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index);\n+u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr);\n+void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,\n+\t\t\t       u32 mc_addr_count);\n+s32 igc_setup_led(struct igc_hw *hw);\n+s32 igc_cleanup_led(struct igc_hw *hw);\n+s32 igc_check_reset_block(struct igc_hw *hw);\n+s32 igc_blink_led(struct igc_hw *hw);\n+s32 igc_led_on(struct igc_hw *hw);\n+s32 igc_led_off(struct igc_hw *hw);\n+s32 igc_id_led_init(struct igc_hw *hw);\n+void igc_reset_adaptive(struct igc_hw *hw);\n+void igc_update_adaptive(struct igc_hw *hw);\n+s32 igc_get_cable_length(struct igc_hw *hw);\n+s32 igc_validate_mdi_setting(struct igc_hw *hw);\n+s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data);\n+s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data);\n+s32 igc_write_8bit_ctrl_reg(struct igc_hw *hw, u32 reg, u32 offset,\n+\t\t\t      u8 data);\n+s32 igc_get_phy_info(struct igc_hw *hw);\n+void igc_release_phy(struct igc_hw *hw);\n+s32 igc_acquire_phy(struct igc_hw *hw);\n+s32 igc_cfg_on_link_up(struct igc_hw *hw);\n+s32 igc_phy_hw_reset(struct igc_hw *hw);\n+s32 igc_phy_commit(struct igc_hw *hw);\n+void igc_power_up_phy(struct igc_hw *hw);\n+void igc_power_down_phy(struct igc_hw *hw);\n+s32 igc_read_mac_addr(struct igc_hw *hw);\n+s32 igc_read_pba_num(struct igc_hw *hw, u32 *part_num);\n+s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size);\n+s32 igc_read_pba_length(struct igc_hw *hw, u32 *pba_num_size);\n+void igc_reload_nvm(struct igc_hw *hw);\n+s32 igc_update_nvm_checksum(struct igc_hw *hw);\n+s32 igc_validate_nvm_checksum(struct igc_hw *hw);\n+s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);\n+s32 igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data);\n+s32 igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data);\n+s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data);\n+s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active);\n+s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active);\n+bool igc_check_mng_mode(struct igc_hw *hw);\n+bool igc_enable_tx_pkt_filtering(struct igc_hw *hw);\n+s32 igc_mng_enable_host_if(struct igc_hw *hw);\n+s32 igc_mng_host_if_write(struct igc_hw *hw, u8 *buffer, u16 length,\n+\t\t\t    u16 offset, u8 *sum);\n+s32 igc_mng_write_cmd_header(struct igc_hw *hw,\n+\t\t\t       struct igc_host_mng_command_header *hdr);\n+s32 igc_mng_write_dhcp_info(struct igc_hw *hw, u8 *buffer, u16 length);\n+u32  igc_translate_register_82542(u32 reg);\n+\n+#endif /* _IGC_API_H_ */\ndiff --git a/drivers/net/igc/base/e1000_base.c b/drivers/net/igc/base/e1000_base.c\nnew file mode 100644\nindex 0000000..a952fad\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_base.c\n@@ -0,0 +1,190 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_hw.h\"\n+#include \"e1000_i225.h\"\n+#include \"e1000_mac.h\"\n+#include \"e1000_base.h\"\n+#include \"e1000_manage.h\"\n+\n+/**\n+ *  igc_acquire_phy_base - Acquire rights to access PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Acquire access rights to the correct PHY.\n+ **/\n+s32 igc_acquire_phy_base(struct igc_hw *hw)\n+{\n+\tu16 mask = IGC_SWFW_PHY0_SM;\n+\n+\tDEBUGFUNC(\"igc_acquire_phy_base\");\n+\n+\tif (hw->bus.func == IGC_FUNC_1)\n+\t\tmask = IGC_SWFW_PHY1_SM;\n+\telse if (hw->bus.func == IGC_FUNC_2)\n+\t\tmask = IGC_SWFW_PHY2_SM;\n+\telse if (hw->bus.func == IGC_FUNC_3)\n+\t\tmask = IGC_SWFW_PHY3_SM;\n+\n+\treturn hw->mac.ops.acquire_swfw_sync(hw, mask);\n+}\n+\n+/**\n+ *  igc_release_phy_base - Release rights to access PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  A wrapper to release access rights to the correct PHY.\n+ **/\n+void igc_release_phy_base(struct igc_hw *hw)\n+{\n+\tu16 mask = IGC_SWFW_PHY0_SM;\n+\n+\tDEBUGFUNC(\"igc_release_phy_base\");\n+\n+\tif (hw->bus.func == IGC_FUNC_1)\n+\t\tmask = IGC_SWFW_PHY1_SM;\n+\telse if (hw->bus.func == IGC_FUNC_2)\n+\t\tmask = IGC_SWFW_PHY2_SM;\n+\telse if (hw->bus.func == IGC_FUNC_3)\n+\t\tmask = IGC_SWFW_PHY3_SM;\n+\n+\thw->mac.ops.release_swfw_sync(hw, mask);\n+}\n+\n+/**\n+ *  igc_init_hw_base - Initialize hardware\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This inits the hardware readying it for operation.\n+ **/\n+s32 igc_init_hw_base(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val;\n+\tu16 i, rar_count = mac->rar_entry_count;\n+\n+\tDEBUGFUNC(\"igc_init_hw_base\");\n+\n+\t/* Setup the receive address */\n+\tigc_init_rx_addrs_generic(hw, rar_count);\n+\n+\t/* Zero out the Multicast HASH table */\n+\tDEBUGOUT(\"Zeroing the MTA\\n\");\n+\tfor (i = 0; i < mac->mta_reg_count; i++)\n+\t\tIGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);\n+\n+\t/* Zero out the Unicast HASH table */\n+\tDEBUGOUT(\"Zeroing the UTA\\n\");\n+\tfor (i = 0; i < mac->uta_reg_count; i++)\n+\t\tIGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);\n+\n+\t/* Setup link and flow control */\n+\tret_val = mac->ops.setup_link(hw);\n+\t/*\n+\t * Clear all of the statistics registers (clear on read).  It is\n+\t * important that we do this after we have tried to establish link\n+\t * because the symbol error count will increment wildly if there\n+\t * is no link.\n+\t */\n+\tigc_clear_hw_cntrs_base_generic(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_power_down_phy_copper_base - Remove link during PHY power down\n+ * @hw: pointer to the HW structure\n+ *\n+ * In the case of a PHY power down to save power, or to turn off link during a\n+ * driver unload, or wake on lan is not enabled, remove the link.\n+ **/\n+void igc_power_down_phy_copper_base(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\n+\tif (!(phy->ops.check_reset_block))\n+\t\treturn;\n+\n+\t/* If the management interface is not enabled, then power down */\n+\tif (!phy->ops.check_reset_block(hw))\n+\t\tigc_power_down_phy_copper(hw);\n+}\n+\n+/**\n+ *  igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  After Rx enable, if manageability is enabled then there is likely some\n+ *  bad data at the start of the FIFO and possibly in the DMA FIFO.  This\n+ *  function clears the FIFOs and flushes any packets that came in as Rx was\n+ *  being enabled.\n+ **/\n+void igc_rx_fifo_flush_base(struct igc_hw *hw)\n+{\n+\tu32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;\n+\tint i, ms_wait;\n+\n+\tDEBUGFUNC(\"igc_rx_fifo_flush_base\");\n+\n+\t/* disable IPv6 options as per hardware errata */\n+\trfctl = IGC_READ_REG(hw, IGC_RFCTL);\n+\trfctl |= IGC_RFCTL_IPV6_EX_DIS;\n+\tIGC_WRITE_REG(hw, IGC_RFCTL, rfctl);\n+\n+\tif (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))\n+\t\treturn;\n+\n+\t/* Disable all Rx queues */\n+\tfor (i = 0; i < 4; i++) {\n+\t\trxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));\n+\t\tIGC_WRITE_REG(hw, IGC_RXDCTL(i),\n+\t\t\t\trxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);\n+\t}\n+\t/* Poll all queues to verify they have shut down */\n+\tfor (ms_wait = 0; ms_wait < 10; ms_wait++) {\n+\t\tmsec_delay(1);\n+\t\trx_enabled = 0;\n+\t\tfor (i = 0; i < 4; i++)\n+\t\t\trx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));\n+\t\tif (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ms_wait == 10)\n+\t\tDEBUGOUT(\"Queue disable timed out after 10ms\\n\");\n+\n+\t/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all\n+\t * incoming packets are rejected.  Set enable and wait 2ms so that\n+\t * any packet that was coming in as RCTL.EN was set is flushed\n+\t */\n+\tIGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);\n+\n+\trlpml = IGC_READ_REG(hw, IGC_RLPML);\n+\tIGC_WRITE_REG(hw, IGC_RLPML, 0);\n+\n+\trctl = IGC_READ_REG(hw, IGC_RCTL);\n+\ttemp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);\n+\ttemp_rctl |= IGC_RCTL_LPE;\n+\n+\tIGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);\n+\tIGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);\n+\tIGC_WRITE_FLUSH(hw);\n+\tmsec_delay(2);\n+\n+\t/* Enable Rx queues that were previously enabled and restore our\n+\t * previous state\n+\t */\n+\tfor (i = 0; i < 4; i++)\n+\t\tIGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);\n+\tIGC_WRITE_REG(hw, IGC_RCTL, rctl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tIGC_WRITE_REG(hw, IGC_RLPML, rlpml);\n+\tIGC_WRITE_REG(hw, IGC_RFCTL, rfctl);\n+\n+\t/* Flush receive errors generated by workaround */\n+\tIGC_READ_REG(hw, IGC_ROC);\n+\tIGC_READ_REG(hw, IGC_RNBC);\n+\tIGC_READ_REG(hw, IGC_MPC);\n+}\ndiff --git a/drivers/net/igc/base/e1000_base.h b/drivers/net/igc/base/e1000_base.h\nnew file mode 100644\nindex 0000000..2817a29\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_base.h\n@@ -0,0 +1,127 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_BASE_H_\n+#define _IGC_BASE_H_\n+\n+/* forward declaration */\n+s32 igc_init_hw_base(struct igc_hw *hw);\n+void igc_power_down_phy_copper_base(struct igc_hw *hw);\n+void igc_rx_fifo_flush_base(struct igc_hw *hw);\n+s32 igc_acquire_phy_base(struct igc_hw *hw);\n+void igc_release_phy_base(struct igc_hw *hw);\n+\n+/* Transmit Descriptor - Advanced */\n+union igc_adv_tx_desc {\n+\tstruct {\n+\t\t__le64 buffer_addr;    /* Address of descriptor's data buf */\n+\t\t__le32 cmd_type_len;\n+\t\t__le32 olinfo_status;\n+\t} read;\n+\tstruct {\n+\t\t__le64 rsvd;       /* Reserved */\n+\t\t__le32 nxtseq_seed;\n+\t\t__le32 status;\n+\t} wb;\n+};\n+\n+/* Context descriptors */\n+struct igc_adv_tx_context_desc {\n+\t__le32 vlan_macip_lens;\n+\tunion {\n+\t\t__le32 launch_time;\n+\t\t__le32 seqnum_seed;\n+\t} u;\n+\t__le32 type_tucmd_mlhl;\n+\t__le32 mss_l4len_idx;\n+};\n+\n+/* Adv Transmit Descriptor Config Masks */\n+#define IGC_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n+#define IGC_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n+#define IGC_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n+#define IGC_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n+#define IGC_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n+#define IGC_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n+#define IGC_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n+#define IGC_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n+#define IGC_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n+#define IGC_ADVTXD_MAC_LINKSEC\t0x00040000 /* Apply LinkSec on pkt */\n+#define IGC_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 Timestamp pkt */\n+#define IGC_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED prsnt in WB */\n+#define IGC_ADVTXD_IDX_SHIFT\t\t4  /* Adv desc Index shift */\n+#define IGC_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n+#define IGC_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n+#define IGC_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n+/* 1st & Last TSO-full iSCSI PDU*/\n+#define IGC_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n+#define IGC_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n+#define IGC_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n+\n+/* Advanced Transmit Context Descriptor Config */\n+#define IGC_ADVTXD_MACLEN_SHIFT\t9  /* Adv ctxt desc mac len shift */\n+#define IGC_ADVTXD_VLAN_SHIFT\t\t16  /* Adv ctxt vlan tag shift */\n+#define IGC_ADVTXD_TUCMD_IPV4\t\t0x00000400  /* IP Packet Type: 1=IPv4 */\n+#define IGC_ADVTXD_TUCMD_IPV6\t\t0x00000000  /* IP Packet Type: 0=IPv6 */\n+#define IGC_ADVTXD_TUCMD_L4T_UDP\t0x00000000  /* L4 Packet TYPE of UDP */\n+#define IGC_ADVTXD_TUCMD_L4T_TCP\t0x00000800  /* L4 Packet TYPE of TCP */\n+#define IGC_ADVTXD_TUCMD_L4T_SCTP\t0x00001000  /* L4 Packet TYPE of SCTP */\n+#define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP\t0x00002000 /* IPSec Type ESP */\n+/* IPSec Encrypt Enable for ESP */\n+#define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN\t0x00004000\n+/* Req requires Markers and CRC */\n+#define IGC_ADVTXD_TUCMD_MKRREQ\t0x00002000\n+#define IGC_ADVTXD_L4LEN_SHIFT\t8  /* Adv ctxt L4LEN shift */\n+#define IGC_ADVTXD_MSS_SHIFT\t\t16  /* Adv ctxt MSS shift */\n+/* Adv ctxt IPSec SA IDX mask */\n+#define IGC_ADVTXD_IPSEC_SA_INDEX_MASK\t0x000000FF\n+/* Adv ctxt IPSec ESP len mask */\n+#define IGC_ADVTXD_IPSEC_ESP_LEN_MASK\t\t0x000000FF\n+\n+#define IGC_RAR_ENTRIES_BASE\t\t16\n+\n+/* Receive Descriptor - Advanced */\n+union igc_adv_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tunion {\n+\t\t\t\t__le32 data;\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 pkt_info; /*RSS type, Pkt type*/\n+\t\t\t\t\t/* Split Header, header buffer len */\n+\t\t\t\t\t__le16 hdr_info;\n+\t\t\t\t} hs_rss;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 ip_id; /* IP id */\n+\t\t\t\t\t__le16 csum; /* Packet Checksum */\n+\t\t\t\t} csum_ip;\n+\t\t\t} hi_dword;\n+\t\t} lower;\n+\t\tstruct {\n+\t\t\t__le32 status_error; /* ext status/error */\n+\t\t\t__le16 length; /* Packet length */\n+\t\t\t__le16 vlan; /* VLAN tag */\n+\t\t} upper;\n+\t} wb;  /* writeback */\n+};\n+\n+/* Additional Transmit Descriptor Control definitions */\n+#define IGC_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n+\n+/* Additional Receive Descriptor Control definitions */\n+#define IGC_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n+\n+/* SRRCTL bit definitions */\n+#define IGC_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n+#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2  /* Shift _left_ */\n+#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n+\n+#endif /* _IGC_BASE_H_ */\ndiff --git a/drivers/net/igc/base/e1000_defines.h b/drivers/net/igc/base/e1000_defines.h\nnew file mode 100644\nindex 0000000..b9e2916\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_defines.h\n@@ -0,0 +1,1649 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_DEFINES_H_\n+#define _IGC_DEFINES_H_\n+\n+/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n+#define REQ_TX_DESCRIPTOR_MULTIPLE  8\n+#define REQ_RX_DESCRIPTOR_MULTIPLE  8\n+\n+/* Definitions for power management and wakeup registers */\n+/* Wake Up Control */\n+#define IGC_WUC_APME\t\t0x00000001 /* APM Enable */\n+#define IGC_WUC_PME_EN\t0x00000002 /* PME Enable */\n+#define IGC_WUC_PME_STATUS\t0x00000004 /* PME Status */\n+#define IGC_WUC_APMPME\t0x00000008 /* Assert PME on APM Wakeup */\n+#define IGC_WUC_PHY_WAKE\t0x00000100 /* if PHY supports wakeup */\n+\n+/* Wake Up Filter Control */\n+#define IGC_WUFC_LNKC\t0x00000001 /* Link Status Change Wakeup Enable */\n+#define IGC_WUFC_MAG\t0x00000002 /* Magic Packet Wakeup Enable */\n+#define IGC_WUFC_EX\t0x00000004 /* Directed Exact Wakeup Enable */\n+#define IGC_WUFC_MC\t0x00000008 /* Directed Multicast Wakeup Enable */\n+#define IGC_WUFC_BC\t0x00000010 /* Broadcast Wakeup Enable */\n+#define IGC_WUFC_ARP\t0x00000020 /* ARP Request Packet Wakeup Enable */\n+#define IGC_WUFC_IPV4\t0x00000040 /* Directed IPv4 Packet Wakeup Enable */\n+#define IGC_WUFC_FLX0\t\t0x00010000 /* Flexible Filter 0 Enable */\n+\n+/* Wake Up Status */\n+#define IGC_WUS_LNKC\t\tIGC_WUFC_LNKC\n+#define IGC_WUS_MAG\t\tIGC_WUFC_MAG\n+#define IGC_WUS_EX\t\tIGC_WUFC_EX\n+#define IGC_WUS_MC\t\tIGC_WUFC_MC\n+#define IGC_WUS_BC\t\tIGC_WUFC_BC\n+\n+/* Extended Device Control */\n+#define IGC_CTRL_EXT_LPCD\t\t0x00000004 /* LCD Power Cycle Done */\n+#define IGC_CTRL_EXT_SDP4_DATA\t0x00000010 /* SW Definable Pin 4 data */\n+#define IGC_CTRL_EXT_SDP6_DATA\t0x00000040 /* SW Definable Pin 6 data */\n+#define IGC_CTRL_EXT_SDP3_DATA\t0x00000080 /* SW Definable Pin 3 data */\n+/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */\n+#define IGC_CTRL_EXT_SDP4_DIR\t0x00000100 /* Direction of SDP4 0=in 1=out */\n+#define IGC_CTRL_EXT_SDP6_DIR\t0x00000400 /* Direction of SDP6 0=in 1=out */\n+#define IGC_CTRL_EXT_SDP3_DIR\t0x00000800 /* Direction of SDP3 0=in 1=out */\n+#define IGC_CTRL_EXT_FORCE_SMBUS\t0x00000800 /* Force SMBus mode */\n+#define IGC_CTRL_EXT_EE_RST\t0x00002000 /* Reinitialize from EEPROM */\n+/* Physical Func Reset Done Indication */\n+#define IGC_CTRL_EXT_PFRSTD\t0x00004000\n+#define IGC_CTRL_EXT_SDLPE\t0X00040000  /* SerDes Low Power Enable */\n+#define IGC_CTRL_EXT_SPD_BYPS\t0x00008000 /* Speed Select Bypass */\n+#define IGC_CTRL_EXT_RO_DIS\t0x00020000 /* Relaxed Ordering disable */\n+#define IGC_CTRL_EXT_DMA_DYN_CLK_EN\t0x00080000 /* DMA Dynamic Clk Gating */\n+#define IGC_CTRL_EXT_LINK_MODE_MASK\t0x00C00000\n+/* Offset of the link mode field in Ctrl Ext register */\n+#define IGC_CTRL_EXT_LINK_MODE_OFFSET\t22\n+#define IGC_CTRL_EXT_LINK_MODE_1000BASE_KX\t0x00400000\n+#define IGC_CTRL_EXT_LINK_MODE_GMII\t0x00000000\n+#define IGC_CTRL_EXT_LINK_MODE_PCIE_SERDES\t0x00C00000\n+#define IGC_CTRL_EXT_LINK_MODE_SGMII\t0x00800000\n+#define IGC_CTRL_EXT_EIAME\t\t0x01000000\n+#define IGC_CTRL_EXT_IRCA\t\t0x00000001\n+#define IGC_CTRL_EXT_DRV_LOAD\t\t0x10000000 /* Drv loaded bit for FW */\n+#define IGC_CTRL_EXT_IAME\t\t0x08000000 /* Int ACK Auto-mask */\n+#define IGC_CTRL_EXT_PBA_CLR\t\t0x80000000 /* PBA Clear */\n+#define IGC_CTRL_EXT_LSECCK\t\t0x00001000\n+#define IGC_CTRL_EXT_PHYPDEN\t\t0x00100000\n+#define IGC_I2CCMD_REG_ADDR_SHIFT\t16\n+#define IGC_I2CCMD_PHY_ADDR_SHIFT\t24\n+#define IGC_I2CCMD_OPCODE_READ\t0x08000000\n+#define IGC_I2CCMD_OPCODE_WRITE\t0x00000000\n+#define IGC_I2CCMD_READY\t\t0x20000000\n+#define IGC_I2CCMD_ERROR\t\t0x80000000\n+#define IGC_I2CCMD_SFP_DATA_ADDR(a)\t(0x0000 + (a))\n+#define IGC_I2CCMD_SFP_DIAG_ADDR(a)\t(0x0100 + (a))\n+#define IGC_MAX_SGMII_PHY_REG_ADDR\t255\n+#define IGC_I2CCMD_PHY_TIMEOUT\t200\n+#define IGC_IVAR_VALID\t0x80\n+#define IGC_GPIE_NSICR\t0x00000001\n+#define IGC_GPIE_MSIX_MODE\t0x00000010\n+#define IGC_GPIE_EIAME\t0x40000000\n+#define IGC_GPIE_PBA\t\t0x80000000\n+\n+/* Receive Descriptor bit definitions */\n+#define IGC_RXD_STAT_DD\t0x01    /* Descriptor Done */\n+#define IGC_RXD_STAT_EOP\t0x02    /* End of Packet */\n+#define IGC_RXD_STAT_IXSM\t0x04    /* Ignore checksum */\n+#define IGC_RXD_STAT_VP\t0x08    /* IEEE VLAN Packet */\n+#define IGC_RXD_STAT_UDPCS\t0x10    /* UDP xsum calculated */\n+#define IGC_RXD_STAT_TCPCS\t0x20    /* TCP xsum calculated */\n+#define IGC_RXD_STAT_IPCS\t0x40    /* IP xsum calculated */\n+#define IGC_RXD_STAT_PIF\t0x80    /* passed in-exact filter */\n+#define IGC_RXD_STAT_IPIDV\t0x200   /* IP identification valid */\n+#define IGC_RXD_STAT_UDPV\t0x400   /* Valid UDP checksum */\n+#define IGC_RXD_STAT_DYNINT\t0x800   /* Pkt caused INT via DYNINT */\n+#define IGC_RXD_ERR_CE\t0x01    /* CRC Error */\n+#define IGC_RXD_ERR_SE\t0x02    /* Symbol Error */\n+#define IGC_RXD_ERR_SEQ\t0x04    /* Sequence Error */\n+#define IGC_RXD_ERR_CXE\t0x10    /* Carrier Extension Error */\n+#define IGC_RXD_ERR_TCPE\t0x20    /* TCP/UDP Checksum Error */\n+#define IGC_RXD_ERR_IPE\t0x40    /* IP Checksum Error */\n+#define IGC_RXD_ERR_RXE\t0x80    /* Rx Data Error */\n+#define IGC_RXD_SPC_VLAN_MASK\t0x0FFF  /* VLAN ID is in lower 12 bits */\n+\n+#define IGC_RXDEXT_STATERR_TST\t0x00000100 /* Time Stamp taken */\n+#define IGC_RXDEXT_STATERR_LB\t\t0x00040000\n+#define IGC_RXDEXT_STATERR_CE\t\t0x01000000\n+#define IGC_RXDEXT_STATERR_SE\t\t0x02000000\n+#define IGC_RXDEXT_STATERR_SEQ\t0x04000000\n+#define IGC_RXDEXT_STATERR_CXE\t0x10000000\n+#define IGC_RXDEXT_STATERR_TCPE\t0x20000000\n+#define IGC_RXDEXT_STATERR_IPE\t0x40000000\n+#define IGC_RXDEXT_STATERR_RXE\t0x80000000\n+\n+/* mask to determine if packets should be dropped due to frame errors */\n+#define IGC_RXD_ERR_FRAME_ERR_MASK ( \\\n+\tIGC_RXD_ERR_CE  |\t\t\\\n+\tIGC_RXD_ERR_SE  |\t\t\\\n+\tIGC_RXD_ERR_SEQ |\t\t\\\n+\tIGC_RXD_ERR_CXE |\t\t\\\n+\tIGC_RXD_ERR_RXE)\n+\n+/* Same mask, but for extended and packet split descriptors */\n+#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \\\n+\tIGC_RXDEXT_STATERR_CE  |\t\\\n+\tIGC_RXDEXT_STATERR_SE  |\t\\\n+\tIGC_RXDEXT_STATERR_SEQ |\t\\\n+\tIGC_RXDEXT_STATERR_CXE |\t\\\n+\tIGC_RXDEXT_STATERR_RXE)\n+\n+#define IGC_MRQC_ENABLE_RSS_2Q\t\t0x00000001\n+#define IGC_MRQC_RSS_FIELD_MASK\t\t0xFFFF0000\n+#define IGC_MRQC_RSS_FIELD_IPV4_TCP\t\t0x00010000\n+#define IGC_MRQC_RSS_FIELD_IPV4\t\t0x00020000\n+#define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX\t0x00040000\n+#define IGC_MRQC_RSS_FIELD_IPV6\t\t0x00100000\n+#define IGC_MRQC_RSS_FIELD_IPV6_TCP\t\t0x00200000\n+\n+#define IGC_RXDPS_HDRSTAT_HDRSP\t\t0x00008000\n+\n+/* Management Control */\n+#define IGC_MANC_SMBUS_EN\t0x00000001 /* SMBus Enabled - RO */\n+#define IGC_MANC_ASF_EN\t0x00000002 /* ASF Enabled - RO */\n+#define IGC_MANC_ARP_EN\t0x00002000 /* Enable ARP Request Filtering */\n+#define IGC_MANC_RCV_TCO_EN\t0x00020000 /* Receive TCO Packets Enabled */\n+#define IGC_MANC_BLK_PHY_RST_ON_IDE\t0x00040000 /* Block phy resets */\n+/* Enable MAC address filtering */\n+#define IGC_MANC_EN_MAC_ADDR_FILTER\t0x00100000\n+/* Enable MNG packets to host memory */\n+#define IGC_MANC_EN_MNG2HOST\t\t0x00200000\n+\n+#define IGC_MANC2H_PORT_623\t\t0x00000020 /* Port 0x26f */\n+#define IGC_MANC2H_PORT_664\t\t0x00000040 /* Port 0x298 */\n+#define IGC_MDEF_PORT_623\t\t0x00000800 /* Port 0x26f */\n+#define IGC_MDEF_PORT_664\t\t0x00000400 /* Port 0x298 */\n+\n+/* Receive Control */\n+#define IGC_RCTL_RST\t\t0x00000001 /* Software reset */\n+#define IGC_RCTL_EN\t\t0x00000002 /* enable */\n+#define IGC_RCTL_SBP\t\t0x00000004 /* store bad packet */\n+#define IGC_RCTL_UPE\t\t0x00000008 /* unicast promisc enable */\n+#define IGC_RCTL_MPE\t\t0x00000010 /* multicast promisc enable */\n+#define IGC_RCTL_LPE\t\t0x00000020 /* long packet enable */\n+#define IGC_RCTL_LBM_NO\t0x00000000 /* no loopback mode */\n+#define IGC_RCTL_LBM_MAC\t0x00000040 /* MAC loopback mode */\n+#define IGC_RCTL_LBM_TCVR\t0x000000C0 /* tcvr loopback mode */\n+#define IGC_RCTL_DTYP_PS\t0x00000400 /* Packet Split descriptor */\n+#define IGC_RCTL_RDMTS_HALF\t0x00000000 /* Rx desc min thresh size */\n+#define IGC_RCTL_RDMTS_HEX\t0x00010000\n+#define IGC_RCTL_RDMTS1_HEX\tIGC_RCTL_RDMTS_HEX\n+#define IGC_RCTL_MO_SHIFT\t12 /* multicast offset shift */\n+#define IGC_RCTL_MO_3\t\t0x00003000 /* multicast offset 15:4 */\n+#define IGC_RCTL_BAM\t\t0x00008000 /* broadcast enable */\n+/* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */\n+#define IGC_RCTL_SZ_2048\t0x00000000 /* Rx buffer size 2048 */\n+#define IGC_RCTL_SZ_1024\t0x00010000 /* Rx buffer size 1024 */\n+#define IGC_RCTL_SZ_512\t0x00020000 /* Rx buffer size 512 */\n+#define IGC_RCTL_SZ_256\t0x00030000 /* Rx buffer size 256 */\n+/* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */\n+#define IGC_RCTL_SZ_16384\t0x00010000 /* Rx buffer size 16384 */\n+#define IGC_RCTL_SZ_8192\t0x00020000 /* Rx buffer size 8192 */\n+#define IGC_RCTL_SZ_4096\t0x00030000 /* Rx buffer size 4096 */\n+#define IGC_RCTL_VFE\t\t0x00040000 /* vlan filter enable */\n+#define IGC_RCTL_CFIEN\t0x00080000 /* canonical form enable */\n+#define IGC_RCTL_CFI\t\t0x00100000 /* canonical form indicator */\n+#define IGC_RCTL_DPF\t\t0x00400000 /* discard pause frames */\n+#define IGC_RCTL_PMCF\t\t0x00800000 /* pass MAC control frames */\n+#define IGC_RCTL_BSEX\t\t0x02000000 /* Buffer size extension */\n+#define IGC_RCTL_SECRC\t0x04000000 /* Strip Ethernet CRC */\n+\n+/* Use byte values for the following shift parameters\n+ * Usage:\n+ *     psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) &\n+ *\t\t  IGC_PSRCTL_BSIZE0_MASK) |\n+ *\t\t((ROUNDUP(value1, 1024) >> IGC_PSRCTL_BSIZE1_SHIFT) &\n+ *\t\t  IGC_PSRCTL_BSIZE1_MASK) |\n+ *\t\t((ROUNDUP(value2, 1024) << IGC_PSRCTL_BSIZE2_SHIFT) &\n+ *\t\t  IGC_PSRCTL_BSIZE2_MASK) |\n+ *\t\t((ROUNDUP(value3, 1024) << IGC_PSRCTL_BSIZE3_SHIFT) |;\n+ *\t\t  IGC_PSRCTL_BSIZE3_MASK))\n+ * where value0 = [128..16256],  default=256\n+ *       value1 = [1024..64512], default=4096\n+ *       value2 = [0..64512],    default=4096\n+ *       value3 = [0..64512],    default=0\n+ */\n+\n+#define IGC_PSRCTL_BSIZE0_MASK\t0x0000007F\n+#define IGC_PSRCTL_BSIZE1_MASK\t0x00003F00\n+#define IGC_PSRCTL_BSIZE2_MASK\t0x003F0000\n+#define IGC_PSRCTL_BSIZE3_MASK\t0x3F000000\n+\n+#define IGC_PSRCTL_BSIZE0_SHIFT\t7    /* Shift _right_ 7 */\n+#define IGC_PSRCTL_BSIZE1_SHIFT\t2    /* Shift _right_ 2 */\n+#define IGC_PSRCTL_BSIZE2_SHIFT\t6    /* Shift _left_ 6 */\n+#define IGC_PSRCTL_BSIZE3_SHIFT\t14   /* Shift _left_ 14 */\n+\n+/* SWFW_SYNC Definitions */\n+#define IGC_SWFW_EEP_SM\t0x01\n+#define IGC_SWFW_PHY0_SM\t0x02\n+#define IGC_SWFW_PHY1_SM\t0x04\n+#define IGC_SWFW_CSR_SM\t0x08\n+#define IGC_SWFW_PHY2_SM\t0x20\n+#define IGC_SWFW_PHY3_SM\t0x40\n+#define IGC_SWFW_SW_MNG_SM\t0x400\n+\n+/* Device Control */\n+#define IGC_CTRL_FD\t\t0x00000001  /* Full duplex.0=half; 1=full */\n+#define IGC_CTRL_PRIOR\t0x00000004  /* Priority on PCI. 0=rx,1=fair */\n+#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */\n+#define IGC_CTRL_LRST\t\t0x00000008  /* Link reset. 0=normal,1=reset */\n+#define IGC_CTRL_ASDE\t\t0x00000020  /* Auto-speed detect enable */\n+#define IGC_CTRL_SLU\t\t0x00000040  /* Set link up (Force Link) */\n+#define IGC_CTRL_ILOS\t\t0x00000080  /* Invert Loss-Of Signal */\n+#define IGC_CTRL_SPD_SEL\t0x00000300  /* Speed Select Mask */\n+#define IGC_CTRL_SPD_10\t0x00000000  /* Force 10Mb */\n+#define IGC_CTRL_SPD_100\t0x00000100  /* Force 100Mb */\n+#define IGC_CTRL_SPD_1000\t0x00000200  /* Force 1Gb */\n+#define IGC_CTRL_FRCSPD\t0x00000800  /* Force Speed */\n+#define IGC_CTRL_FRCDPX\t0x00001000  /* Force Duplex */\n+#define IGC_CTRL_LANPHYPC_OVERRIDE\t0x00010000 /* SW control of LANPHYPC */\n+#define IGC_CTRL_LANPHYPC_VALUE\t0x00020000 /* SW value of LANPHYPC */\n+#define IGC_CTRL_MEHE\t\t0x00080000 /* Memory Error Handling Enable */\n+#define IGC_CTRL_SWDPIN0\t0x00040000 /* SWDPIN 0 value */\n+#define IGC_CTRL_SWDPIN1\t0x00080000 /* SWDPIN 1 value */\n+#define IGC_CTRL_SWDPIN2\t0x00100000 /* SWDPIN 2 value */\n+#define IGC_CTRL_ADVD3WUC\t0x00100000 /* D3 WUC */\n+#define IGC_CTRL_EN_PHY_PWR_MGMT\t0x00200000 /* PHY PM enable */\n+#define IGC_CTRL_SWDPIN3\t0x00200000 /* SWDPIN 3 value */\n+#define IGC_CTRL_SWDPIO0\t0x00400000 /* SWDPIN 0 Input or output */\n+#define IGC_CTRL_SWDPIO2\t0x01000000 /* SWDPIN 2 input or output */\n+#define IGC_CTRL_SWDPIO3\t0x02000000 /* SWDPIN 3 input or output */\n+#define IGC_CTRL_DEV_RST\t0x20000000 /* Device reset */\n+#define IGC_CTRL_RST\t\t0x04000000 /* Global reset */\n+#define IGC_CTRL_RFCE\t\t0x08000000 /* Receive Flow Control enable */\n+#define IGC_CTRL_TFCE\t\t0x10000000 /* Transmit flow control enable */\n+#define IGC_CTRL_VME\t\t0x40000000 /* IEEE VLAN mode enable */\n+#define IGC_CTRL_PHY_RST\t0x80000000 /* PHY Reset */\n+#define IGC_CTRL_I2C_ENA\t0x02000000 /* I2C enable */\n+\n+#define IGC_CTRL_MDIO_DIR\t\tIGC_CTRL_SWDPIO2\n+#define IGC_CTRL_MDIO\t\t\tIGC_CTRL_SWDPIN2\n+#define IGC_CTRL_MDC_DIR\t\tIGC_CTRL_SWDPIO3\n+#define IGC_CTRL_MDC\t\t\tIGC_CTRL_SWDPIN3\n+\n+#define IGC_CONNSW_AUTOSENSE_EN\t0x1\n+#define IGC_CONNSW_ENRGSRC\t\t0x4\n+#define IGC_CONNSW_PHYSD\t\t0x400\n+#define IGC_CONNSW_PHY_PDN\t\t0x800\n+#define IGC_CONNSW_SERDESD\t\t0x200\n+#define IGC_CONNSW_AUTOSENSE_CONF\t0x2\n+#define IGC_PCS_CFG_PCS_EN\t\t8\n+#define IGC_PCS_LCTL_FLV_LINK_UP\t1\n+#define IGC_PCS_LCTL_FSV_10\t\t0\n+#define IGC_PCS_LCTL_FSV_100\t\t2\n+#define IGC_PCS_LCTL_FSV_1000\t\t4\n+#define IGC_PCS_LCTL_FDV_FULL\t\t8\n+#define IGC_PCS_LCTL_FSD\t\t0x10\n+#define IGC_PCS_LCTL_FORCE_LINK\t0x20\n+#define IGC_PCS_LCTL_FORCE_FCTRL\t0x80\n+#define IGC_PCS_LCTL_AN_ENABLE\t0x10000\n+#define IGC_PCS_LCTL_AN_RESTART\t0x20000\n+#define IGC_PCS_LCTL_AN_TIMEOUT\t0x40000\n+#define IGC_ENABLE_SERDES_LOOPBACK\t0x0410\n+\n+#define IGC_PCS_LSTS_LINK_OK\t\t1\n+#define IGC_PCS_LSTS_SPEED_100\t2\n+#define IGC_PCS_LSTS_SPEED_1000\t4\n+#define IGC_PCS_LSTS_DUPLEX_FULL\t8\n+#define IGC_PCS_LSTS_SYNK_OK\t\t0x10\n+#define IGC_PCS_LSTS_AN_COMPLETE\t0x10000\n+\n+/* Device Status */\n+#define IGC_STATUS_FD\t\t\t0x00000001 /* Duplex 0=half 1=full */\n+#define IGC_STATUS_LU\t\t\t0x00000002 /* Link up.0=no,1=link */\n+#define IGC_STATUS_FUNC_MASK\t\t0x0000000C /* PCI Function Mask */\n+#define IGC_STATUS_FUNC_SHIFT\t\t2\n+#define IGC_STATUS_FUNC_1\t\t0x00000004 /* Function 1 */\n+#define IGC_STATUS_TXOFF\t\t0x00000010 /* transmission paused */\n+#define IGC_STATUS_SPEED_MASK\t0x000000C0\n+#define IGC_STATUS_SPEED_10\t\t0x00000000 /* Speed 10Mb/s */\n+#define IGC_STATUS_SPEED_100\t\t0x00000040 /* Speed 100Mb/s */\n+#define IGC_STATUS_SPEED_1000\t\t0x00000080 /* Speed 1000Mb/s */\n+/* Speed 2.5Gb/s indication for I225 */\n+#define IGC_STATUS_SPEED_2500\t\t0x00400000\n+#define IGC_STATUS_LAN_INIT_DONE\t0x00000200 /* Lan Init Compltn by NVM */\n+#define IGC_STATUS_PHYRA\t\t0x00000400 /* PHY Reset Asserted */\n+#define IGC_STATUS_GIO_MASTER_ENABLE\t0x00080000 /* Master request status */\n+#define IGC_STATUS_PCI66\t\t0x00000800 /* In 66Mhz slot */\n+#define IGC_STATUS_BUS64\t\t0x00001000 /* In 64 bit slot */\n+#define IGC_STATUS_2P5_SKU\t\t0x00001000 /* Val of 2.5GBE SKU strap */\n+#define IGC_STATUS_2P5_SKU_OVER\t0x00002000 /* Val of 2.5GBE SKU Over */\n+#define IGC_STATUS_PCIX_MODE\t\t0x00002000 /* PCI-X mode */\n+#define IGC_STATUS_PCIX_SPEED\t\t0x0000C000 /* PCI-X bus speed */\n+\n+/* Constants used to interpret the masked PCI-X bus speed. */\n+#define IGC_STATUS_PCIX_SPEED_66\t0x00000000 /* PCI-X bus spd 50-66MHz */\n+#define IGC_STATUS_PCIX_SPEED_100\t0x00004000 /* PCI-X bus spd 66-100MHz */\n+#define IGC_STATUS_PCIX_SPEED_133\t0x00008000 /* PCI-X bus spd 100-133MHz*/\n+#define IGC_STATUS_PCIM_STATE\t\t0x40000000 /* PCIm function state */\n+\n+#define SPEED_10\t10\n+#define SPEED_100\t100\n+#define SPEED_1000\t1000\n+#define SPEED_2500\t2500\n+#define HALF_DUPLEX\t1\n+#define FULL_DUPLEX\t2\n+\n+#define PHY_FORCE_TIME\t20\n+\n+#define ADVERTISE_10_HALF\t\t0x0001\n+#define ADVERTISE_10_FULL\t\t0x0002\n+#define ADVERTISE_100_HALF\t\t0x0004\n+#define ADVERTISE_100_FULL\t\t0x0008\n+#define ADVERTISE_1000_HALF\t\t0x0010 /* Not used, just FYI */\n+#define ADVERTISE_1000_FULL\t\t0x0020\n+#define ADVERTISE_2500_HALF\t\t0x0040 /* NOT used, just FYI */\n+#define ADVERTISE_2500_FULL\t\t0x0080\n+\n+/* 1000/H is not supported, nor spec-compliant. */\n+#define IGC_ALL_SPEED_DUPLEX\t( \\\n+\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n+\tADVERTISE_100_FULL | ADVERTISE_1000_FULL)\n+#define IGC_ALL_SPEED_DUPLEX_2500 ( \\\n+\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n+\tADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)\n+#define IGC_ALL_NOT_GIG\t( \\\n+\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n+\tADVERTISE_100_FULL)\n+#define IGC_ALL_100_SPEED\t(ADVERTISE_100_HALF | ADVERTISE_100_FULL)\n+#define IGC_ALL_10_SPEED\t(ADVERTISE_10_HALF | ADVERTISE_10_FULL)\n+#define IGC_ALL_HALF_DUPLEX\t(ADVERTISE_10_HALF | ADVERTISE_100_HALF)\n+\n+#define AUTONEG_ADVERTISE_SPEED_DEFAULT\t\tIGC_ALL_SPEED_DUPLEX\n+#define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500\tIGC_ALL_SPEED_DUPLEX_2500\n+\n+/* LED Control */\n+#define IGC_PHY_LED0_MODE_MASK\t0x00000007\n+#define IGC_PHY_LED0_IVRT\t\t0x00000008\n+#define IGC_PHY_LED0_MASK\t\t0x0000001F\n+\n+#define IGC_LEDCTL_LED0_MODE_MASK\t0x0000000F\n+#define IGC_LEDCTL_LED0_MODE_SHIFT\t0\n+#define IGC_LEDCTL_LED0_IVRT\t\t0x00000040\n+#define IGC_LEDCTL_LED0_BLINK\t\t0x00000080\n+\n+#define IGC_LEDCTL_MODE_LINK_UP\t0x2\n+#define IGC_LEDCTL_MODE_LED_ON\t0xE\n+#define IGC_LEDCTL_MODE_LED_OFF\t0xF\n+\n+/* Transmit Descriptor bit definitions */\n+#define IGC_TXD_DTYP_D\t0x00100000 /* Data Descriptor */\n+#define IGC_TXD_DTYP_C\t0x00000000 /* Context Descriptor */\n+#define IGC_TXD_POPTS_IXSM\t0x01       /* Insert IP checksum */\n+#define IGC_TXD_POPTS_TXSM\t0x02       /* Insert TCP/UDP checksum */\n+#define IGC_TXD_CMD_EOP\t0x01000000 /* End of Packet */\n+#define IGC_TXD_CMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n+#define IGC_TXD_CMD_IC\t0x04000000 /* Insert Checksum */\n+#define IGC_TXD_CMD_RS\t0x08000000 /* Report Status */\n+#define IGC_TXD_CMD_RPS\t0x10000000 /* Report Packet Sent */\n+#define IGC_TXD_CMD_DEXT\t0x20000000 /* Desc extension (0 = legacy) */\n+#define IGC_TXD_CMD_VLE\t0x40000000 /* Add VLAN tag */\n+#define IGC_TXD_CMD_IDE\t0x80000000 /* Enable Tidv register */\n+#define IGC_TXD_STAT_DD\t0x00000001 /* Descriptor Done */\n+#define IGC_TXD_STAT_EC\t0x00000002 /* Excess Collisions */\n+#define IGC_TXD_STAT_LC\t0x00000004 /* Late Collisions */\n+#define IGC_TXD_STAT_TU\t0x00000008 /* Transmit underrun */\n+#define IGC_TXD_CMD_TCP\t0x01000000 /* TCP packet */\n+#define IGC_TXD_CMD_IP\t0x02000000 /* IP packet */\n+#define IGC_TXD_CMD_TSE\t0x04000000 /* TCP Seg enable */\n+#define IGC_TXD_STAT_TC\t0x00000004 /* Tx Underrun */\n+#define IGC_TXD_EXTCMD_TSTAMP\t0x00000010 /* IEEE1588 Timestamp packet */\n+\n+/* Transmit Control */\n+#define IGC_TCTL_EN\t\t0x00000002 /* enable Tx */\n+#define IGC_TCTL_PSP\t\t0x00000008 /* pad short packets */\n+#define IGC_TCTL_CT\t\t0x00000ff0 /* collision threshold */\n+#define IGC_TCTL_COLD\t\t0x003ff000 /* collision distance */\n+#define IGC_TCTL_RTLC\t\t0x01000000 /* Re-transmit on late collision */\n+#define IGC_TCTL_MULR\t\t0x10000000 /* Multiple request support */\n+\n+/* Transmit Arbitration Count */\n+#define IGC_TARC0_ENABLE\t0x00000400 /* Enable Tx Queue 0 */\n+\n+/* SerDes Control */\n+#define IGC_SCTL_DISABLE_SERDES_LOOPBACK\t0x0400\n+#define IGC_SCTL_ENABLE_SERDES_LOOPBACK\t0x0410\n+\n+/* Receive Checksum Control */\n+#define IGC_RXCSUM_IPOFL\t0x00000100 /* IPv4 checksum offload */\n+#define IGC_RXCSUM_TUOFL\t0x00000200 /* TCP / UDP checksum offload */\n+#define IGC_RXCSUM_CRCOFL\t0x00000800 /* CRC32 offload enable */\n+#define IGC_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n+#define IGC_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n+\n+/* GPY211 - I225 defines */\n+#define GPY_MMD_MASK\t\t0xFFFF0000\n+#define GPY_MMD_SHIFT\t\t16\n+#define GPY_REG_MASK\t\t0x0000FFFF\n+/* Header split receive */\n+#define IGC_RFCTL_NFSW_DIS\t\t0x00000040\n+#define IGC_RFCTL_NFSR_DIS\t\t0x00000080\n+#define IGC_RFCTL_ACK_DIS\t\t0x00001000\n+#define IGC_RFCTL_EXTEN\t\t0x00008000\n+#define IGC_RFCTL_IPV6_EX_DIS\t\t0x00010000\n+#define IGC_RFCTL_NEW_IPV6_EXT_DIS\t0x00020000\n+#define IGC_RFCTL_LEF\t\t\t0x00040000\n+\n+/* Collision related configuration parameters */\n+#define IGC_CT_SHIFT\t\t\t4\n+#define IGC_COLLISION_THRESHOLD\t15\n+#define IGC_COLLISION_DISTANCE\t63\n+#define IGC_COLD_SHIFT\t\t12\n+\n+/* Default values for the transmit IPG register */\n+#define DEFAULT_82542_TIPG_IPGT\t\t10\n+#define DEFAULT_82543_TIPG_IPGT_FIBER\t9\n+#define DEFAULT_82543_TIPG_IPGT_COPPER\t8\n+\n+#define IGC_TIPG_IPGT_MASK\t\t0x000003FF\n+\n+#define DEFAULT_82542_TIPG_IPGR1\t2\n+#define DEFAULT_82543_TIPG_IPGR1\t8\n+#define IGC_TIPG_IPGR1_SHIFT\t\t10\n+\n+#define DEFAULT_82542_TIPG_IPGR2\t10\n+#define DEFAULT_82543_TIPG_IPGR2\t6\n+#define DEFAULT_80003ES2LAN_TIPG_IPGR2\t7\n+#define IGC_TIPG_IPGR2_SHIFT\t\t20\n+\n+/* Ethertype field values */\n+#define ETHERNET_IEEE_VLAN_TYPE\t\t0x8100  /* 802.3ac packet */\n+\n+#define ETHERNET_FCS_SIZE\t\t4\n+#define MAX_JUMBO_FRAME_SIZE\t\t0x3F00\n+/* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */\n+#define MAX_RX_JUMBO_FRAME_SIZE\t\t0x2600\n+#define IGC_TX_PTR_GAP\t\t0x1F\n+\n+/* Extended Configuration Control and Size */\n+#define IGC_EXTCNF_CTRL_MDIO_SW_OWNERSHIP\t0x00000020\n+#define IGC_EXTCNF_CTRL_LCD_WRITE_ENABLE\t0x00000001\n+#define IGC_EXTCNF_CTRL_OEM_WRITE_ENABLE\t0x00000008\n+#define IGC_EXTCNF_CTRL_SWFLAG\t\t0x00000020\n+#define IGC_EXTCNF_CTRL_GATE_PHY_CFG\t\t0x00000080\n+#define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK\t0x00FF0000\n+#define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT\t16\n+#define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_MASK\t0x0FFF0000\n+#define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT\t16\n+\n+#define IGC_PHY_CTRL_D0A_LPLU\t\t\t0x00000002\n+#define IGC_PHY_CTRL_NOND0A_LPLU\t\t0x00000004\n+#define IGC_PHY_CTRL_NOND0A_GBE_DISABLE\t0x00000008\n+#define IGC_PHY_CTRL_GBE_DISABLE\t\t0x00000040\n+\n+#define IGC_KABGTXD_BGSQLBIAS\t\t\t0x00050000\n+\n+/* Low Power IDLE Control */\n+#define IGC_LPIC_LPIET_SHIFT\t\t24\t/* Low Power Idle Entry Time */\n+\n+/* PBA constants */\n+#define IGC_PBA_8K\t\t0x0008    /* 8KB */\n+#define IGC_PBA_10K\t\t0x000A    /* 10KB */\n+#define IGC_PBA_12K\t\t0x000C    /* 12KB */\n+#define IGC_PBA_14K\t\t0x000E    /* 14KB */\n+#define IGC_PBA_16K\t\t0x0010    /* 16KB */\n+#define IGC_PBA_18K\t\t0x0012\n+#define IGC_PBA_20K\t\t0x0014\n+#define IGC_PBA_22K\t\t0x0016\n+#define IGC_PBA_24K\t\t0x0018\n+#define IGC_PBA_26K\t\t0x001A\n+#define IGC_PBA_30K\t\t0x001E\n+#define IGC_PBA_32K\t\t0x0020\n+#define IGC_PBA_34K\t\t0x0022\n+#define IGC_PBA_35K\t\t0x0023\n+#define IGC_PBA_38K\t\t0x0026\n+#define IGC_PBA_40K\t\t0x0028\n+#define IGC_PBA_48K\t\t0x0030    /* 48KB */\n+#define IGC_PBA_64K\t\t0x0040    /* 64KB */\n+\n+#define IGC_PBA_RXA_MASK\t0xFFFF\n+\n+#define IGC_PBS_16K\t\tIGC_PBA_16K\n+\n+/* Uncorrectable/correctable ECC Error counts and enable bits */\n+#define IGC_PBECCSTS_CORR_ERR_CNT_MASK\t0x000000FF\n+#define IGC_PBECCSTS_UNCORR_ERR_CNT_MASK\t0x0000FF00\n+#define IGC_PBECCSTS_UNCORR_ERR_CNT_SHIFT\t8\n+#define IGC_PBECCSTS_ECC_ENABLE\t\t0x00010000\n+\n+#define IFS_MAX\t\t\t80\n+#define IFS_MIN\t\t\t40\n+#define IFS_RATIO\t\t4\n+#define IFS_STEP\t\t10\n+#define MIN_NUM_XMITS\t\t1000\n+\n+/* SW Semaphore Register */\n+#define IGC_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n+#define IGC_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n+#define IGC_SWSM_DRV_LOAD\t0x00000008 /* Driver Loaded Bit */\n+\n+#define IGC_SWSM2_LOCK\t0x00000002 /* Secondary driver semaphore bit */\n+\n+/* Interrupt Cause Read */\n+#define IGC_ICR_TXDW\t\t0x00000001 /* Transmit desc written back */\n+#define IGC_ICR_TXQE\t\t0x00000002 /* Transmit Queue empty */\n+#define IGC_ICR_LSC\t\t0x00000004 /* Link Status Change */\n+#define IGC_ICR_RXSEQ\t\t0x00000008 /* Rx sequence error */\n+#define IGC_ICR_RXDMT0\t0x00000010 /* Rx desc min. threshold (0) */\n+#define IGC_ICR_RXO\t\t0x00000040 /* Rx overrun */\n+#define IGC_ICR_RXT0\t\t0x00000080 /* Rx timer intr (ring 0) */\n+#define IGC_ICR_VMMB\t\t0x00000100 /* VM MB event */\n+#define IGC_ICR_RXCFG\t\t0x00000400 /* Rx /c/ ordered set */\n+#define IGC_ICR_GPI_EN0\t0x00000800 /* GP Int 0 */\n+#define IGC_ICR_GPI_EN1\t0x00001000 /* GP Int 1 */\n+#define IGC_ICR_GPI_EN2\t0x00002000 /* GP Int 2 */\n+#define IGC_ICR_GPI_EN3\t0x00004000 /* GP Int 3 */\n+#define IGC_ICR_TXD_LOW\t0x00008000\n+#define IGC_ICR_MNG\t\t0x00040000 /* Manageability event */\n+#define IGC_ICR_ECCER\t\t0x00400000 /* Uncorrectable ECC Error */\n+#define IGC_ICR_TS\t\t0x00080000 /* Time Sync Interrupt */\n+#define IGC_ICR_DRSTA\t\t0x40000000 /* Device Reset Asserted */\n+/* If this bit asserted, the driver should claim the interrupt */\n+#define IGC_ICR_INT_ASSERTED\t0x80000000\n+#define IGC_ICR_DOUTSYNC\t0x10000000 /* NIC DMA out of sync */\n+#define IGC_ICR_RXQ0\t\t0x00100000 /* Rx Queue 0 Interrupt */\n+#define IGC_ICR_RXQ1\t\t0x00200000 /* Rx Queue 1 Interrupt */\n+#define IGC_ICR_TXQ0\t\t0x00400000 /* Tx Queue 0 Interrupt */\n+#define IGC_ICR_TXQ1\t\t0x00800000 /* Tx Queue 1 Interrupt */\n+#define IGC_ICR_OTHER\t\t0x01000000 /* Other Interrupts */\n+#define IGC_ICR_FER\t\t0x00400000 /* Fatal Error */\n+\n+#define IGC_ICR_THS\t\t0x00800000 /* ICR.THS: Thermal Sensor Event*/\n+#define IGC_ICR_MDDET\t\t0x10000000 /* Malicious Driver Detect */\n+\n+/* PBA ECC Register */\n+#define IGC_PBA_ECC_COUNTER_MASK\t0xFFF00000 /* ECC counter mask */\n+#define IGC_PBA_ECC_COUNTER_SHIFT\t20 /* ECC counter shift value */\n+#define IGC_PBA_ECC_CORR_EN\t0x00000001 /* Enable ECC error correction */\n+#define IGC_PBA_ECC_STAT_CLR\t0x00000002 /* Clear ECC error counter */\n+#define IGC_PBA_ECC_INT_EN\t0x00000004 /* Enable ICR bit 5 on ECC error */\n+\n+/* Extended Interrupt Cause Read */\n+#define IGC_EICR_RX_QUEUE0\t0x00000001 /* Rx Queue 0 Interrupt */\n+#define IGC_EICR_RX_QUEUE1\t0x00000002 /* Rx Queue 1 Interrupt */\n+#define IGC_EICR_RX_QUEUE2\t0x00000004 /* Rx Queue 2 Interrupt */\n+#define IGC_EICR_RX_QUEUE3\t0x00000008 /* Rx Queue 3 Interrupt */\n+#define IGC_EICR_TX_QUEUE0\t0x00000100 /* Tx Queue 0 Interrupt */\n+#define IGC_EICR_TX_QUEUE1\t0x00000200 /* Tx Queue 1 Interrupt */\n+#define IGC_EICR_TX_QUEUE2\t0x00000400 /* Tx Queue 2 Interrupt */\n+#define IGC_EICR_TX_QUEUE3\t0x00000800 /* Tx Queue 3 Interrupt */\n+#define IGC_EICR_TCP_TIMER\t0x40000000 /* TCP Timer */\n+#define IGC_EICR_OTHER\t0x80000000 /* Interrupt Cause Active */\n+/* TCP Timer */\n+#define IGC_TCPTIMER_KS\t0x00000100 /* KickStart */\n+#define IGC_TCPTIMER_COUNT_ENABLE\t0x00000200 /* Count Enable */\n+#define IGC_TCPTIMER_COUNT_FINISH\t0x00000400 /* Count finish */\n+#define IGC_TCPTIMER_LOOP\t0x00000800 /* Loop */\n+\n+/* This defines the bits that are set in the Interrupt Mask\n+ * Set/Read Register.  Each bit is documented below:\n+ *   o RXT0   = Receiver Timer Interrupt (ring 0)\n+ *   o TXDW   = Transmit Descriptor Written Back\n+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)\n+ *   o RXSEQ  = Receive Sequence Error\n+ *   o LSC    = Link Status Change\n+ */\n+#define IMS_ENABLE_MASK ( \\\n+\tIGC_IMS_RXT0   |    \\\n+\tIGC_IMS_TXDW   |    \\\n+\tIGC_IMS_RXDMT0 |    \\\n+\tIGC_IMS_RXSEQ  |    \\\n+\tIGC_IMS_LSC)\n+\n+/* Interrupt Mask Set */\n+#define IGC_IMS_TXDW\t\tIGC_ICR_TXDW    /* Tx desc written back */\n+#define IGC_IMS_TXQE\t\tIGC_ICR_TXQE    /* Transmit Queue empty */\n+#define IGC_IMS_LSC\t\tIGC_ICR_LSC     /* Link Status Change */\n+#define IGC_IMS_VMMB\t\tIGC_ICR_VMMB    /* Mail box activity */\n+#define IGC_IMS_RXSEQ\t\tIGC_ICR_RXSEQ   /* Rx sequence error */\n+#define IGC_IMS_RXDMT0\tIGC_ICR_RXDMT0  /* Rx desc min. threshold */\n+#define IGC_QVECTOR_MASK\t0x7FFC\t\t/* Q-vector mask */\n+#define IGC_ITR_VAL_MASK\t0x04\t\t/* ITR value mask */\n+#define IGC_IMS_RXO\t\tIGC_ICR_RXO     /* Rx overrun */\n+#define IGC_IMS_RXT0\t\tIGC_ICR_RXT0    /* Rx timer intr */\n+#define IGC_IMS_TXD_LOW\tIGC_ICR_TXD_LOW\n+#define IGC_IMS_ECCER\t\tIGC_ICR_ECCER   /* Uncorrectable ECC Error */\n+#define IGC_IMS_TS\t\tIGC_ICR_TS      /* Time Sync Interrupt */\n+#define IGC_IMS_DRSTA\t\tIGC_ICR_DRSTA   /* Device Reset Asserted */\n+#define IGC_IMS_DOUTSYNC\tIGC_ICR_DOUTSYNC /* NIC DMA out of sync */\n+#define IGC_IMS_RXQ0\t\tIGC_ICR_RXQ0 /* Rx Queue 0 Interrupt */\n+#define IGC_IMS_RXQ1\t\tIGC_ICR_RXQ1 /* Rx Queue 1 Interrupt */\n+#define IGC_IMS_TXQ0\t\tIGC_ICR_TXQ0 /* Tx Queue 0 Interrupt */\n+#define IGC_IMS_TXQ1\t\tIGC_ICR_TXQ1 /* Tx Queue 1 Interrupt */\n+#define IGC_IMS_OTHER\t\tIGC_ICR_OTHER /* Other Interrupts */\n+#define IGC_IMS_FER\t\tIGC_ICR_FER /* Fatal Error */\n+\n+#define IGC_IMS_THS\t\tIGC_ICR_THS /* ICR.TS: Thermal Sensor Event*/\n+#define IGC_IMS_MDDET\t\tIGC_ICR_MDDET /* Malicious Driver Detect */\n+/* Extended Interrupt Mask Set */\n+#define IGC_EIMS_RX_QUEUE0\tIGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n+#define IGC_EIMS_RX_QUEUE1\tIGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n+#define IGC_EIMS_RX_QUEUE2\tIGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n+#define IGC_EIMS_RX_QUEUE3\tIGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n+#define IGC_EIMS_TX_QUEUE0\tIGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n+#define IGC_EIMS_TX_QUEUE1\tIGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n+#define IGC_EIMS_TX_QUEUE2\tIGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n+#define IGC_EIMS_TX_QUEUE3\tIGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n+#define IGC_EIMS_TCP_TIMER\tIGC_EICR_TCP_TIMER /* TCP Timer */\n+#define IGC_EIMS_OTHER\tIGC_EICR_OTHER   /* Interrupt Cause Active */\n+\n+/* Interrupt Cause Set */\n+#define IGC_ICS_LSC\t\tIGC_ICR_LSC       /* Link Status Change */\n+#define IGC_ICS_RXSEQ\t\tIGC_ICR_RXSEQ     /* Rx sequence error */\n+#define IGC_ICS_RXDMT0\tIGC_ICR_RXDMT0    /* Rx desc min. threshold */\n+#define IGC_ICS_DRSTA\t\tIGC_ICR_DRSTA     /* Device Reset Aserted */\n+\n+/* Extended Interrupt Cause Set */\n+#define IGC_EICS_RX_QUEUE0\tIGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n+#define IGC_EICS_RX_QUEUE1\tIGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n+#define IGC_EICS_RX_QUEUE2\tIGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n+#define IGC_EICS_RX_QUEUE3\tIGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n+#define IGC_EICS_TX_QUEUE0\tIGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n+#define IGC_EICS_TX_QUEUE1\tIGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n+#define IGC_EICS_TX_QUEUE2\tIGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n+#define IGC_EICS_TX_QUEUE3\tIGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n+#define IGC_EICS_TCP_TIMER\tIGC_EICR_TCP_TIMER /* TCP Timer */\n+#define IGC_EICS_OTHER\tIGC_EICR_OTHER   /* Interrupt Cause Active */\n+\n+#define IGC_EITR_ITR_INT_MASK\t0x0000FFFF\n+#define IGC_EITR_INTERVAL 0x00007FFC\n+/* IGC_EITR_CNT_IGNR is only for 82576 and newer */\n+#define IGC_EITR_CNT_IGNR\t0x80000000 /* Don't reset counters on write */\n+\n+/* Transmit Descriptor Control */\n+#define IGC_TXDCTL_PTHRESH\t0x0000003F /* TXDCTL Prefetch Threshold */\n+#define IGC_TXDCTL_HTHRESH\t0x00003F00 /* TXDCTL Host Threshold */\n+#define IGC_TXDCTL_WTHRESH\t0x003F0000 /* TXDCTL Writeback Threshold */\n+#define IGC_TXDCTL_GRAN\t0x01000000 /* TXDCTL Granularity */\n+#define IGC_TXDCTL_FULL_TX_DESC_WB\t0x01010000 /* GRAN=1, WTHRESH=1 */\n+#define IGC_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */\n+/* Enable the counting of descriptors still to be processed. */\n+#define IGC_TXDCTL_COUNT_DESC\t0x00400000\n+\n+/* Flow Control Constants */\n+#define FLOW_CONTROL_ADDRESS_LOW\t0x00C28001\n+#define FLOW_CONTROL_ADDRESS_HIGH\t0x00000100\n+#define FLOW_CONTROL_TYPE\t\t0x8808\n+\n+/* 802.1q VLAN Packet Size */\n+#define VLAN_TAG_SIZE\t\t\t4    /* 802.3ac tag (not DMA'd) */\n+#define IGC_VLAN_FILTER_TBL_SIZE\t128  /* VLAN Filter Table (4096 bits) */\n+\n+/* Receive Address\n+ * Number of high/low register pairs in the RAR. The RAR (Receive Address\n+ * Registers) holds the directed and multicast addresses that we monitor.\n+ * Technically, we have 16 spots.  However, we reserve one of these spots\n+ * (RAR[15]) for our directed address used by controllers with\n+ * manageability enabled, allowing us room for 15 multicast addresses.\n+ */\n+#define IGC_RAR_ENTRIES\t15\n+#define IGC_RAH_AV\t\t0x80000000 /* Receive descriptor valid */\n+#define IGC_RAL_MAC_ADDR_LEN\t4\n+#define IGC_RAH_MAC_ADDR_LEN\t2\n+#define IGC_RAH_QUEUE_MASK_82575\t0x000C0000\n+#define IGC_RAH_POOL_1\t0x00040000\n+\n+/* Error Codes */\n+#define IGC_SUCCESS\t\t\t0\n+#define IGC_ERR_NVM\t\t\t1\n+#define IGC_ERR_PHY\t\t\t2\n+#define IGC_ERR_CONFIG\t\t3\n+#define IGC_ERR_PARAM\t\t\t4\n+#define IGC_ERR_MAC_INIT\t\t5\n+#define IGC_ERR_PHY_TYPE\t\t6\n+#define IGC_ERR_RESET\t\t\t9\n+#define IGC_ERR_MASTER_REQUESTS_PENDING\t10\n+#define IGC_ERR_HOST_INTERFACE_COMMAND\t11\n+#define IGC_BLK_PHY_RESET\t\t12\n+#define IGC_ERR_SWFW_SYNC\t\t13\n+#define IGC_NOT_IMPLEMENTED\t\t14\n+#define IGC_ERR_MBX\t\t\t15\n+#define IGC_ERR_INVALID_ARGUMENT\t16\n+#define IGC_ERR_NO_SPACE\t\t17\n+#define IGC_ERR_NVM_PBA_SECTION\t18\n+#define IGC_ERR_I2C\t\t\t19\n+#define IGC_ERR_INVM_VALUE_NOT_FOUND\t20\n+\n+/* Loop limit on how long we wait for auto-negotiation to complete */\n+#define FIBER_LINK_UP_LIMIT\t\t50\n+#define COPPER_LINK_UP_LIMIT\t\t10\n+#define PHY_AUTO_NEG_LIMIT\t\t45\n+#define PHY_FORCE_LIMIT\t\t\t20\n+/* Number of 100 microseconds we wait for PCI Express master disable */\n+#define MASTER_DISABLE_TIMEOUT\t\t800\n+/* Number of milliseconds we wait for PHY configuration done after MAC reset */\n+#define PHY_CFG_TIMEOUT\t\t\t100\n+/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */\n+#define MDIO_OWNERSHIP_TIMEOUT\t\t10\n+/* Number of milliseconds for NVM auto read done after MAC reset. */\n+#define AUTO_READ_DONE_TIMEOUT\t\t10\n+\n+/* Flow Control */\n+#define IGC_FCRTH_RTH\t\t0x0000FFF8 /* Mask Bits[15:3] for RTH */\n+#define IGC_FCRTL_RTL\t\t0x0000FFF8 /* Mask Bits[15:3] for RTL */\n+#define IGC_FCRTL_XONE\t0x80000000 /* Enable XON frame transmission */\n+\n+/* Transmit Configuration Word */\n+#define IGC_TXCW_FD\t\t0x00000020 /* TXCW full duplex */\n+#define IGC_TXCW_PAUSE\t0x00000080 /* TXCW sym pause request */\n+#define IGC_TXCW_ASM_DIR\t0x00000100 /* TXCW astm pause direction */\n+#define IGC_TXCW_PAUSE_MASK\t0x00000180 /* TXCW pause request mask */\n+#define IGC_TXCW_ANE\t\t0x80000000 /* Auto-neg enable */\n+\n+/* Receive Configuration Word */\n+#define IGC_RXCW_CW\t\t0x0000ffff /* RxConfigWord mask */\n+#define IGC_RXCW_IV\t\t0x08000000 /* Receive config invalid */\n+#define IGC_RXCW_C\t\t0x20000000 /* Receive config */\n+#define IGC_RXCW_SYNCH\t0x40000000 /* Receive config synch */\n+\n+#define IGC_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n+#define IGC_TSYNCTXCTL_ENABLED\t0x00000010 /* enable Tx timestamping */\n+\n+/* HH Time Sync */\n+#define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK\t0x0000F000 /* max delay */\n+#define IGC_TSYNCTXCTL_SYNC_COMP_ERR\t\t0x20000000 /* sync err */\n+#define IGC_TSYNCTXCTL_SYNC_COMP\t\t0x40000000 /* sync complete */\n+#define IGC_TSYNCTXCTL_START_SYNC\t\t0x80000000 /* initiate sync */\n+\n+#define IGC_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n+#define IGC_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n+#define IGC_TSYNCRXCTL_TYPE_L2_V2\t0x00\n+#define IGC_TSYNCRXCTL_TYPE_L4_V1\t0x02\n+#define IGC_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n+#define IGC_TSYNCRXCTL_TYPE_ALL\t0x08\n+#define IGC_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n+#define IGC_TSYNCRXCTL_ENABLED\t0x00000010 /* enable Rx timestamping */\n+#define IGC_TSYNCRXCTL_SYSCFI\t\t0x00000020 /* Sys clock frequency */\n+\n+#define IGC_RXMTRL_PTP_V1_SYNC_MESSAGE\t0x00000000\n+#define IGC_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE\t0x00010000\n+\n+#define IGC_RXMTRL_PTP_V2_SYNC_MESSAGE\t0x00000000\n+#define IGC_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE\t0x01000000\n+\n+#define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK\t\t0x000000FF\n+#define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE\t\t0x00\n+#define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE\t0x01\n+#define IGC_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE\t0x02\n+#define IGC_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE\t0x03\n+#define IGC_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE\t0x04\n+\n+#define IGC_TSYNCRXCFG_PTP_V2_MSGID_MASK\t\t0x00000F00\n+#define IGC_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE\t\t0x0000\n+#define IGC_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE\t0x0100\n+#define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE\t0x0200\n+#define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE\t0x0300\n+#define IGC_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE\t0x0800\n+#define IGC_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE\t0x0900\n+#define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00\n+#define IGC_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE\t0x0B00\n+#define IGC_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE\t0x0C00\n+#define IGC_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE\t0x0D00\n+\n+#define IGC_TIMINCA_16NS_SHIFT\t24\n+#define IGC_TIMINCA_INCPERIOD_SHIFT\t24\n+#define IGC_TIMINCA_INCVALUE_MASK\t0x00FFFFFF\n+\n+/* Time Sync Interrupt Cause/Mask Register Bits */\n+#define TSINTR_SYS_WRAP\t(1 << 0) /* SYSTIM Wrap around. */\n+#define TSINTR_TXTS\t(1 << 1) /* Transmit Timestamp. */\n+#define TSINTR_TT0\t(1 << 3) /* Target Time 0 Trigger. */\n+#define TSINTR_TT1\t(1 << 4) /* Target Time 1 Trigger. */\n+#define TSINTR_AUTT0\t(1 << 5) /* Auxiliary Timestamp 0 Taken. */\n+#define TSINTR_AUTT1\t(1 << 6) /* Auxiliary Timestamp 1 Taken. */\n+\n+#define TSYNC_INTERRUPTS\tTSINTR_TXTS\n+\n+/* TSAUXC Configuration Bits */\n+#define TSAUXC_EN_TT0\t(1 << 0)  /* Enable target time 0. */\n+#define TSAUXC_EN_TT1\t(1 << 1)  /* Enable target time 1. */\n+#define TSAUXC_EN_CLK0\t(1 << 2)  /* Enable Configurable Frequency Clock 0. */\n+#define TSAUXC_ST0\t(1 << 4)  /* Start Clock 0 Toggle on Target Time 0. */\n+#define TSAUXC_EN_CLK1\t(1 << 5)  /* Enable Configurable Frequency Clock 1. */\n+#define TSAUXC_ST1\t(1 << 7)  /* Start Clock 1 Toggle on Target Time 1. */\n+#define TSAUXC_EN_TS0\t(1 << 8)  /* Enable hardware timestamp 0. */\n+#define TSAUXC_EN_TS1\t(1 << 10) /* Enable hardware timestamp 0. */\n+\n+/* SDP Configuration Bits */\n+#define AUX0_SEL_SDP0\t(0u << 0)  /* Assign SDP0 to auxiliary time stamp 0. */\n+#define AUX0_SEL_SDP1\t(1u << 0)  /* Assign SDP1 to auxiliary time stamp 0. */\n+#define AUX0_SEL_SDP2\t(2u << 0)  /* Assign SDP2 to auxiliary time stamp 0. */\n+#define AUX0_SEL_SDP3\t(3u << 0)  /* Assign SDP3 to auxiliary time stamp 0. */\n+#define AUX0_TS_SDP_EN\t(1u << 2)  /* Enable auxiliary time stamp trigger 0. */\n+#define AUX1_SEL_SDP0\t(0u << 3)  /* Assign SDP0 to auxiliary time stamp 1. */\n+#define AUX1_SEL_SDP1\t(1u << 3)  /* Assign SDP1 to auxiliary time stamp 1. */\n+#define AUX1_SEL_SDP2\t(2u << 3)  /* Assign SDP2 to auxiliary time stamp 1. */\n+#define AUX1_SEL_SDP3\t(3u << 3)  /* Assign SDP3 to auxiliary time stamp 1. */\n+#define AUX1_TS_SDP_EN\t(1u << 5)  /* Enable auxiliary time stamp trigger 1. */\n+#define TS_SDP0_EN\t(1u << 8)  /* SDP0 is assigned to Tsync. */\n+#define TS_SDP1_EN\t(1u << 11) /* SDP1 is assigned to Tsync. */\n+#define TS_SDP2_EN\t(1u << 14) /* SDP2 is assigned to Tsync. */\n+#define TS_SDP3_EN\t(1u << 17) /* SDP3 is assigned to Tsync. */\n+#define TS_SDP0_SEL_TT0\t(0u << 6)  /* Target time 0 is output on SDP0. */\n+#define TS_SDP0_SEL_TT1\t(1u << 6)  /* Target time 1 is output on SDP0. */\n+#define TS_SDP1_SEL_TT0\t(0u << 9)  /* Target time 0 is output on SDP1. */\n+#define TS_SDP1_SEL_TT1\t(1u << 9)  /* Target time 1 is output on SDP1. */\n+#define TS_SDP0_SEL_FC0\t(2u << 6)  /* Freq clock  0 is output on SDP0. */\n+#define TS_SDP0_SEL_FC1\t(3u << 6)  /* Freq clock  1 is output on SDP0. */\n+#define TS_SDP1_SEL_FC0\t(2u << 9)  /* Freq clock  0 is output on SDP1. */\n+#define TS_SDP1_SEL_FC1\t(3u << 9)  /* Freq clock  1 is output on SDP1. */\n+#define TS_SDP2_SEL_TT0\t(0u << 12) /* Target time 0 is output on SDP2. */\n+#define TS_SDP2_SEL_TT1\t(1u << 12) /* Target time 1 is output on SDP2. */\n+#define TS_SDP2_SEL_FC0\t(2u << 12) /* Freq clock  0 is output on SDP2. */\n+#define TS_SDP2_SEL_FC1\t(3u << 12) /* Freq clock  1 is output on SDP2. */\n+#define TS_SDP3_SEL_TT0\t(0u << 15) /* Target time 0 is output on SDP3. */\n+#define TS_SDP3_SEL_TT1\t(1u << 15) /* Target time 1 is output on SDP3. */\n+#define TS_SDP3_SEL_FC0\t(2u << 15) /* Freq clock  0 is output on SDP3. */\n+#define TS_SDP3_SEL_FC1\t(3u << 15) /* Freq clock  1 is output on SDP3. */\n+\n+#define IGC_CTRL_SDP0_DIR\t0x00400000  /* SDP0 Data direction */\n+#define IGC_CTRL_SDP1_DIR\t0x00800000  /* SDP1 Data direction */\n+\n+/* Extended Device Control */\n+#define IGC_CTRL_EXT_SDP2_DIR\t0x00000400 /* SDP2 Data direction */\n+\n+/* ETQF register bit definitions */\n+#define IGC_ETQF_1588\t\t\t(1 << 30)\n+#define IGC_FTQF_VF_BP\t\t0x00008000\n+#define IGC_FTQF_1588_TIME_STAMP\t0x08000000\n+#define IGC_FTQF_MASK\t\t\t0xF0000000\n+#define IGC_FTQF_MASK_PROTO_BP\t0x10000000\n+/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n+#define IGC_IMIREXT_CTRL_BP\t0x00080000  /* Bypass check of ctrl bits */\n+#define IGC_IMIREXT_SIZE_BP\t0x00001000  /* Packet size bypass */\n+\n+#define IGC_RXDADV_STAT_TSIP\t\t0x08000 /* timestamp in packet */\n+#define IGC_TSICR_TXTS\t\t0x00000002\n+#define IGC_TSIM_TXTS\t\t\t0x00000002\n+/* TUPLE Filtering Configuration */\n+#define IGC_TTQF_DISABLE_MASK\t\t0xF0008000 /* TTQF Disable Mask */\n+#define IGC_TTQF_QUEUE_ENABLE\t\t0x100   /* TTQF Queue Enable Bit */\n+#define IGC_TTQF_PROTOCOL_MASK\t0xFF    /* TTQF Protocol Mask */\n+/* TTQF TCP Bit, shift with IGC_TTQF_PROTOCOL SHIFT */\n+#define IGC_TTQF_PROTOCOL_TCP\t\t0x0\n+/* TTQF UDP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */\n+#define IGC_TTQF_PROTOCOL_UDP\t\t0x1\n+/* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */\n+#define IGC_TTQF_PROTOCOL_SCTP\t0x2\n+#define IGC_TTQF_PROTOCOL_SHIFT\t5       /* TTQF Protocol Shift */\n+#define IGC_TTQF_QUEUE_SHIFT\t\t16      /* TTQF Queue Shfit */\n+#define IGC_TTQF_RX_QUEUE_MASK\t0x70000 /* TTQF Queue Mask */\n+#define IGC_TTQF_MASK_ENABLE\t\t0x10000000 /* TTQF Mask Enable Bit */\n+#define IGC_IMIR_CLEAR_MASK\t\t0xF001FFFF /* IMIR Reg Clear Mask */\n+#define IGC_IMIR_PORT_BYPASS\t\t0x20000 /* IMIR Port Bypass Bit */\n+#define IGC_IMIR_PRIORITY_SHIFT\t29 /* IMIR Priority Shift */\n+#define IGC_IMIREXT_CLEAR_MASK\t0x7FFFF /* IMIREXT Reg Clear Mask */\n+\n+#define IGC_MDICNFG_EXT_MDIO\t\t0x80000000 /* MDI ext/int destination */\n+#define IGC_MDICNFG_COM_MDIO\t\t0x40000000 /* MDI shared w/ lan 0 */\n+#define IGC_MDICNFG_PHY_MASK\t\t0x03E00000\n+#define IGC_MDICNFG_PHY_SHIFT\t\t21\n+\n+#define IGC_MEDIA_PORT_COPPER\t\t\t1\n+#define IGC_MEDIA_PORT_OTHER\t\t\t2\n+#define IGC_M88E1112_AUTO_COPPER_SGMII\t0x2\n+#define IGC_M88E1112_AUTO_COPPER_BASEX\t0x3\n+#define IGC_M88E1112_STATUS_LINK\t\t0x0004 /* Interface Link Bit */\n+#define IGC_M88E1112_MAC_CTRL_1\t\t0x10\n+#define IGC_M88E1112_MAC_CTRL_1_MODE_MASK\t0x0380 /* Mode Select */\n+#define IGC_M88E1112_MAC_CTRL_1_MODE_SHIFT\t7\n+#define IGC_M88E1112_PAGE_ADDR\t\t0x16\n+#define IGC_M88E1112_STATUS\t\t\t0x01\n+\n+#define IGC_THSTAT_LOW_EVENT\t\t0x20000000 /* Low thermal threshold */\n+#define IGC_THSTAT_MID_EVENT\t\t0x00200000 /* Mid thermal threshold */\n+#define IGC_THSTAT_HIGH_EVENT\t\t0x00002000 /* High thermal threshold */\n+#define IGC_THSTAT_PWR_DOWN\t\t0x00000001 /* Power Down Event */\n+#define IGC_THSTAT_LINK_THROTTLE\t0x00000002 /* Link Spd Throttle Event */\n+\n+/* EEE defines */\n+#define IGC_IPCNFG_EEE_2_5G_AN\t0x00000010 /* IPCNFG EEE Ena 2.5G AN */\n+#define IGC_IPCNFG_EEE_1G_AN\t\t0x00000008 /* IPCNFG EEE Ena 1G AN */\n+#define IGC_IPCNFG_EEE_100M_AN\t0x00000004 /* IPCNFG EEE Ena 100M AN */\n+#define IGC_EEER_TX_LPI_EN\t\t0x00010000 /* EEER Tx LPI Enable */\n+#define IGC_EEER_RX_LPI_EN\t\t0x00020000 /* EEER Rx LPI Enable */\n+#define IGC_EEER_LPI_FC\t\t0x00040000 /* EEER Ena on Flow Cntrl */\n+/* EEE status */\n+#define IGC_EEER_EEE_NEG\t\t0x20000000 /* EEE capability nego */\n+#define IGC_EEER_RX_LPI_STATUS\t0x40000000 /* Rx in LPI state */\n+#define IGC_EEER_TX_LPI_STATUS\t0x80000000 /* Tx in LPI state */\n+#define IGC_EEE_LP_ADV_ADDR_I350\t0x040F     /* EEE LP Advertisement */\n+#define IGC_M88E1543_PAGE_ADDR\t0x16       /* Page Offset Register */\n+#define IGC_M88E1543_EEE_CTRL_1\t0x0\n+#define IGC_M88E1543_EEE_CTRL_1_MS\t0x0001     /* EEE Master/Slave */\n+#define IGC_M88E1543_FIBER_CTRL\t0x0        /* Fiber Control Register */\n+#define IGC_EEE_ADV_DEV_I354\t\t7\n+#define IGC_EEE_ADV_ADDR_I354\t\t60\n+#define IGC_EEE_ADV_100_SUPPORTED\t(1 << 1)   /* 100BaseTx EEE Supported */\n+#define IGC_EEE_ADV_1000_SUPPORTED\t(1 << 2)   /* 1000BaseT EEE Supported */\n+#define IGC_PCS_STATUS_DEV_I354\t3\n+#define IGC_PCS_STATUS_ADDR_I354\t1\n+#define IGC_PCS_STATUS_RX_LPI_RCVD\t0x0400\n+#define IGC_PCS_STATUS_TX_LPI_RCVD\t0x0800\n+#define IGC_M88E1512_CFG_REG_1\t0x0010\n+#define IGC_M88E1512_CFG_REG_2\t0x0011\n+#define IGC_M88E1512_CFG_REG_3\t0x0007\n+#define IGC_M88E1512_MODE\t\t0x0014\n+#define IGC_EEE_SU_LPI_CLK_STP\t0x00800000 /* EEE LPI Clock Stop */\n+#define IGC_EEE_LP_ADV_DEV_I210\t7          /* EEE LP Adv Device */\n+#define IGC_EEE_LP_ADV_ADDR_I210\t61         /* EEE LP Adv Register */\n+#define IGC_EEE_SU_LPI_CLK_STP\t0x00800000 /* EEE LPI Clock Stop */\n+#define IGC_EEE_LP_ADV_DEV_I225\t7          /* EEE LP Adv Device */\n+#define IGC_EEE_LP_ADV_ADDR_I225\t61         /* EEE LP Adv Register */\n+\n+/* PCI Express Control */\n+#define IGC_GCR_RXD_NO_SNOOP\t\t0x00000001\n+#define IGC_GCR_RXDSCW_NO_SNOOP\t0x00000002\n+#define IGC_GCR_RXDSCR_NO_SNOOP\t0x00000004\n+#define IGC_GCR_TXD_NO_SNOOP\t\t0x00000008\n+#define IGC_GCR_TXDSCW_NO_SNOOP\t0x00000010\n+#define IGC_GCR_TXDSCR_NO_SNOOP\t0x00000020\n+#define IGC_GCR_CMPL_TMOUT_MASK\t0x0000F000\n+#define IGC_GCR_CMPL_TMOUT_10ms\t0x00001000\n+#define IGC_GCR_CMPL_TMOUT_RESEND\t0x00010000\n+#define IGC_GCR_CAP_VER2\t\t0x00040000\n+\n+#define PCIE_NO_SNOOP_ALL\t(IGC_GCR_RXD_NO_SNOOP | \\\n+\t\t\t\t IGC_GCR_RXDSCW_NO_SNOOP | \\\n+\t\t\t\t IGC_GCR_RXDSCR_NO_SNOOP | \\\n+\t\t\t\t IGC_GCR_TXD_NO_SNOOP    | \\\n+\t\t\t\t IGC_GCR_TXDSCW_NO_SNOOP | \\\n+\t\t\t\t IGC_GCR_TXDSCR_NO_SNOOP)\n+\n+#define IGC_MMDAC_FUNC_DATA\t0x4000 /* Data, no post increment */\n+\n+/* mPHY address control and data registers */\n+#define IGC_MPHY_ADDR_CTL\t\t0x0024 /* Address Control Reg */\n+#define IGC_MPHY_ADDR_CTL_OFFSET_MASK\t0xFFFF0000\n+#define IGC_MPHY_DATA\t\t\t0x0E10 /* Data Register */\n+\n+/* AFE CSR Offset for PCS CLK */\n+#define IGC_MPHY_PCS_CLK_REG_OFFSET\t0x0004\n+/* Override for near end digital loopback. */\n+#define IGC_MPHY_PCS_CLK_REG_DIGINELBEN\t0x10\n+\n+/* PHY Control Register */\n+#define MII_CR_SPEED_SELECT_MSB\t0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */\n+#define MII_CR_COLL_TEST_ENABLE\t0x0080  /* Collision test enable */\n+#define MII_CR_FULL_DUPLEX\t0x0100  /* FDX =1, half duplex =0 */\n+#define MII_CR_RESTART_AUTO_NEG\t0x0200  /* Restart auto negotiation */\n+#define MII_CR_ISOLATE\t\t0x0400  /* Isolate PHY from MII */\n+#define MII_CR_POWER_DOWN\t0x0800  /* Power down */\n+#define MII_CR_AUTO_NEG_EN\t0x1000  /* Auto Neg Enable */\n+#define MII_CR_SPEED_SELECT_LSB\t0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */\n+#define MII_CR_LOOPBACK\t\t0x4000  /* 0 = normal, 1 = loopback */\n+#define MII_CR_RESET\t\t0x8000  /* 0 = normal, 1 = PHY reset */\n+#define MII_CR_SPEED_1000\t0x0040\n+#define MII_CR_SPEED_100\t0x2000\n+#define MII_CR_SPEED_10\t\t0x0000\n+\n+/* PHY Status Register */\n+#define MII_SR_EXTENDED_CAPS\t0x0001 /* Extended register capabilities */\n+#define MII_SR_JABBER_DETECT\t0x0002 /* Jabber Detected */\n+#define MII_SR_LINK_STATUS\t0x0004 /* Link Status 1 = link */\n+#define MII_SR_AUTONEG_CAPS\t0x0008 /* Auto Neg Capable */\n+#define MII_SR_REMOTE_FAULT\t0x0010 /* Remote Fault Detect */\n+#define MII_SR_AUTONEG_COMPLETE\t0x0020 /* Auto Neg Complete */\n+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */\n+#define MII_SR_EXTENDED_STATUS\t0x0100 /* Ext. status info in Reg 0x0F */\n+#define MII_SR_100T2_HD_CAPS\t0x0200 /* 100T2 Half Duplex Capable */\n+#define MII_SR_100T2_FD_CAPS\t0x0400 /* 100T2 Full Duplex Capable */\n+#define MII_SR_10T_HD_CAPS\t0x0800 /* 10T   Half Duplex Capable */\n+#define MII_SR_10T_FD_CAPS\t0x1000 /* 10T   Full Duplex Capable */\n+#define MII_SR_100X_HD_CAPS\t0x2000 /* 100X  Half Duplex Capable */\n+#define MII_SR_100X_FD_CAPS\t0x4000 /* 100X  Full Duplex Capable */\n+#define MII_SR_100T4_CAPS\t0x8000 /* 100T4 Capable */\n+\n+/* Autoneg Advertisement Register */\n+#define NWAY_AR_SELECTOR_FIELD\t0x0001   /* indicates IEEE 802.3 CSMA/CD */\n+#define NWAY_AR_10T_HD_CAPS\t0x0020   /* 10T   Half Duplex Capable */\n+#define NWAY_AR_10T_FD_CAPS\t0x0040   /* 10T   Full Duplex Capable */\n+#define NWAY_AR_100TX_HD_CAPS\t0x0080   /* 100TX Half Duplex Capable */\n+#define NWAY_AR_100TX_FD_CAPS\t0x0100   /* 100TX Full Duplex Capable */\n+#define NWAY_AR_100T4_CAPS\t0x0200   /* 100T4 Capable */\n+#define NWAY_AR_PAUSE\t\t0x0400   /* Pause operation desired */\n+#define NWAY_AR_ASM_DIR\t\t0x0800   /* Asymmetric Pause Direction bit */\n+#define NWAY_AR_REMOTE_FAULT\t0x2000   /* Remote Fault detected */\n+#define NWAY_AR_NEXT_PAGE\t0x8000   /* Next Page ability supported */\n+\n+/* Link Partner Ability Register (Base Page) */\n+#define NWAY_LPAR_SELECTOR_FIELD\t0x0000 /* LP protocol selector field */\n+#define NWAY_LPAR_10T_HD_CAPS\t\t0x0020 /* LP 10T Half Dplx Capable */\n+#define NWAY_LPAR_10T_FD_CAPS\t\t0x0040 /* LP 10T Full Dplx Capable */\n+#define NWAY_LPAR_100TX_HD_CAPS\t\t0x0080 /* LP 100TX Half Dplx Capable */\n+#define NWAY_LPAR_100TX_FD_CAPS\t\t0x0100 /* LP 100TX Full Dplx Capable */\n+#define NWAY_LPAR_100T4_CAPS\t\t0x0200 /* LP is 100T4 Capable */\n+#define NWAY_LPAR_PAUSE\t\t\t0x0400 /* LP Pause operation desired */\n+#define NWAY_LPAR_ASM_DIR\t\t0x0800 /* LP Asym Pause Direction bit */\n+#define NWAY_LPAR_REMOTE_FAULT\t\t0x2000 /* LP detected Remote Fault */\n+#define NWAY_LPAR_ACKNOWLEDGE\t\t0x4000 /* LP rx'd link code word */\n+#define NWAY_LPAR_NEXT_PAGE\t\t0x8000 /* Next Page ability supported */\n+\n+/* Autoneg Expansion Register */\n+#define NWAY_ER_LP_NWAY_CAPS\t\t0x0001 /* LP has Auto Neg Capability */\n+#define NWAY_ER_PAGE_RXD\t\t0x0002 /* LP 10T Half Dplx Capable */\n+#define NWAY_ER_NEXT_PAGE_CAPS\t\t0x0004 /* LP 10T Full Dplx Capable */\n+#define NWAY_ER_LP_NEXT_PAGE_CAPS\t0x0008 /* LP 100TX Half Dplx Capable */\n+#define NWAY_ER_PAR_DETECT_FAULT\t0x0010 /* LP 100TX Full Dplx Capable */\n+\n+/* 1000BASE-T Control Register */\n+#define CR_1000T_ASYM_PAUSE\t0x0080 /* Advertise asymmetric pause bit */\n+#define CR_1000T_HD_CAPS\t0x0100 /* Advertise 1000T HD capability */\n+#define CR_1000T_FD_CAPS\t0x0200 /* Advertise 1000T FD capability  */\n+/* 1=Repeater/switch device port 0=DTE device */\n+#define CR_1000T_REPEATER_DTE\t0x0400\n+/* 1=Configure PHY as Master 0=Configure PHY as Slave */\n+#define CR_1000T_MS_VALUE\t0x0800\n+/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */\n+#define CR_1000T_MS_ENABLE\t0x1000\n+#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */\n+#define CR_1000T_TEST_MODE_1\t0x2000 /* Transmit Waveform test */\n+#define CR_1000T_TEST_MODE_2\t0x4000 /* Master Transmit Jitter test */\n+#define CR_1000T_TEST_MODE_3\t0x6000 /* Slave Transmit Jitter test */\n+#define CR_1000T_TEST_MODE_4\t0x8000 /* Transmitter Distortion test */\n+\n+/* 1000BASE-T Status Register */\n+#define SR_1000T_IDLE_ERROR_CNT\t\t0x00FF /* Num idle err since last rd */\n+#define SR_1000T_ASYM_PAUSE_DIR\t\t0x0100 /* LP asym pause direction bit */\n+#define SR_1000T_LP_HD_CAPS\t\t0x0400 /* LP is 1000T HD capable */\n+#define SR_1000T_LP_FD_CAPS\t\t0x0800 /* LP is 1000T FD capable */\n+#define SR_1000T_REMOTE_RX_STATUS\t0x1000 /* Remote receiver OK */\n+#define SR_1000T_LOCAL_RX_STATUS\t0x2000 /* Local receiver OK */\n+#define SR_1000T_MS_CONFIG_RES\t\t0x4000 /* 1=Local Tx Master, 0=Slave */\n+#define SR_1000T_MS_CONFIG_FAULT\t0x8000 /* Master/Slave config fault */\n+\n+#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT\t5\n+\n+/* PHY 1000 MII Register/Bit Definitions */\n+/* PHY Registers defined by IEEE */\n+#define PHY_CONTROL\t\t0x00 /* Control Register */\n+#define PHY_STATUS\t\t0x01 /* Status Register */\n+#define PHY_ID1\t\t\t0x02 /* Phy Id Reg (word 1) */\n+#define PHY_ID2\t\t\t0x03 /* Phy Id Reg (word 2) */\n+#define PHY_AUTONEG_ADV\t\t0x04 /* Autoneg Advertisement */\n+#define PHY_LP_ABILITY\t\t0x05 /* Link Partner Ability (Base Page) */\n+#define PHY_AUTONEG_EXP\t\t0x06 /* Autoneg Expansion Reg */\n+#define PHY_NEXT_PAGE_TX\t0x07 /* Next Page Tx */\n+#define PHY_LP_NEXT_PAGE\t0x08 /* Link Partner Next Page */\n+#define PHY_1000T_CTRL\t\t0x09 /* 1000Base-T Control Reg */\n+#define PHY_1000T_STATUS\t0x0A /* 1000Base-T Status Reg */\n+#define PHY_EXT_STATUS\t\t0x0F /* Extended Status Reg */\n+\n+/* PHY GPY 211 registers */\n+#define STANDARD_AN_REG_MASK\t0x0007 /* MMD */\n+#define ANEG_MULTIGBT_AN_CTRL\t0x0020 /* MULTI GBT AN Control Register */\n+#define MMD_DEVADDR_SHIFT\t16     /* Shift MMD to higher bits */\n+#define CR_2500T_FD_CAPS\t0x0080 /* Advertise 2500T FD capability */\n+\n+#define PHY_CONTROL_LB\t\t0x4000 /* PHY Loopback bit */\n+\n+/* NVM Control */\n+#define IGC_EECD_SK\t\t0x00000001 /* NVM Clock */\n+#define IGC_EECD_CS\t\t0x00000002 /* NVM Chip Select */\n+#define IGC_EECD_DI\t\t0x00000004 /* NVM Data In */\n+#define IGC_EECD_DO\t\t0x00000008 /* NVM Data Out */\n+#define IGC_EECD_REQ\t\t0x00000040 /* NVM Access Request */\n+#define IGC_EECD_GNT\t\t0x00000080 /* NVM Access Grant */\n+#define IGC_EECD_PRES\t\t0x00000100 /* NVM Present */\n+#define IGC_EECD_SIZE\t\t0x00000200 /* NVM Size (0=64 word 1=256 word) */\n+#define IGC_EECD_BLOCKED\t0x00008000 /* Bit banging access blocked flag */\n+#define IGC_EECD_ABORT\t0x00010000 /* NVM operation aborted flag */\n+#define IGC_EECD_TIMEOUT\t0x00020000 /* NVM read operation timeout flag */\n+#define IGC_EECD_ERROR_CLR\t0x00040000 /* NVM error status clear bit */\n+/* NVM Addressing bits based on type 0=small, 1=large */\n+#define IGC_EECD_ADDR_BITS\t0x00000400\n+#define IGC_EECD_TYPE\t\t0x00002000 /* NVM Type (1-SPI, 0-Microwire) */\n+#define IGC_NVM_GRANT_ATTEMPTS\t1000 /* NVM # attempts to gain grant */\n+#define IGC_EECD_AUTO_RD\t\t0x00000200  /* NVM Auto Read done */\n+#define IGC_EECD_SIZE_EX_MASK\t\t0x00007800  /* NVM Size */\n+#define IGC_EECD_SIZE_EX_SHIFT\t11\n+#define IGC_EECD_FLUPD\t\t0x00080000 /* Update FLASH */\n+#define IGC_EECD_AUPDEN\t\t0x00100000 /* Ena Auto FLASH update */\n+#define IGC_EECD_SEC1VAL\t\t0x00400000 /* Sector One Valid */\n+#define IGC_EECD_SEC1VAL_VALID_MASK\t(IGC_EECD_AUTO_RD | IGC_EECD_PRES)\n+#define IGC_EECD_FLUPD_I210\t\t0x00800000 /* Update FLASH */\n+#define IGC_EECD_FLUDONE_I210\t\t0x04000000 /* Update FLASH done */\n+#define IGC_EECD_FLASH_DETECTED_I210\t0x00080000 /* FLASH detected */\n+#define IGC_EECD_SEC1VAL_I210\t\t0x02000000 /* Sector One Valid */\n+#define IGC_FLUDONE_ATTEMPTS\t\t20000\n+#define IGC_EERD_EEWR_MAX_COUNT\t512 /* buffered EEPROM words rw */\n+#define IGC_I210_FIFO_SEL_RX\t\t0x00\n+#define IGC_I210_FIFO_SEL_TX_QAV(_i)\t(0x02 + (_i))\n+#define IGC_I210_FIFO_SEL_TX_LEGACY\tIGC_I210_FIFO_SEL_TX_QAV(0)\n+#define IGC_I210_FIFO_SEL_BMC2OS_TX\t0x06\n+#define IGC_I210_FIFO_SEL_BMC2OS_RX\t0x01\n+\n+#define IGC_I210_FLASH_SECTOR_SIZE\t0x1000 /* 4KB FLASH sector unit size */\n+/* Secure FLASH mode requires removing MSb */\n+#define IGC_I210_FW_PTR_MASK\t\t0x7FFF\n+/* Firmware code revision field word offset*/\n+#define IGC_I210_FW_VER_OFFSET\t328\n+\n+#define IGC_EECD_FLUPD_I225\t\t0x00800000 /* Update FLASH */\n+#define IGC_EECD_FLUDONE_I225\t\t0x04000000 /* Update FLASH done */\n+#define IGC_EECD_FLASH_DETECTED_I225\t0x00080000 /* FLASH detected */\n+#define IGC_FLUDONE_ATTEMPTS\t\t20000\n+#define IGC_EERD_EEWR_MAX_COUNT\t512 /* buffered EEPROM words rw */\n+#define IGC_EECD_SEC1VAL_I225\t\t0x02000000 /* Sector One Valid */\n+#define IGC_FLSECU_BLK_SW_ACCESS_I225\t0x00000004 /* Block SW access */\n+#define IGC_FWSM_FW_VALID_I225\t0x8000 /* FW valid bit */\n+\n+#define IGC_NVM_RW_REG_DATA\t16  /* Offset to data in NVM read/write regs */\n+#define IGC_NVM_RW_REG_DONE\t2   /* Offset to READ/WRITE done bit */\n+#define IGC_NVM_RW_REG_START\t1   /* Start operation */\n+#define IGC_NVM_RW_ADDR_SHIFT\t2   /* Shift to the address bits */\n+#define IGC_NVM_POLL_WRITE\t1   /* Flag for polling for write complete */\n+#define IGC_NVM_POLL_READ\t0   /* Flag for polling for read complete */\n+#define IGC_FLASH_UPDATES\t2000\n+\n+/* NVM Word Offsets */\n+#define NVM_COMPAT\t\t\t0x0003\n+#define NVM_ID_LED_SETTINGS\t\t0x0004\n+#define NVM_VERSION\t\t\t0x0005\n+#define NVM_SERDES_AMPLITUDE\t\t0x0006 /* SERDES output amplitude */\n+#define NVM_PHY_CLASS_WORD\t\t0x0007\n+#define IGC_I210_NVM_FW_MODULE_PTR\t0x0010\n+#define IGC_I350_NVM_FW_MODULE_PTR\t0x0051\n+#define NVM_FUTURE_INIT_WORD1\t\t0x0019\n+#define NVM_ETRACK_WORD\t\t\t0x0042\n+#define NVM_ETRACK_HIWORD\t\t0x0043\n+#define NVM_COMB_VER_OFF\t\t0x0083\n+#define NVM_COMB_VER_PTR\t\t0x003d\n+\n+/* NVM version defines */\n+#define NVM_MAJOR_MASK\t\t\t0xF000\n+#define NVM_MINOR_MASK\t\t\t0x0FF0\n+#define NVM_IMAGE_ID_MASK\t\t0x000F\n+#define NVM_COMB_VER_MASK\t\t0x00FF\n+#define NVM_MAJOR_SHIFT\t\t\t12\n+#define NVM_MINOR_SHIFT\t\t\t4\n+#define NVM_COMB_VER_SHFT\t\t8\n+#define NVM_VER_INVALID\t\t\t0xFFFF\n+#define NVM_ETRACK_SHIFT\t\t16\n+#define NVM_ETRACK_VALID\t\t0x8000\n+#define NVM_NEW_DEC_MASK\t\t0x0F00\n+#define NVM_HEX_CONV\t\t\t16\n+#define NVM_HEX_TENS\t\t\t10\n+\n+/* FW version defines */\n+/* Offset of \"Loader patch ptr\" in Firmware Header */\n+#define IGC_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET\t0x01\n+/* Patch generation hour & minutes */\n+#define IGC_I350_NVM_FW_VER_WORD1_OFFSET\t\t0x04\n+/* Patch generation month & day */\n+#define IGC_I350_NVM_FW_VER_WORD2_OFFSET\t\t0x05\n+/* Patch generation year */\n+#define IGC_I350_NVM_FW_VER_WORD3_OFFSET\t\t0x06\n+/* Patch major & minor numbers */\n+#define IGC_I350_NVM_FW_VER_WORD4_OFFSET\t\t0x07\n+\n+#define NVM_MAC_ADDR\t\t\t0x0000\n+#define NVM_SUB_DEV_ID\t\t\t0x000B\n+#define NVM_SUB_VEN_ID\t\t\t0x000C\n+#define NVM_DEV_ID\t\t\t0x000D\n+#define NVM_VEN_ID\t\t\t0x000E\n+#define NVM_INIT_CTRL_2\t\t\t0x000F\n+#define NVM_INIT_CTRL_4\t\t\t0x0013\n+#define NVM_LED_1_CFG\t\t\t0x001C\n+#define NVM_LED_0_2_CFG\t\t\t0x001F\n+\n+#define NVM_COMPAT_VALID_CSUM\t\t0x0001\n+#define NVM_FUTURE_INIT_WORD1_VALID_CSUM\t0x0040\n+\n+#define NVM_INIT_CONTROL2_REG\t\t0x000F\n+#define NVM_INIT_CONTROL3_PORT_B\t0x0014\n+#define NVM_INIT_3GIO_3\t\t\t0x001A\n+#define NVM_SWDEF_PINS_CTRL_PORT_0\t0x0020\n+#define NVM_INIT_CONTROL3_PORT_A\t0x0024\n+#define NVM_CFG\t\t\t\t0x0012\n+#define NVM_ALT_MAC_ADDR_PTR\t\t0x0037\n+#define NVM_CHECKSUM_REG\t\t0x003F\n+#define NVM_COMPATIBILITY_REG_3\t\t0x0003\n+#define NVM_COMPATIBILITY_BIT_MASK\t0x8000\n+\n+#define IGC_NVM_CFG_DONE_PORT_0\t0x040000 /* MNG config cycle done */\n+#define IGC_NVM_CFG_DONE_PORT_1\t0x080000 /* ...for second port */\n+#define IGC_NVM_CFG_DONE_PORT_2\t0x100000 /* ...for third port */\n+#define IGC_NVM_CFG_DONE_PORT_3\t0x200000 /* ...for fourth port */\n+\n+#define NVM_82580_LAN_FUNC_OFFSET(a)\t(\t\\\n+\t__extension__ ({\t\t\t\\\n+\t\ttypeof(a) _a = (a);\t\t\\\n+\t\t_a ? (0x40 + 0x40 * _a) : 0;\t\\\n+\t}))\n+\n+/* Mask bits for fields in Word 0x24 of the NVM */\n+#define NVM_WORD24_COM_MDIO\t\t0x0008 /* MDIO interface shared */\n+#define NVM_WORD24_EXT_MDIO\t\t0x0004 /* MDIO accesses routed extrnl */\n+/* Offset of Link Mode bits for 82575/82576 */\n+#define NVM_WORD24_LNK_MODE_OFFSET\t8\n+/* Offset of Link Mode bits for 82580 up */\n+#define NVM_WORD24_82580_LNK_MODE_OFFSET\t4\n+\n+\n+/* Mask bits for fields in Word 0x0f of the NVM */\n+#define NVM_WORD0F_PAUSE_MASK\t\t0x3000\n+#define NVM_WORD0F_PAUSE\t\t0x1000\n+#define NVM_WORD0F_ASM_DIR\t\t0x2000\n+#define NVM_WORD0F_SWPDIO_EXT_MASK\t0x00F0\n+\n+/* Mask bits for fields in Word 0x1a of the NVM */\n+#define NVM_WORD1A_ASPM_MASK\t\t0x000C\n+\n+/* Mask bits for fields in Word 0x03 of the EEPROM */\n+#define NVM_COMPAT_LOM\t\t\t0x0800\n+\n+/* length of string needed to store PBA number */\n+#define IGC_PBANUM_LENGTH\t\t11\n+\n+/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */\n+#define NVM_SUM\t\t\t\t0xBABA\n+\n+/* PBA (printed board assembly) number words */\n+#define NVM_PBA_OFFSET_0\t\t8\n+#define NVM_PBA_OFFSET_1\t\t9\n+#define NVM_PBA_PTR_GUARD\t\t0xFAFA\n+#define NVM_RESERVED_WORD\t\t0xFFFF\n+#define NVM_PHY_CLASS_A\t\t\t0x8000\n+#define NVM_SERDES_AMPLITUDE_MASK\t0x000F\n+#define NVM_SIZE_MASK\t\t\t0x1C00\n+#define NVM_SIZE_SHIFT\t\t\t10\n+#define NVM_WORD_SIZE_BASE_SHIFT\t6\n+#define NVM_SWDPIO_EXT_SHIFT\t\t4\n+\n+/* NVM Commands - Microwire */\n+#define NVM_READ_OPCODE_MICROWIRE\t0x6  /* NVM read opcode */\n+#define NVM_WRITE_OPCODE_MICROWIRE\t0x5  /* NVM write opcode */\n+#define NVM_ERASE_OPCODE_MICROWIRE\t0x7  /* NVM erase opcode */\n+#define NVM_EWEN_OPCODE_MICROWIRE\t0x13 /* NVM erase/write enable */\n+#define NVM_EWDS_OPCODE_MICROWIRE\t0x10 /* NVM erase/write disable */\n+\n+/* NVM Commands - SPI */\n+#define NVM_MAX_RETRY_SPI\t5000 /* Max wait of 5ms, for RDY signal */\n+#define NVM_READ_OPCODE_SPI\t0x03 /* NVM read opcode */\n+#define NVM_WRITE_OPCODE_SPI\t0x02 /* NVM write opcode */\n+#define NVM_A8_OPCODE_SPI\t0x08 /* opcode bit-3 = address bit-8 */\n+#define NVM_WREN_OPCODE_SPI\t0x06 /* NVM set Write Enable latch */\n+#define NVM_RDSR_OPCODE_SPI\t0x05 /* NVM read Status register */\n+\n+/* SPI NVM Status Register */\n+#define NVM_STATUS_RDY_SPI\t0x01\n+\n+/* Word definitions for ID LED Settings */\n+#define ID_LED_RESERVED_0000\t0x0000\n+#define ID_LED_RESERVED_FFFF\t0xFFFF\n+#define ID_LED_DEFAULT\t\t((ID_LED_OFF1_ON2  << 12) | \\\n+\t\t\t\t (ID_LED_OFF1_OFF2 <<  8) | \\\n+\t\t\t\t (ID_LED_DEF1_DEF2 <<  4) | \\\n+\t\t\t\t (ID_LED_DEF1_DEF2))\n+#define ID_LED_DEF1_DEF2\t0x1\n+#define ID_LED_DEF1_ON2\t\t0x2\n+#define ID_LED_DEF1_OFF2\t0x3\n+#define ID_LED_ON1_DEF2\t\t0x4\n+#define ID_LED_ON1_ON2\t\t0x5\n+#define ID_LED_ON1_OFF2\t\t0x6\n+#define ID_LED_OFF1_DEF2\t0x7\n+#define ID_LED_OFF1_ON2\t\t0x8\n+#define ID_LED_OFF1_OFF2\t0x9\n+\n+#define IGP_ACTIVITY_LED_MASK\t0xFFFFF0FF\n+#define IGP_ACTIVITY_LED_ENABLE\t0x0300\n+#define IGP_LED3_MODE\t\t0x07000000\n+\n+/* PCI/PCI-X/PCI-EX Config space */\n+#define PCIX_COMMAND_REGISTER\t\t0xE6\n+#define PCIX_STATUS_REGISTER_LO\t\t0xE8\n+#define PCIX_STATUS_REGISTER_HI\t\t0xEA\n+#define PCI_HEADER_TYPE_REGISTER\t0x0E\n+#define PCIE_LINK_STATUS\t\t0x12\n+#define PCIE_DEVICE_CONTROL2\t\t0x28\n+\n+#define PCIX_COMMAND_MMRBC_MASK\t\t0x000C\n+#define PCIX_COMMAND_MMRBC_SHIFT\t0x2\n+#define PCIX_STATUS_HI_MMRBC_MASK\t0x0060\n+#define PCIX_STATUS_HI_MMRBC_SHIFT\t0x5\n+#define PCIX_STATUS_HI_MMRBC_4K\t\t0x3\n+#define PCIX_STATUS_HI_MMRBC_2K\t\t0x2\n+#define PCIX_STATUS_LO_FUNC_MASK\t0x7\n+#define PCI_HEADER_TYPE_MULTIFUNC\t0x80\n+#define PCIE_LINK_WIDTH_MASK\t\t0x3F0\n+#define PCIE_LINK_WIDTH_SHIFT\t\t4\n+#define PCIE_LINK_SPEED_MASK\t\t0x0F\n+#define PCIE_LINK_SPEED_2500\t\t0x01\n+#define PCIE_LINK_SPEED_5000\t\t0x02\n+#define PCIE_DEVICE_CONTROL2_16ms\t0x0005\n+\n+#define ETH_ADDR_LEN\t\t\t6\n+\n+#define PHY_REVISION_MASK\t\t0xFFFFFFF0\n+#define MAX_PHY_REG_ADDRESS\t\t0x1F  /* 5 bit address bus (0-0x1F) */\n+#define MAX_PHY_MULTI_PAGE_REG\t\t0xF\n+\n+/* Bit definitions for valid PHY IDs.\n+ * I = Integrated\n+ * E = External\n+ */\n+#define M88IGC_E_PHY_ID\t0x01410C50\n+#define M88IGC_I_PHY_ID\t0x01410C30\n+#define M88E1011_I_PHY_ID\t0x01410C20\n+#define IGP01IGC_I_PHY_ID\t0x02A80380\n+#define M88E1111_I_PHY_ID\t0x01410CC0\n+#define M88E1543_E_PHY_ID\t0x01410EA0\n+#define M88E1512_E_PHY_ID\t0x01410DD0\n+#define M88E1112_E_PHY_ID\t0x01410C90\n+#define I347AT4_E_PHY_ID\t0x01410DC0\n+#define M88E1340M_E_PHY_ID\t0x01410DF0\n+#define GG82563_E_PHY_ID\t0x01410CA0\n+#define IGP03IGC_E_PHY_ID\t0x02A80390\n+#define IFE_E_PHY_ID\t\t0x02A80330\n+#define IFE_PLUS_E_PHY_ID\t0x02A80320\n+#define IFE_C_E_PHY_ID\t\t0x02A80310\n+#define BMIGC_E_PHY_ID\t0x01410CB0\n+#define BMIGC_E_PHY_ID_R2\t0x01410CB1\n+#define I82577_E_PHY_ID\t\t0x01540050\n+#define I82578_E_PHY_ID\t\t0x004DD040\n+#define I82579_E_PHY_ID\t\t0x01540090\n+#define I217_E_PHY_ID\t\t0x015400A0\n+#define I82580_I_PHY_ID\t\t0x015403A0\n+#define I350_I_PHY_ID\t\t0x015403B0\n+#define I210_I_PHY_ID\t\t0x01410C00\n+#define IGP04IGC_E_PHY_ID\t0x02A80391\n+#define M88_VENDOR\t\t0x0141\n+#define I225_I_PHY_ID\t\t0x67C9DC00\n+\n+/* M88E1000 Specific Registers */\n+#define M88IGC_PHY_SPEC_CTRL\t\t0x10  /* PHY Specific Control Reg */\n+#define M88IGC_PHY_SPEC_STATUS\t0x11  /* PHY Specific Status Reg */\n+#define M88IGC_EXT_PHY_SPEC_CTRL\t0x14  /* Extended PHY Specific Cntrl */\n+#define M88IGC_RX_ERR_CNTR\t\t0x15  /* Receive Error Counter */\n+\n+#define M88IGC_PHY_EXT_CTRL\t\t0x1A  /* PHY extend control register */\n+#define M88IGC_PHY_PAGE_SELECT\t0x1D  /* Reg 29 for pg number setting */\n+#define M88IGC_PHY_GEN_CONTROL\t0x1E  /* meaning depends on reg 29 */\n+#define M88IGC_PHY_VCO_REG_BIT8\t0x100 /* Bits 8 & 11 are adjusted for */\n+#define M88IGC_PHY_VCO_REG_BIT11\t0x800 /* improved BER performance */\n+\n+/* M88E1000 PHY Specific Control Register */\n+#define M88IGC_PSCR_POLARITY_REVERSAL\t0x0002 /* 1=Polarity Reverse enabled */\n+/* MDI Crossover Mode bits 6:5 Manual MDI configuration */\n+#define M88IGC_PSCR_MDI_MANUAL_MODE\t0x0000\n+#define M88IGC_PSCR_MDIX_MANUAL_MODE\t0x0020  /* Manual MDIX configuration */\n+/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */\n+#define M88IGC_PSCR_AUTO_X_1000T\t0x0040\n+/* Auto crossover enabled all speeds */\n+#define M88IGC_PSCR_AUTO_X_MODE\t0x0060\n+#define M88IGC_PSCR_ASSERT_CRS_ON_TX\t0x0800 /* 1=Assert CRS on Tx */\n+\n+/* M88E1000 PHY Specific Status Register */\n+#define M88IGC_PSSR_REV_POLARITY\t0x0002 /* 1=Polarity reversed */\n+#define M88IGC_PSSR_DOWNSHIFT\t\t0x0020 /* 1=Downshifted */\n+#define M88IGC_PSSR_MDIX\t\t0x0040 /* 1=MDIX; 0=MDI */\n+/* 0 = <50M\n+ * 1 = 50-80M\n+ * 2 = 80-110M\n+ * 3 = 110-140M\n+ * 4 = >140M\n+ */\n+#define M88IGC_PSSR_CABLE_LENGTH\t0x0380\n+#define M88IGC_PSSR_LINK\t\t0x0400 /* 1=Link up, 0=Link down */\n+#define M88IGC_PSSR_SPD_DPLX_RESOLVED\t0x0800 /* 1=Speed & Duplex resolved */\n+#define M88IGC_PSSR_DPLX\t\t0x2000 /* 1=Duplex 0=Half Duplex */\n+#define M88IGC_PSSR_SPEED\t\t0xC000 /* Speed, bits 14:15 */\n+#define M88IGC_PSSR_100MBS\t\t0x4000 /* 01=100Mbs */\n+#define M88IGC_PSSR_1000MBS\t\t0x8000 /* 10=1000Mbs */\n+\n+#define M88IGC_PSSR_CABLE_LENGTH_SHIFT\t7\n+\n+/* Number of times we will attempt to autonegotiate before downshifting if we\n+ * are the master\n+ */\n+#define M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK\t0x0C00\n+#define M88IGC_EPSCR_MASTER_DOWNSHIFT_1X\t0x0000\n+/* Number of times we will attempt to autonegotiate before downshifting if we\n+ * are the slave\n+ */\n+#define M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK\t0x0300\n+#define M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X\t0x0100\n+#define M88IGC_EPSCR_TX_CLK_25\t0x0070 /* 25  MHz TX_CLK */\n+\n+/* Intel I347AT4 Registers */\n+#define I347AT4_PCDL\t\t0x10 /* PHY Cable Diagnostics Length */\n+#define I347AT4_PCDC\t\t0x15 /* PHY Cable Diagnostics Control */\n+#define I347AT4_PAGE_SELECT\t0x16\n+\n+/* I347AT4 Extended PHY Specific Control Register */\n+\n+/* Number of times we will attempt to autonegotiate before downshifting if we\n+ * are the master\n+ */\n+#define I347AT4_PSCR_DOWNSHIFT_ENABLE\t0x0800\n+#define I347AT4_PSCR_DOWNSHIFT_MASK\t0x7000\n+#define I347AT4_PSCR_DOWNSHIFT_1X\t0x0000\n+#define I347AT4_PSCR_DOWNSHIFT_2X\t0x1000\n+#define I347AT4_PSCR_DOWNSHIFT_3X\t0x2000\n+#define I347AT4_PSCR_DOWNSHIFT_4X\t0x3000\n+#define I347AT4_PSCR_DOWNSHIFT_5X\t0x4000\n+#define I347AT4_PSCR_DOWNSHIFT_6X\t0x5000\n+#define I347AT4_PSCR_DOWNSHIFT_7X\t0x6000\n+#define I347AT4_PSCR_DOWNSHIFT_8X\t0x7000\n+\n+/* I347AT4 PHY Cable Diagnostics Control */\n+#define I347AT4_PCDC_CABLE_LENGTH_UNIT\t0x0400 /* 0=cm 1=meters */\n+\n+/* M88E1112 only registers */\n+#define M88E1112_VCT_DSP_DISTANCE\t0x001A\n+\n+/* M88EC018 Rev 2 specific DownShift settings */\n+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK\t0x0E00\n+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X\t0x0800\n+\n+#define I82578_EPSCR_DOWNSHIFT_ENABLE\t\t0x0020\n+#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK\t0x001C\n+\n+/* BME1000 PHY Specific Control Register */\n+#define BMIGC_PSCR_ENABLE_DOWNSHIFT\t0x0800 /* 1 = enable downshift */\n+\n+/* Bits...\n+ * 15-5: page\n+ * 4-0: register offset\n+ */\n+#define GG82563_PAGE_SHIFT\t5\n+#define GG82563_REG(page, reg)\t\\\n+\t(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))\n+#define GG82563_MIN_ALT_REG\t30\n+\n+/* GG82563 Specific Registers */\n+#define GG82563_PHY_SPEC_CTRL\t\tGG82563_REG(0, 16) /* PHY Spec Cntrl */\n+#define GG82563_PHY_PAGE_SELECT\t\tGG82563_REG(0, 22) /* Page Select */\n+#define GG82563_PHY_SPEC_CTRL_2\t\tGG82563_REG(0, 26) /* PHY Spec Cntrl2 */\n+#define GG82563_PHY_PAGE_SELECT_ALT\tGG82563_REG(0, 29) /* Alt Page Select */\n+\n+/* MAC Specific Control Register */\n+#define GG82563_PHY_MAC_SPEC_CTRL\tGG82563_REG(2, 21)\n+\n+#define GG82563_PHY_DSP_DISTANCE\tGG82563_REG(5, 26) /* DSP Distance */\n+\n+/* Page 193 - Port Control Registers */\n+/* Kumeran Mode Control */\n+#define GG82563_PHY_KMRN_MODE_CTRL\tGG82563_REG(193, 16)\n+#define GG82563_PHY_PWR_MGMT_CTRL\tGG82563_REG(193, 20) /* Pwr Mgt Ctrl */\n+\n+/* Page 194 - KMRN Registers */\n+#define GG82563_PHY_INBAND_CTRL\t\tGG82563_REG(194, 18) /* Inband Ctrl */\n+\n+/* MDI Control */\n+#define IGC_MDIC_DATA_MASK\t0x0000FFFF\n+#define IGC_MDIC_INT_EN\t\t0x20000000\n+#define IGC_MDIC_REG_MASK\t0x001F0000\n+#define IGC_MDIC_REG_SHIFT\t16\n+#define IGC_MDIC_PHY_MASK\t0x03E00000\n+#define IGC_MDIC_PHY_SHIFT\t21\n+#define IGC_MDIC_OP_WRITE\t0x04000000\n+#define IGC_MDIC_OP_READ\t0x08000000\n+#define IGC_MDIC_READY\t0x10000000\n+#define IGC_MDIC_ERROR\t0x40000000\n+#define IGC_MDIC_DEST\t\t0x80000000\n+\n+#define IGC_N0_QUEUE -1\n+\n+#define IGC_MAX_MAC_HDR_LEN\t127\n+#define IGC_MAX_NETWORK_HDR_LEN\t511\n+\n+#define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))\n+#define IGC_VLAPQF_P_VALID(_n)\t(0x1 << (3 + (_n) * 4))\n+#define IGC_VLAPQF_QUEUE_MASK\t0x03\n+#define IGC_VFTA_BLOCK_SIZE\t8\n+/* SerDes Control */\n+#define IGC_GEN_CTL_READY\t\t0x80000000\n+#define IGC_GEN_CTL_ADDRESS_SHIFT\t8\n+#define IGC_GEN_POLL_TIMEOUT\t\t640\n+\n+/* LinkSec register fields */\n+#define IGC_LSECTXCAP_SUM_MASK\t0x00FF0000\n+#define IGC_LSECTXCAP_SUM_SHIFT\t16\n+#define IGC_LSECRXCAP_SUM_MASK\t0x00FF0000\n+#define IGC_LSECRXCAP_SUM_SHIFT\t16\n+\n+#define IGC_LSECTXCTRL_EN_MASK\t0x00000003\n+#define IGC_LSECTXCTRL_DISABLE\t0x0\n+#define IGC_LSECTXCTRL_AUTH\t\t0x1\n+#define IGC_LSECTXCTRL_AUTH_ENCRYPT\t0x2\n+#define IGC_LSECTXCTRL_AISCI\t\t0x00000020\n+#define IGC_LSECTXCTRL_PNTHRSH_MASK\t0xFFFFFF00\n+#define IGC_LSECTXCTRL_RSV_MASK\t0x000000D8\n+\n+#define IGC_LSECRXCTRL_EN_MASK\t0x0000000C\n+#define IGC_LSECRXCTRL_EN_SHIFT\t2\n+#define IGC_LSECRXCTRL_DISABLE\t0x0\n+#define IGC_LSECRXCTRL_CHECK\t\t0x1\n+#define IGC_LSECRXCTRL_STRICT\t\t0x2\n+#define IGC_LSECRXCTRL_DROP\t\t0x3\n+#define IGC_LSECRXCTRL_PLSH\t\t0x00000040\n+#define IGC_LSECRXCTRL_RP\t\t0x00000080\n+#define IGC_LSECRXCTRL_RSV_MASK\t0xFFFFFF33\n+\n+/* Tx Rate-Scheduler Config fields */\n+#define IGC_RTTBCNRC_RS_ENA\t\t0x80000000\n+#define IGC_RTTBCNRC_RF_DEC_MASK\t0x00003FFF\n+#define IGC_RTTBCNRC_RF_INT_SHIFT\t14\n+#define IGC_RTTBCNRC_RF_INT_MASK\t\\\n+\t(IGC_RTTBCNRC_RF_DEC_MASK << IGC_RTTBCNRC_RF_INT_SHIFT)\n+\n+/* DMA Coalescing register fields */\n+/* DMA Coalescing Watchdog Timer */\n+#define IGC_DMACR_DMACWT_MASK\t\t0x00003FFF\n+/* DMA Coalescing Rx Threshold */\n+#define IGC_DMACR_DMACTHR_MASK\t0x00FF0000\n+#define IGC_DMACR_DMACTHR_SHIFT\t16\n+/* Lx when no PCIe transactions */\n+#define IGC_DMACR_DMAC_LX_MASK\t0x30000000\n+#define IGC_DMACR_DMAC_LX_SHIFT\t28\n+#define IGC_DMACR_DMAC_EN\t\t0x80000000 /* Enable DMA Coalescing */\n+/* DMA Coalescing BMC-to-OS Watchdog Enable */\n+#define IGC_DMACR_DC_BMC2OSW_EN\t0x00008000\n+\n+/* DMA Coalescing Transmit Threshold */\n+#define IGC_DMCTXTH_DMCTTHR_MASK\t0x00000FFF\n+\n+#define IGC_DMCTLX_TTLX_MASK\t\t0x00000FFF /* Time to LX request */\n+\n+/* Rx Traffic Rate Threshold */\n+#define IGC_DMCRTRH_UTRESH_MASK\t0x0007FFFF\n+/* Rx packet rate in current window */\n+#define IGC_DMCRTRH_LRPRCW\t\t0x80000000\n+\n+/* DMA Coal Rx Traffic Current Count */\n+#define IGC_DMCCNT_CCOUNT_MASK\t0x01FFFFFF\n+\n+/* Flow ctrl Rx Threshold High val */\n+#define IGC_FCRTC_RTH_COAL_MASK\t0x0003FFF0\n+#define IGC_FCRTC_RTH_COAL_SHIFT\t4\n+/* Lx power decision based on DMA coal */\n+#define IGC_PCIEMISC_LX_DECISION\t0x00000080\n+\n+#define IGC_RXPBS_CFG_TS_EN\t\t0x80000000 /* Timestamp in Rx buffer */\n+#define IGC_RXPBS_SIZE_I210_MASK\t0x0000003F /* Rx packet buffer size */\n+#define IGC_TXPB0S_SIZE_I210_MASK\t0x0000003F /* Tx packet buffer 0 size */\n+#define I210_RXPBSIZE_DEFAULT\t\t0x000000A2 /* RXPBSIZE default */\n+#define I210_TXPBSIZE_DEFAULT\t\t0x04000014 /* TXPBSIZE default */\n+\n+\n+#define I225_RXPBSIZE_DEFAULT\t\t0x000000A2 /* RXPBSIZE default */\n+#define I225_TXPBSIZE_DEFAULT\t\t0x04000014 /* TXPBSIZE default */\n+#define IGC_RXPBS_SIZE_I225_MASK\t0x0000003F /* Rx packet buffer size */\n+#define IGC_TXPB0S_SIZE_I225_MASK\t0x0000003F /* Tx packet buffer 0 size */\n+#define IGC_STM_OPCODE\t\t0xDB00\n+#define IGC_EEPROM_FLASH_SIZE_WORD\t0x11\n+#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \\\n+\t(u8)((invm_dword) & 0x7)\n+#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \\\n+\t(u8)(((invm_dword) & 0x0000FE00) >> 9)\n+#define INVM_DWORD_TO_WORD_DATA(invm_dword) \\\n+\t(u16)(((invm_dword) & 0xFFFF0000) >> 16)\n+#define IGC_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS\t8\n+#define IGC_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS\t1\n+#define IGC_INVM_ULT_BYTES_SIZE\t\t8\n+#define IGC_INVM_RECORD_SIZE_IN_BYTES\t4\n+#define IGC_INVM_VER_FIELD_ONE\t\t0x1FF8\n+#define IGC_INVM_VER_FIELD_TWO\t\t0x7FE000\n+#define IGC_INVM_IMGTYPE_FIELD\t\t0x1F800000\n+\n+#define IGC_INVM_MAJOR_MASK\t0x3F0\n+#define IGC_INVM_MINOR_MASK\t0xF\n+#define IGC_INVM_MAJOR_SHIFT\t4\n+\n+/* PLL Defines */\n+#define IGC_PCI_PMCSR\t\t0x44\n+#define IGC_PCI_PMCSR_D3\t\t0x03\n+#define IGC_MAX_PLL_TRIES\t\t5\n+#define IGC_PHY_PLL_UNCONF\t\t0xFF\n+#define IGC_PHY_PLL_FREQ_PAGE\t0xFC0000\n+#define IGC_PHY_PLL_FREQ_REG\t\t0x000E\n+#define IGC_INVM_DEFAULT_AL\t\t0x202F\n+#define IGC_INVM_AUTOLOAD\t\t0x0A\n+#define IGC_INVM_PLL_WO_VAL\t\t0x0010\n+\n+/* Proxy Filter Control Extended */\n+#define IGC_PROXYFCEX_MDNS\t\t0x00000001 /* mDNS */\n+#define IGC_PROXYFCEX_MDNS_M\t\t0x00000002 /* mDNS Multicast */\n+#define IGC_PROXYFCEX_MDNS_U\t\t0x00000004 /* mDNS Unicast */\n+#define IGC_PROXYFCEX_IPV4_M\t\t0x00000008 /* IPv4 Multicast */\n+#define IGC_PROXYFCEX_IPV6_M\t\t0x00000010 /* IPv6 Multicast */\n+#define IGC_PROXYFCEX_IGMP\t\t0x00000020 /* IGMP */\n+#define IGC_PROXYFCEX_IGMP_M\t\t0x00000040 /* IGMP Multicast */\n+#define IGC_PROXYFCEX_ARPRES\t\t0x00000080 /* ARP Response */\n+#define IGC_PROXYFCEX_ARPRES_D\t0x00000100 /* ARP Response Directed */\n+#define IGC_PROXYFCEX_ICMPV4\t\t0x00000200 /* ICMPv4 */\n+#define IGC_PROXYFCEX_ICMPV4_D\t0x00000400 /* ICMPv4 Directed */\n+#define IGC_PROXYFCEX_ICMPV6\t\t0x00000800 /* ICMPv6 */\n+#define IGC_PROXYFCEX_ICMPV6_D\t0x00001000 /* ICMPv6 Directed */\n+#define IGC_PROXYFCEX_DNS\t\t0x00002000 /* DNS */\n+\n+/* Proxy Filter Control */\n+#define IGC_PROXYFC_D0\t\t0x00000001 /* Enable offload in D0 */\n+#define IGC_PROXYFC_EX\t\t0x00000004 /* Directed exact proxy */\n+#define IGC_PROXYFC_MC\t\t0x00000008 /* Directed MC Proxy */\n+#define IGC_PROXYFC_BC\t\t0x00000010 /* Broadcast Proxy Enable */\n+#define IGC_PROXYFC_ARP_DIRECTED\t0x00000020 /* Directed ARP Proxy Ena */\n+#define IGC_PROXYFC_IPV4\t\t0x00000040 /* Directed IPv4 Enable */\n+#define IGC_PROXYFC_IPV6\t\t0x00000080 /* Directed IPv6 Enable */\n+#define IGC_PROXYFC_NS\t\t0x00000200 /* IPv6 Neighbor Solicitation */\n+#define IGC_PROXYFC_NS_DIRECTED\t0x00000400 /* Directed NS Proxy Ena */\n+#define IGC_PROXYFC_ARP\t\t0x00000800 /* ARP Request Proxy Ena */\n+/* Proxy Status */\n+#define IGC_PROXYS_CLEAR\t\t0xFFFFFFFF /* Clear */\n+\n+/* Firmware Status */\n+#define IGC_FWSTS_FWRI\t\t0x80000000 /* FW Reset Indication */\n+/* VF Control */\n+#define IGC_VTCTRL_RST\t\t0x04000000 /* Reset VF */\n+\n+#define IGC_STATUS_LAN_ID_MASK\t0x00000000C /* Mask for Lan ID field */\n+/* Lan ID bit field offset in status register */\n+#define IGC_STATUS_LAN_ID_OFFSET\t2\n+#define IGC_VFTA_ENTRIES\t\t128\n+\n+#define IGC_UNUSEDARG\n+#define ERROR_REPORT(fmt)\tdo { } while (0)\n+#endif /* _IGC_DEFINES_H_ */\ndiff --git a/drivers/net/igc/base/e1000_hw.h b/drivers/net/igc/base/e1000_hw.h\nnew file mode 100644\nindex 0000000..9a5781a\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_hw.h\n@@ -0,0 +1,1051 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_HW_H_\n+#define _IGC_HW_H_\n+\n+#include \"e1000_osdep.h\"\n+#include \"e1000_regs.h\"\n+#include \"e1000_defines.h\"\n+\n+struct igc_hw;\n+\n+#define IGC_DEV_ID_82542\t\t\t0x1000\n+#define IGC_DEV_ID_82543GC_FIBER\t\t0x1001\n+#define IGC_DEV_ID_82543GC_COPPER\t\t0x1004\n+#define IGC_DEV_ID_82544EI_COPPER\t\t0x1008\n+#define IGC_DEV_ID_82544EI_FIBER\t\t0x1009\n+#define IGC_DEV_ID_82544GC_COPPER\t\t0x100C\n+#define IGC_DEV_ID_82544GC_LOM\t\t0x100D\n+#define IGC_DEV_ID_82540EM\t\t\t0x100E\n+#define IGC_DEV_ID_82540EM_LOM\t\t0x1015\n+#define IGC_DEV_ID_82540EP_LOM\t\t0x1016\n+#define IGC_DEV_ID_82540EP\t\t\t0x1017\n+#define IGC_DEV_ID_82540EP_LP\t\t\t0x101E\n+#define IGC_DEV_ID_82545EM_COPPER\t\t0x100F\n+#define IGC_DEV_ID_82545EM_FIBER\t\t0x1011\n+#define IGC_DEV_ID_82545GM_COPPER\t\t0x1026\n+#define IGC_DEV_ID_82545GM_FIBER\t\t0x1027\n+#define IGC_DEV_ID_82545GM_SERDES\t\t0x1028\n+#define IGC_DEV_ID_82546EB_COPPER\t\t0x1010\n+#define IGC_DEV_ID_82546EB_FIBER\t\t0x1012\n+#define IGC_DEV_ID_82546EB_QUAD_COPPER\t0x101D\n+#define IGC_DEV_ID_82546GB_COPPER\t\t0x1079\n+#define IGC_DEV_ID_82546GB_FIBER\t\t0x107A\n+#define IGC_DEV_ID_82546GB_SERDES\t\t0x107B\n+#define IGC_DEV_ID_82546GB_PCIE\t\t0x108A\n+#define IGC_DEV_ID_82546GB_QUAD_COPPER\t0x1099\n+#define IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3\t0x10B5\n+#define IGC_DEV_ID_82541EI\t\t\t0x1013\n+#define IGC_DEV_ID_82541EI_MOBILE\t\t0x1018\n+#define IGC_DEV_ID_82541ER_LOM\t\t0x1014\n+#define IGC_DEV_ID_82541ER\t\t\t0x1078\n+#define IGC_DEV_ID_82541GI\t\t\t0x1076\n+#define IGC_DEV_ID_82541GI_LF\t\t\t0x107C\n+#define IGC_DEV_ID_82541GI_MOBILE\t\t0x1077\n+#define IGC_DEV_ID_82547EI\t\t\t0x1019\n+#define IGC_DEV_ID_82547EI_MOBILE\t\t0x101A\n+#define IGC_DEV_ID_82547GI\t\t\t0x1075\n+#define IGC_DEV_ID_82571EB_COPPER\t\t0x105E\n+#define IGC_DEV_ID_82571EB_FIBER\t\t0x105F\n+#define IGC_DEV_ID_82571EB_SERDES\t\t0x1060\n+#define IGC_DEV_ID_82571EB_SERDES_DUAL\t0x10D9\n+#define IGC_DEV_ID_82571EB_SERDES_QUAD\t0x10DA\n+#define IGC_DEV_ID_82571EB_QUAD_COPPER\t0x10A4\n+#define IGC_DEV_ID_82571PT_QUAD_COPPER\t0x10D5\n+#define IGC_DEV_ID_82571EB_QUAD_FIBER\t\t0x10A5\n+#define IGC_DEV_ID_82571EB_QUAD_COPPER_LP\t0x10BC\n+#define IGC_DEV_ID_82572EI_COPPER\t\t0x107D\n+#define IGC_DEV_ID_82572EI_FIBER\t\t0x107E\n+#define IGC_DEV_ID_82572EI_SERDES\t\t0x107F\n+#define IGC_DEV_ID_82572EI\t\t\t0x10B9\n+#define IGC_DEV_ID_82573E\t\t\t0x108B\n+#define IGC_DEV_ID_82573E_IAMT\t\t0x108C\n+#define IGC_DEV_ID_82573L\t\t\t0x109A\n+#define IGC_DEV_ID_82574L\t\t\t0x10D3\n+#define IGC_DEV_ID_82574LA\t\t\t0x10F6\n+#define IGC_DEV_ID_82583V\t\t\t0x150C\n+#define IGC_DEV_ID_80003ES2LAN_COPPER_DPT\t0x1096\n+#define IGC_DEV_ID_80003ES2LAN_SERDES_DPT\t0x1098\n+#define IGC_DEV_ID_80003ES2LAN_COPPER_SPT\t0x10BA\n+#define IGC_DEV_ID_80003ES2LAN_SERDES_SPT\t0x10BB\n+#define IGC_DEV_ID_ICH8_82567V_3\t\t0x1501\n+#define IGC_DEV_ID_ICH8_IGP_M_AMT\t\t0x1049\n+#define IGC_DEV_ID_ICH8_IGP_AMT\t\t0x104A\n+#define IGC_DEV_ID_ICH8_IGP_C\t\t\t0x104B\n+#define IGC_DEV_ID_ICH8_IFE\t\t\t0x104C\n+#define IGC_DEV_ID_ICH8_IFE_GT\t\t0x10C4\n+#define IGC_DEV_ID_ICH8_IFE_G\t\t\t0x10C5\n+#define IGC_DEV_ID_ICH8_IGP_M\t\t\t0x104D\n+#define IGC_DEV_ID_ICH9_IGP_M\t\t\t0x10BF\n+#define IGC_DEV_ID_ICH9_IGP_M_AMT\t\t0x10F5\n+#define IGC_DEV_ID_ICH9_IGP_M_V\t\t0x10CB\n+#define IGC_DEV_ID_ICH9_IGP_AMT\t\t0x10BD\n+#define IGC_DEV_ID_ICH9_BM\t\t\t0x10E5\n+#define IGC_DEV_ID_ICH9_IGP_C\t\t\t0x294C\n+#define IGC_DEV_ID_ICH9_IFE\t\t\t0x10C0\n+#define IGC_DEV_ID_ICH9_IFE_GT\t\t0x10C3\n+#define IGC_DEV_ID_ICH9_IFE_G\t\t\t0x10C2\n+#define IGC_DEV_ID_ICH10_R_BM_LM\t\t0x10CC\n+#define IGC_DEV_ID_ICH10_R_BM_LF\t\t0x10CD\n+#define IGC_DEV_ID_ICH10_R_BM_V\t\t0x10CE\n+#define IGC_DEV_ID_ICH10_D_BM_LM\t\t0x10DE\n+#define IGC_DEV_ID_ICH10_D_BM_LF\t\t0x10DF\n+#define IGC_DEV_ID_ICH10_D_BM_V\t\t0x1525\n+#define IGC_DEV_ID_PCH_M_HV_LM\t\t0x10EA\n+#define IGC_DEV_ID_PCH_M_HV_LC\t\t0x10EB\n+#define IGC_DEV_ID_PCH_D_HV_DM\t\t0x10EF\n+#define IGC_DEV_ID_PCH_D_HV_DC\t\t0x10F0\n+#define IGC_DEV_ID_PCH2_LV_LM\t\t\t0x1502\n+#define IGC_DEV_ID_PCH2_LV_V\t\t\t0x1503\n+#define IGC_DEV_ID_PCH_LPT_I217_LM\t\t0x153A\n+#define IGC_DEV_ID_PCH_LPT_I217_V\t\t0x153B\n+#define IGC_DEV_ID_PCH_LPTLP_I218_LM\t\t0x155A\n+#define IGC_DEV_ID_PCH_LPTLP_I218_V\t\t0x1559\n+#define IGC_DEV_ID_PCH_I218_LM2\t\t0x15A0\n+#define IGC_DEV_ID_PCH_I218_V2\t\t0x15A1\n+#define IGC_DEV_ID_PCH_I218_LM3\t\t0x15A2 /* Wildcat Point PCH */\n+#define IGC_DEV_ID_PCH_I218_V3\t\t0x15A3 /* Wildcat Point PCH */\n+#define IGC_DEV_ID_PCH_SPT_I219_LM\t\t0x156F /* Sunrise Point PCH */\n+#define IGC_DEV_ID_PCH_SPT_I219_V\t\t0x1570 /* Sunrise Point PCH */\n+#define IGC_DEV_ID_PCH_SPT_I219_LM2\t\t0x15B7 /* Sunrise Point-H PCH */\n+#define IGC_DEV_ID_PCH_SPT_I219_V2\t\t0x15B8 /* Sunrise Point-H PCH */\n+#define IGC_DEV_ID_PCH_LBG_I219_LM3\t\t0x15B9 /* LEWISBURG PCH */\n+#define IGC_DEV_ID_PCH_SPT_I219_LM4\t\t0x15D7\n+#define IGC_DEV_ID_PCH_SPT_I219_V4\t\t0x15D8\n+#define IGC_DEV_ID_PCH_SPT_I219_LM5\t\t0x15E3\n+#define IGC_DEV_ID_PCH_SPT_I219_V5\t\t0x15D6\n+#define IGC_DEV_ID_PCH_CNP_I219_LM6\t\t0x15BD\n+#define IGC_DEV_ID_PCH_CNP_I219_V6\t\t0x15BE\n+#define IGC_DEV_ID_PCH_CNP_I219_LM7\t\t0x15BB\n+#define IGC_DEV_ID_PCH_CNP_I219_V7\t\t0x15BC\n+#define IGC_DEV_ID_PCH_ICP_I219_LM8\t\t0x15DF\n+#define IGC_DEV_ID_PCH_ICP_I219_V8\t\t0x15E0\n+#define IGC_DEV_ID_PCH_ICP_I219_LM9\t\t0x15E1\n+#define IGC_DEV_ID_PCH_ICP_I219_V9\t\t0x15E2\n+#define IGC_DEV_ID_82576\t\t\t0x10C9\n+#define IGC_DEV_ID_82576_FIBER\t\t0x10E6\n+#define IGC_DEV_ID_82576_SERDES\t\t0x10E7\n+#define IGC_DEV_ID_82576_QUAD_COPPER\t\t0x10E8\n+#define IGC_DEV_ID_82576_QUAD_COPPER_ET2\t0x1526\n+#define IGC_DEV_ID_82576_NS\t\t\t0x150A\n+#define IGC_DEV_ID_82576_NS_SERDES\t\t0x1518\n+#define IGC_DEV_ID_82576_SERDES_QUAD\t\t0x150D\n+#define IGC_DEV_ID_82576_VF\t\t\t0x10CA\n+#define IGC_DEV_ID_82576_VF_HV\t\t0x152D\n+#define IGC_DEV_ID_I350_VF\t\t\t0x1520\n+#define IGC_DEV_ID_I350_VF_HV\t\t\t0x152F\n+#define IGC_DEV_ID_82575EB_COPPER\t\t0x10A7\n+#define IGC_DEV_ID_82575EB_FIBER_SERDES\t0x10A9\n+#define IGC_DEV_ID_82575GB_QUAD_COPPER\t0x10D6\n+#define IGC_DEV_ID_82580_COPPER\t\t0x150E\n+#define IGC_DEV_ID_82580_FIBER\t\t0x150F\n+#define IGC_DEV_ID_82580_SERDES\t\t0x1510\n+#define IGC_DEV_ID_82580_SGMII\t\t0x1511\n+#define IGC_DEV_ID_82580_COPPER_DUAL\t\t0x1516\n+#define IGC_DEV_ID_82580_QUAD_FIBER\t\t0x1527\n+#define IGC_DEV_ID_I350_COPPER\t\t0x1521\n+#define IGC_DEV_ID_I350_FIBER\t\t\t0x1522\n+#define IGC_DEV_ID_I350_SERDES\t\t0x1523\n+#define IGC_DEV_ID_I350_SGMII\t\t\t0x1524\n+#define IGC_DEV_ID_I350_DA4\t\t\t0x1546\n+#define IGC_DEV_ID_I210_COPPER\t\t0x1533\n+#define IGC_DEV_ID_I210_COPPER_OEM1\t\t0x1534\n+#define IGC_DEV_ID_I210_COPPER_IT\t\t0x1535\n+#define IGC_DEV_ID_I210_FIBER\t\t\t0x1536\n+#define IGC_DEV_ID_I210_SERDES\t\t0x1537\n+#define IGC_DEV_ID_I210_SGMII\t\t\t0x1538\n+#define IGC_DEV_ID_I210_COPPER_FLASHLESS\t0x157B\n+#define IGC_DEV_ID_I210_SERDES_FLASHLESS\t0x157C\n+#define IGC_DEV_ID_I210_SGMII_FLASHLESS\t0x15F6\n+#define IGC_DEV_ID_I211_COPPER\t\t0x1539\n+#define IGC_DEV_ID_I225_LM\t\t\t0x15F2\n+#define IGC_DEV_ID_I225_V\t\t\t0x15F3\n+#define IGC_DEV_ID_I225_K\t\t\t0x3100\n+#define IGC_DEV_ID_I225_I\t\t\t0x15F8\n+#define IGC_DEV_ID_I220_V\t\t\t0x15F7\n+#define IGC_DEV_ID_I225_BLANK_NVM\t\t0x15FD\n+#define IGC_DEV_ID_I354_BACKPLANE_1GBPS\t0x1F40\n+#define IGC_DEV_ID_I354_SGMII\t\t\t0x1F41\n+#define IGC_DEV_ID_I354_BACKPLANE_2_5GBPS\t0x1F45\n+#define IGC_DEV_ID_DH89XXCC_SGMII\t\t0x0438\n+#define IGC_DEV_ID_DH89XXCC_SERDES\t\t0x043A\n+#define IGC_DEV_ID_DH89XXCC_BACKPLANE\t\t0x043C\n+#define IGC_DEV_ID_DH89XXCC_SFP\t\t0x0440\n+\n+#define IGC_REVISION_0\t0\n+#define IGC_REVISION_1\t1\n+#define IGC_REVISION_2\t2\n+#define IGC_REVISION_3\t3\n+#define IGC_REVISION_4\t4\n+\n+#define IGC_FUNC_0\t\t0\n+#define IGC_FUNC_1\t\t1\n+#define IGC_FUNC_2\t\t2\n+#define IGC_FUNC_3\t\t3\n+\n+#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0\t0\n+#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1\t3\n+#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN2\t6\n+#define IGC_ALT_MAC_ADDRESS_OFFSET_LAN3\t9\n+\n+enum igc_mac_type {\n+\tigc_undefined = 0,\n+\tigc_82542,\n+\tigc_82543,\n+\tigc_82544,\n+\tigc_82540,\n+\tigc_82545,\n+\tigc_82545_rev_3,\n+\tigc_82546,\n+\tigc_82546_rev_3,\n+\tigc_82541,\n+\tigc_82541_rev_2,\n+\tigc_82547,\n+\tigc_82547_rev_2,\n+\tigc_82571,\n+\tigc_82572,\n+\tigc_82573,\n+\tigc_82574,\n+\tigc_82583,\n+\tigc_80003es2lan,\n+\tigc_ich8lan,\n+\tigc_ich9lan,\n+\tigc_ich10lan,\n+\tigc_pchlan,\n+\tigc_pch2lan,\n+\tigc_pch_lpt,\n+\tigc_pch_spt,\n+\tigc_pch_cnp,\n+\tigc_82575,\n+\tigc_82576,\n+\tigc_82580,\n+\tigc_i350,\n+\tigc_i354,\n+\tigc_i210,\n+\tigc_i211,\n+\tigc_i225,\n+\tigc_vfadapt,\n+\tigc_vfadapt_i350,\n+\tigc_num_macs  /* List is 1-based, so subtract 1 for true count. */\n+};\n+\n+enum igc_media_type {\n+\tigc_media_type_unknown = 0,\n+\tigc_media_type_copper = 1,\n+\tigc_media_type_fiber = 2,\n+\tigc_media_type_internal_serdes = 3,\n+\tigc_num_media_types\n+};\n+\n+enum igc_nvm_type {\n+\tigc_nvm_unknown = 0,\n+\tigc_nvm_none,\n+\tigc_nvm_eeprom_spi,\n+\tigc_nvm_eeprom_microwire,\n+\tigc_nvm_flash_hw,\n+\tigc_nvm_invm,\n+\tigc_nvm_flash_sw\n+};\n+\n+enum igc_nvm_override {\n+\tigc_nvm_override_none = 0,\n+\tigc_nvm_override_spi_small,\n+\tigc_nvm_override_spi_large,\n+\tigc_nvm_override_microwire_small,\n+\tigc_nvm_override_microwire_large\n+};\n+\n+enum igc_phy_type {\n+\tigc_phy_unknown = 0,\n+\tigc_phy_none,\n+\tigc_phy_m88,\n+\tigc_phy_igp,\n+\tigc_phy_igp_2,\n+\tigc_phy_gg82563,\n+\tigc_phy_igp_3,\n+\tigc_phy_ife,\n+\tigc_phy_bm,\n+\tigc_phy_82578,\n+\tigc_phy_82577,\n+\tigc_phy_82579,\n+\tigc_phy_i217,\n+\tigc_phy_82580,\n+\tigc_phy_vf,\n+\tigc_phy_i210,\n+\tigc_phy_i225,\n+};\n+\n+enum igc_bus_type {\n+\tigc_bus_type_unknown = 0,\n+\tigc_bus_type_pci,\n+\tigc_bus_type_pcix,\n+\tigc_bus_type_pci_express,\n+\tigc_bus_type_reserved\n+};\n+\n+enum igc_bus_speed {\n+\tigc_bus_speed_unknown = 0,\n+\tigc_bus_speed_33,\n+\tigc_bus_speed_66,\n+\tigc_bus_speed_100,\n+\tigc_bus_speed_120,\n+\tigc_bus_speed_133,\n+\tigc_bus_speed_2500,\n+\tigc_bus_speed_5000,\n+\tigc_bus_speed_reserved\n+};\n+\n+enum igc_bus_width {\n+\tigc_bus_width_unknown = 0,\n+\tigc_bus_width_pcie_x1,\n+\tigc_bus_width_pcie_x2,\n+\tigc_bus_width_pcie_x4 = 4,\n+\tigc_bus_width_pcie_x8 = 8,\n+\tigc_bus_width_32,\n+\tigc_bus_width_64,\n+\tigc_bus_width_reserved\n+};\n+\n+enum igc_1000t_rx_status {\n+\tigc_1000t_rx_status_not_ok = 0,\n+\tigc_1000t_rx_status_ok,\n+\tigc_1000t_rx_status_undefined = 0xFF\n+};\n+\n+enum igc_rev_polarity {\n+\tigc_rev_polarity_normal = 0,\n+\tigc_rev_polarity_reversed,\n+\tigc_rev_polarity_undefined = 0xFF\n+};\n+\n+enum igc_fc_mode {\n+\tigc_fc_none = 0,\n+\tigc_fc_rx_pause,\n+\tigc_fc_tx_pause,\n+\tigc_fc_full,\n+\tigc_fc_default = 0xFF\n+};\n+\n+enum igc_ffe_config {\n+\tigc_ffe_config_enabled = 0,\n+\tigc_ffe_config_active,\n+\tigc_ffe_config_blocked\n+};\n+\n+enum igc_dsp_config {\n+\tigc_dsp_config_disabled = 0,\n+\tigc_dsp_config_enabled,\n+\tigc_dsp_config_activated,\n+\tigc_dsp_config_undefined = 0xFF\n+};\n+\n+enum igc_ms_type {\n+\tigc_ms_hw_default = 0,\n+\tigc_ms_force_master,\n+\tigc_ms_force_slave,\n+\tigc_ms_auto\n+};\n+\n+enum igc_smart_speed {\n+\tigc_smart_speed_default = 0,\n+\tigc_smart_speed_on,\n+\tigc_smart_speed_off\n+};\n+\n+enum igc_serdes_link_state {\n+\tigc_serdes_link_down = 0,\n+\tigc_serdes_link_autoneg_progress,\n+\tigc_serdes_link_autoneg_complete,\n+\tigc_serdes_link_forced_up\n+};\n+\n+enum igc_invm_structure_type {\n+\tigc_invm_uninitialized_structure\t\t= 0x00,\n+\tigc_invm_word_autoload_structure\t\t= 0x01,\n+\tigc_invm_csr_autoload_structure\t\t= 0x02,\n+\tigc_invm_phy_register_autoload_structure\t= 0x03,\n+\tigc_invm_rsa_key_sha256_structure\t\t= 0x04,\n+\tigc_invm_invalidated_structure\t\t= 0x0f,\n+};\n+\n+#define __le16 u16\n+#define __le32 u32\n+#define __le64 u64\n+/* Receive Descriptor */\n+struct igc_rx_desc {\n+\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n+\t__le16 length;      /* Length of data DMAed into data buffer */\n+\t__le16 csum; /* Packet checksum */\n+\tu8  status;  /* Descriptor status */\n+\tu8  errors;  /* Descriptor Errors */\n+\t__le16 special;\n+};\n+\n+/* Receive Descriptor - Extended */\n+union igc_rx_desc_extended {\n+\tstruct {\n+\t\t__le64 buffer_addr;\n+\t\t__le64 reserved;\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\t__le32 mrq; /* Multiple Rx Queues */\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 ip_id;  /* IP id */\n+\t\t\t\t\t__le16 csum;   /* Packet Checksum */\n+\t\t\t\t} csum_ip;\n+\t\t\t} hi_dword;\n+\t\t} lower;\n+\t\tstruct {\n+\t\t\t__le32 status_error;  /* ext status/error */\n+\t\t\t__le16 length;\n+\t\t\t__le16 vlan; /* VLAN tag */\n+\t\t} upper;\n+\t} wb;  /* writeback */\n+};\n+\n+#define MAX_PS_BUFFERS 4\n+\n+/* Number of packet split data buffers (not including the header buffer) */\n+#define PS_PAGE_BUFFERS\t(MAX_PS_BUFFERS - 1)\n+\n+/* Receive Descriptor - Packet Split */\n+union igc_rx_desc_packet_split {\n+\tstruct {\n+\t\t/* one buffer for protocol header(s), three data buffers */\n+\t\t__le64 buffer_addr[MAX_PS_BUFFERS];\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\t__le32 mrq;  /* Multiple Rx Queues */\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\tstruct {\n+\t\t\t\t\t__le16 ip_id;    /* IP id */\n+\t\t\t\t\t__le16 csum;     /* Packet Checksum */\n+\t\t\t\t} csum_ip;\n+\t\t\t} hi_dword;\n+\t\t} lower;\n+\t\tstruct {\n+\t\t\t__le32 status_error;  /* ext status/error */\n+\t\t\t__le16 length0;  /* length of buffer 0 */\n+\t\t\t__le16 vlan;  /* VLAN tag */\n+\t\t} middle;\n+\t\tstruct {\n+\t\t\t__le16 header_status;\n+\t\t\t/* length of buffers 1-3 */\n+\t\t\t__le16 length[PS_PAGE_BUFFERS];\n+\t\t} upper;\n+\t\t__le64 reserved;\n+\t} wb; /* writeback */\n+};\n+\n+/* Transmit Descriptor */\n+struct igc_tx_desc {\n+\t__le64 buffer_addr;   /* Address of the descriptor's data buffer */\n+\tunion {\n+\t\t__le32 data;\n+\t\tstruct {\n+\t\t\t__le16 length;  /* Data buffer length */\n+\t\t\tu8 cso;  /* Checksum offset */\n+\t\t\tu8 cmd;  /* Descriptor control */\n+\t\t} flags;\n+\t} lower;\n+\tunion {\n+\t\t__le32 data;\n+\t\tstruct {\n+\t\t\tu8 status; /* Descriptor status */\n+\t\t\tu8 css;  /* Checksum start */\n+\t\t\t__le16 special;\n+\t\t} fields;\n+\t} upper;\n+};\n+\n+/* Offload Context Descriptor */\n+struct igc_context_desc {\n+\tunion {\n+\t\t__le32 ip_config;\n+\t\tstruct {\n+\t\t\tu8 ipcss;  /* IP checksum start */\n+\t\t\tu8 ipcso;  /* IP checksum offset */\n+\t\t\t__le16 ipcse;  /* IP checksum end */\n+\t\t} ip_fields;\n+\t} lower_setup;\n+\tunion {\n+\t\t__le32 tcp_config;\n+\t\tstruct {\n+\t\t\tu8 tucss;  /* TCP checksum start */\n+\t\t\tu8 tucso;  /* TCP checksum offset */\n+\t\t\t__le16 tucse;  /* TCP checksum end */\n+\t\t} tcp_fields;\n+\t} upper_setup;\n+\t__le32 cmd_and_length;\n+\tunion {\n+\t\t__le32 data;\n+\t\tstruct {\n+\t\t\tu8 status;  /* Descriptor status */\n+\t\t\tu8 hdr_len;  /* Header length */\n+\t\t\t__le16 mss;  /* Maximum segment size */\n+\t\t} fields;\n+\t} tcp_seg_setup;\n+};\n+\n+/* Offload data descriptor */\n+struct igc_data_desc {\n+\t__le64 buffer_addr;  /* Address of the descriptor's buffer address */\n+\tunion {\n+\t\t__le32 data;\n+\t\tstruct {\n+\t\t\t__le16 length;  /* Data buffer length */\n+\t\t\tu8 typ_len_ext;\n+\t\t\tu8 cmd;\n+\t\t} flags;\n+\t} lower;\n+\tunion {\n+\t\t__le32 data;\n+\t\tstruct {\n+\t\t\tu8 status;  /* Descriptor status */\n+\t\t\tu8 popts;  /* Packet Options */\n+\t\t\t__le16 special;\n+\t\t} fields;\n+\t} upper;\n+};\n+\n+/* Statistics counters collected by the MAC */\n+struct igc_hw_stats {\n+\tu64 crcerrs;\n+\tu64 algnerrc;\n+\tu64 symerrs;\n+\tu64 rxerrc;\n+\tu64 mpc;\n+\tu64 scc;\n+\tu64 ecol;\n+\tu64 mcc;\n+\tu64 latecol;\n+\tu64 colc;\n+\tu64 dc;\n+\tu64 tncrs;\n+\tu64 sec;\n+\tu64 cexterr;\n+\tu64 rlec;\n+\tu64 xonrxc;\n+\tu64 xontxc;\n+\tu64 xoffrxc;\n+\tu64 xofftxc;\n+\tu64 fcruc;\n+\tu64 prc64;\n+\tu64 prc127;\n+\tu64 prc255;\n+\tu64 prc511;\n+\tu64 prc1023;\n+\tu64 prc1522;\n+\tu64 gprc;\n+\tu64 bprc;\n+\tu64 mprc;\n+\tu64 gptc;\n+\tu64 gorc;\n+\tu64 gotc;\n+\tu64 rnbc;\n+\tu64 ruc;\n+\tu64 rfc;\n+\tu64 roc;\n+\tu64 rjc;\n+\tu64 mgprc;\n+\tu64 mgpdc;\n+\tu64 mgptc;\n+\tu64 tor;\n+\tu64 tot;\n+\tu64 tpr;\n+\tu64 tpt;\n+\tu64 ptc64;\n+\tu64 ptc127;\n+\tu64 ptc255;\n+\tu64 ptc511;\n+\tu64 ptc1023;\n+\tu64 ptc1522;\n+\tu64 mptc;\n+\tu64 bptc;\n+\tu64 tsctc;\n+\tu64 tsctfc;\n+\tu64 iac;\n+\tu64 icrxptc;\n+\tu64 icrxatc;\n+\tu64 ictxptc;\n+\tu64 ictxatc;\n+\tu64 ictxqec;\n+\tu64 ictxqmtc;\n+\tu64 icrxdmtc;\n+\tu64 icrxoc;\n+\tu64 cbtmpc;\n+\tu64 htdpmc;\n+\tu64 cbrdpc;\n+\tu64 cbrmpc;\n+\tu64 rpthc;\n+\tu64 hgptc;\n+\tu64 htcbdpc;\n+\tu64 hgorc;\n+\tu64 hgotc;\n+\tu64 lenerrs;\n+\tu64 scvpc;\n+\tu64 hrmpc;\n+\tu64 doosync;\n+\tu64 o2bgptc;\n+\tu64 o2bspc;\n+\tu64 b2ospc;\n+\tu64 b2ogprc;\n+};\n+\n+struct igc_vf_stats {\n+\tu64 base_gprc;\n+\tu64 base_gptc;\n+\tu64 base_gorc;\n+\tu64 base_gotc;\n+\tu64 base_mprc;\n+\tu64 base_gotlbc;\n+\tu64 base_gptlbc;\n+\tu64 base_gorlbc;\n+\tu64 base_gprlbc;\n+\n+\tu32 last_gprc;\n+\tu32 last_gptc;\n+\tu32 last_gorc;\n+\tu32 last_gotc;\n+\tu32 last_mprc;\n+\tu32 last_gotlbc;\n+\tu32 last_gptlbc;\n+\tu32 last_gorlbc;\n+\tu32 last_gprlbc;\n+\n+\tu64 gprc;\n+\tu64 gptc;\n+\tu64 gorc;\n+\tu64 gotc;\n+\tu64 mprc;\n+\tu64 gotlbc;\n+\tu64 gptlbc;\n+\tu64 gorlbc;\n+\tu64 gprlbc;\n+};\n+\n+struct igc_phy_stats {\n+\tu32 idle_errors;\n+\tu32 receive_errors;\n+};\n+\n+struct igc_host_mng_dhcp_cookie {\n+\tu32 signature;\n+\tu8  status;\n+\tu8  reserved0;\n+\tu16 vlan_id;\n+\tu32 reserved1;\n+\tu16 reserved2;\n+\tu8  reserved3;\n+\tu8  checksum;\n+};\n+\n+/* Host Interface \"Rev 1\" */\n+struct igc_host_command_header {\n+\tu8 command_id;\n+\tu8 command_length;\n+\tu8 command_options;\n+\tu8 checksum;\n+};\n+\n+#define IGC_HI_MAX_DATA_LENGTH\t252\n+struct igc_host_command_info {\n+\tstruct igc_host_command_header command_header;\n+\tu8 command_data[IGC_HI_MAX_DATA_LENGTH];\n+};\n+\n+/* Host Interface \"Rev 2\" */\n+struct igc_host_mng_command_header {\n+\tu8  command_id;\n+\tu8  checksum;\n+\tu16 reserved1;\n+\tu16 reserved2;\n+\tu16 command_length;\n+};\n+\n+#define IGC_HI_MAX_MNG_DATA_LENGTH\t0x6F8\n+struct igc_host_mng_command_info {\n+\tstruct igc_host_mng_command_header command_header;\n+\tu8 command_data[IGC_HI_MAX_MNG_DATA_LENGTH];\n+};\n+\n+#include \"e1000_mac.h\"\n+#include \"e1000_phy.h\"\n+#include \"e1000_nvm.h\"\n+#include \"e1000_manage.h\"\n+\n+/* Function pointers for the MAC. */\n+struct igc_mac_operations {\n+\ts32  (*init_params)(struct igc_hw *hw);\n+\ts32  (*id_led_init)(struct igc_hw *hw);\n+\ts32  (*blink_led)(struct igc_hw *hw);\n+\tbool (*check_mng_mode)(struct igc_hw *hw);\n+\ts32  (*check_for_link)(struct igc_hw *hw);\n+\ts32  (*cleanup_led)(struct igc_hw *hw);\n+\tvoid (*clear_hw_cntrs)(struct igc_hw *hw);\n+\tvoid (*clear_vfta)(struct igc_hw *hw);\n+\ts32  (*get_bus_info)(struct igc_hw *hw);\n+\tvoid (*set_lan_id)(struct igc_hw *hw);\n+\ts32  (*get_link_up_info)(struct igc_hw *hw, u16 *speed, u16 *duplex);\n+\ts32  (*led_on)(struct igc_hw *hw);\n+\ts32  (*led_off)(struct igc_hw *hw);\n+\tvoid (*update_mc_addr_list)(struct igc_hw *hw,\n+\t\t\tu8 *mc_addr_list, u32 count);\n+\ts32  (*reset_hw)(struct igc_hw *hw);\n+\ts32  (*init_hw)(struct igc_hw *hw);\n+\tvoid (*shutdown_serdes)(struct igc_hw *hw);\n+\tvoid (*power_up_serdes)(struct igc_hw *hw);\n+\ts32  (*setup_link)(struct igc_hw *hw);\n+\ts32  (*setup_physical_interface)(struct igc_hw *hw);\n+\ts32  (*setup_led)(struct igc_hw *hw);\n+\tvoid (*write_vfta)(struct igc_hw *hw, u32 offset, u32 value);\n+\tvoid (*config_collision_dist)(struct igc_hw *hw);\n+\tint  (*rar_set)(struct igc_hw *hw, u8 *addr, u32 index);\n+\ts32  (*read_mac_addr)(struct igc_hw *hw);\n+\ts32  (*validate_mdi_setting)(struct igc_hw *hw);\n+\ts32  (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);\n+\tvoid (*release_swfw_sync)(struct igc_hw *hw, u16 mask);\n+};\n+\n+/* When to use various PHY register access functions:\n+ *\n+ *                 Func   Caller\n+ *   Function      Does   Does    When to use\n+ *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+ *   X_reg         L,P,A  n/a     for simple PHY reg accesses\n+ *   X_reg_locked  P,A    L       for multiple accesses of different regs\n+ *                                on different pages\n+ *   X_reg_page    A      L,P     for multiple accesses of different regs\n+ *                                on the same page\n+ *\n+ * Where X=[read|write], L=locking, P=sets page, A=register access\n+ *\n+ */\n+struct igc_phy_operations {\n+\ts32  (*init_params)(struct igc_hw *hw);\n+\ts32  (*acquire)(struct igc_hw *hw);\n+\ts32  (*cfg_on_link_up)(struct igc_hw *hw);\n+\ts32  (*check_polarity)(struct igc_hw *hw);\n+\ts32  (*check_reset_block)(struct igc_hw *hw);\n+\ts32  (*commit)(struct igc_hw *hw);\n+\ts32  (*force_speed_duplex)(struct igc_hw *hw);\n+\ts32  (*get_cfg_done)(struct igc_hw *hw);\n+\ts32  (*get_cable_length)(struct igc_hw *hw);\n+\ts32  (*get_info)(struct igc_hw *hw);\n+\ts32  (*set_page)(struct igc_hw *hw, u16 page);\n+\ts32  (*read_reg)(struct igc_hw *hw, u32 offset, u16 *data);\n+\ts32  (*read_reg_locked)(struct igc_hw *hw, u32 offset, u16 *data);\n+\ts32  (*read_reg_page)(struct igc_hw *hw, u32 offset, u16 *data);\n+\tvoid (*release)(struct igc_hw *hw);\n+\ts32  (*reset)(struct igc_hw *hw);\n+\ts32  (*set_d0_lplu_state)(struct igc_hw *hw, bool active);\n+\ts32  (*set_d3_lplu_state)(struct igc_hw *hw, bool active);\n+\ts32  (*write_reg)(struct igc_hw *hw, u32 offset, u16 data);\n+\ts32  (*write_reg_locked)(struct igc_hw *hw, u32 offset, u16 data);\n+\ts32  (*write_reg_page)(struct igc_hw *hw, u32 offset, u16 data);\n+\tvoid (*power_up)(struct igc_hw *hw);\n+\tvoid (*power_down)(struct igc_hw *hw);\n+\ts32 (*read_i2c_byte)(struct igc_hw *hw, u8 byte_offset,\n+\t\t\tu8 dev_addr, u8 *data);\n+\ts32 (*write_i2c_byte)(struct igc_hw *hw, u8 byte_offset,\n+\t\t\tu8 dev_addr, u8 data);\n+};\n+\n+/* Function pointers for the NVM. */\n+struct igc_nvm_operations {\n+\ts32  (*init_params)(struct igc_hw *hw);\n+\ts32  (*acquire)(struct igc_hw *hw);\n+\ts32  (*read)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);\n+\tvoid (*release)(struct igc_hw *hw);\n+\tvoid (*reload)(struct igc_hw *hw);\n+\ts32  (*update)(struct igc_hw *hw);\n+\ts32  (*valid_led_default)(struct igc_hw *hw, u16 *data);\n+\ts32  (*validate)(struct igc_hw *hw);\n+\ts32  (*write)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);\n+};\n+\n+struct igc_info {\n+\ts32 (*get_invariants)(struct igc_hw *hw);\n+\tstruct igc_mac_operations *mac_ops;\n+\tconst struct igc_phy_operations *phy_ops;\n+\tstruct igc_nvm_operations *nvm_ops;\n+};\n+\n+extern const struct igc_info igc_i225_info;\n+\n+struct igc_mac_info {\n+\tstruct igc_mac_operations ops;\n+\tu8 addr[ETH_ADDR_LEN];\n+\tu8 perm_addr[ETH_ADDR_LEN];\n+\n+\tenum igc_mac_type type;\n+\n+\tu32 collision_delta;\n+\tu32 ledctl_default;\n+\tu32 ledctl_mode1;\n+\tu32 ledctl_mode2;\n+\tu32 mc_filter_type;\n+\tu32 tx_packet_delta;\n+\tu32 txcw;\n+\n+\tu16 current_ifs_val;\n+\tu16 ifs_max_val;\n+\tu16 ifs_min_val;\n+\tu16 ifs_ratio;\n+\tu16 ifs_step_size;\n+\tu16 mta_reg_count;\n+\tu16 uta_reg_count;\n+\n+\t/* Maximum size of the MTA register table in all supported adapters */\n+#define MAX_MTA_REG 128\n+\tu32 mta_shadow[MAX_MTA_REG];\n+\tu16 rar_entry_count;\n+\n+\tu8  forced_speed_duplex;\n+\n+\tbool adaptive_ifs;\n+\tbool has_fwsm;\n+\tbool arc_subsystem_valid;\n+\tbool asf_firmware_present;\n+\tbool autoneg;\n+\tbool autoneg_failed;\n+\tbool get_link_status;\n+\tbool in_ifs_mode;\n+\tbool report_tx_early;\n+\tenum igc_serdes_link_state serdes_link_state;\n+\tbool serdes_has_link;\n+\tbool tx_pkt_filtering;\n+};\n+\n+struct igc_phy_info {\n+\tstruct igc_phy_operations ops;\n+\tenum igc_phy_type type;\n+\n+\tenum igc_1000t_rx_status local_rx;\n+\tenum igc_1000t_rx_status remote_rx;\n+\tenum igc_ms_type ms_type;\n+\tenum igc_ms_type original_ms_type;\n+\tenum igc_rev_polarity cable_polarity;\n+\tenum igc_smart_speed smart_speed;\n+\n+\tu32 addr;\n+\tu32 id;\n+\tu32 reset_delay_us; /* in usec */\n+\tu32 revision;\n+\n+\tenum igc_media_type media_type;\n+\n+\tu16 autoneg_advertised;\n+\tu16 autoneg_mask;\n+\tu16 cable_length;\n+\tu16 max_cable_length;\n+\tu16 min_cable_length;\n+\n+\tu8 mdix;\n+\n+\tbool disable_polarity_correction;\n+\tbool is_mdix;\n+\tbool polarity_correction;\n+\tbool speed_downgraded;\n+\tbool autoneg_wait_to_complete;\n+};\n+\n+struct igc_nvm_info {\n+\tstruct igc_nvm_operations ops;\n+\tenum igc_nvm_type type;\n+\tenum igc_nvm_override override;\n+\n+\tu32 flash_bank_size;\n+\tu32 flash_base_addr;\n+\n+\tu16 word_size;\n+\tu16 delay_usec;\n+\tu16 address_bits;\n+\tu16 opcode_bits;\n+\tu16 page_size;\n+};\n+\n+struct igc_bus_info {\n+\tenum igc_bus_type type;\n+\tenum igc_bus_speed speed;\n+\tenum igc_bus_width width;\n+\n+\tu16 func;\n+\tu16 pci_cmd_word;\n+};\n+\n+struct igc_fc_info {\n+\tu32 high_water;  /* Flow control high-water mark */\n+\tu32 low_water;  /* Flow control low-water mark */\n+\tu16 pause_time;  /* Flow control pause timer */\n+\tu16 refresh_time;  /* Flow control refresh timer */\n+\tbool send_xon;  /* Flow control send XON */\n+\tbool strict_ieee;  /* Strict IEEE mode */\n+\tenum igc_fc_mode current_mode;  /* FC mode in effect */\n+\tenum igc_fc_mode requested_mode;  /* FC mode requested by caller */\n+};\n+\n+struct igc_mbx_operations {\n+\ts32 (*init_params)(struct igc_hw *hw);\n+};\n+\n+struct igc_mbx_stats {\n+\tu32 msgs_tx;\n+\tu32 msgs_rx;\n+\n+\tu32 acks;\n+\tu32 reqs;\n+\tu32 rsts;\n+};\n+\n+struct igc_mbx_info {\n+\tstruct igc_mbx_operations ops;\n+\tstruct igc_mbx_stats stats;\n+\tu32 timeout;\n+\tu32 usec_delay;\n+\tu16 size;\n+};\n+\n+struct igc_dev_spec_82541 {\n+\tenum igc_dsp_config dsp_config;\n+\tenum igc_ffe_config ffe_config;\n+\tu16 spd_default;\n+\tbool phy_init_script;\n+};\n+\n+struct igc_dev_spec_82542 {\n+\tbool dma_fairness;\n+};\n+\n+struct igc_dev_spec_82543 {\n+\tu32  tbi_compatibility;\n+\tbool dma_fairness;\n+\tbool init_phy_disabled;\n+};\n+\n+struct igc_dev_spec_82571 {\n+\tbool laa_is_present;\n+\tu32 smb_counter;\n+\tIGC_MUTEX swflag_mutex;\n+};\n+\n+struct igc_dev_spec_80003es2lan {\n+\tbool  mdic_wa_enable;\n+};\n+\n+struct igc_shadow_ram {\n+\tu16  value;\n+\tbool modified;\n+};\n+\n+#define IGC_SHADOW_RAM_WORDS\t\t2048\n+\n+/* I218 PHY Ultra Low Power (ULP) states */\n+enum igc_ulp_state {\n+\tigc_ulp_state_unknown,\n+\tigc_ulp_state_off,\n+\tigc_ulp_state_on,\n+};\n+\n+struct igc_dev_spec_ich8lan {\n+\tbool kmrn_lock_loss_workaround_enabled;\n+\tstruct igc_shadow_ram shadow_ram[IGC_SHADOW_RAM_WORDS];\n+\tIGC_MUTEX nvm_mutex;\n+\tIGC_MUTEX swflag_mutex;\n+\tbool nvm_k1_enabled;\n+\tbool disable_k1_off;\n+\tbool eee_disable;\n+\tu16 eee_lp_ability;\n+\tenum igc_ulp_state ulp_state;\n+\tbool ulp_capability_disabled;\n+\tbool during_suspend_flow;\n+\tbool during_dpg_exit;\n+\tu16 lat_enc;\n+\tu16 max_ltr_enc;\n+\tbool smbus_disable;\n+};\n+\n+struct igc_dev_spec_82575 {\n+\tbool sgmii_active;\n+\tbool global_device_reset;\n+\tbool eee_disable;\n+\tbool module_plugged;\n+\tbool clear_semaphore_once;\n+\tu32 mtu;\n+\tstruct sfp_igc_flags eth_flags;\n+\tu8 media_port;\n+\tbool media_changed;\n+};\n+\n+struct igc_dev_spec_vf {\n+\tu32 vf_number;\n+\tu32 v2p_mailbox;\n+};\n+\n+struct igc_dev_spec_i225 {\n+\tbool global_device_reset;\n+\tbool eee_disable;\n+\tbool clear_semaphore_once;\n+\tbool module_plugged;\n+\tu8 media_port;\n+\tbool mas_capable;\n+\tu32 mtu;\n+};\n+\n+struct igc_hw {\n+\tvoid *back;\n+\n+\tu8 *hw_addr;\n+\tu8 *flash_address;\n+\tunsigned long io_base;\n+\n+\tstruct igc_mac_info  mac;\n+\tstruct igc_fc_info   fc;\n+\tstruct igc_phy_info  phy;\n+\tstruct igc_nvm_info  nvm;\n+\tstruct igc_bus_info  bus;\n+\tstruct igc_mbx_info mbx;\n+\tstruct igc_host_mng_dhcp_cookie mng_cookie;\n+\n+\tunion {\n+\t\tstruct igc_dev_spec_82541 _82541;\n+\t\tstruct igc_dev_spec_82542 _82542;\n+\t\tstruct igc_dev_spec_82543 _82543;\n+\t\tstruct igc_dev_spec_82571 _82571;\n+\t\tstruct igc_dev_spec_80003es2lan _80003es2lan;\n+\t\tstruct igc_dev_spec_ich8lan ich8lan;\n+\t\tstruct igc_dev_spec_82575 _82575;\n+\t\tstruct igc_dev_spec_vf vf;\n+\t\tstruct igc_dev_spec_i225 _i225;\n+\t} dev_spec;\n+\n+\tu16 device_id;\n+\tu16 subsystem_vendor_id;\n+\tu16 subsystem_device_id;\n+\tu16 vendor_id;\n+\n+\tu8  revision_id;\n+};\n+\n+#include \"e1000_82571.h\"\n+#include \"e1000_ich8lan.h\"\n+#include \"e1000_82575.h\"\n+#include \"e1000_i225.h\"\n+#include \"e1000_base.h\"\n+\n+/* These functions must be implemented by drivers */\n+void igc_pci_clear_mwi(struct igc_hw *hw);\n+void igc_pci_set_mwi(struct igc_hw *hw);\n+s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n+s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);\n+void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);\n+void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_i225.c b/drivers/net/igc/base/e1000_i225.c\nnew file mode 100644\nindex 0000000..b1a90e4\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_i225.c\n@@ -0,0 +1,1378 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+static s32 igc_init_nvm_params_i225(struct igc_hw *hw);\n+static s32 igc_init_mac_params_i225(struct igc_hw *hw);\n+static s32 igc_init_phy_params_i225(struct igc_hw *hw);\n+static s32 igc_reset_hw_i225(struct igc_hw *hw);\n+static s32 igc_acquire_nvm_i225(struct igc_hw *hw);\n+static void igc_release_nvm_i225(struct igc_hw *hw);\n+static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw);\n+static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t\t  u16 *data);\n+static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw);\n+static s32 igc_valid_led_default_i225(struct igc_hw *hw, u16 *data);\n+\n+/**\n+ *  igc_init_nvm_params_i225 - Init NVM func ptrs.\n+ *  @hw: pointer to the HW structure\n+ **/\n+static s32 igc_init_nvm_params_i225(struct igc_hw *hw)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 eecd = IGC_READ_REG(hw, IGC_EECD);\n+\tu16 size;\n+\n+\tDEBUGFUNC(\"igc_init_nvm_params_i225\");\n+\n+\tsize = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>\n+\t\t     IGC_EECD_SIZE_EX_SHIFT);\n+\t/*\n+\t * Added to a constant, \"size\" becomes the left-shift value\n+\t * for setting word_size.\n+\t */\n+\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n+\n+\t/* Just in case size is out of range, cap it to the largest\n+\t * EEPROM size supported\n+\t */\n+\tif (size > 15)\n+\t\tsize = 15;\n+\n+\tnvm->word_size = 1 << size;\n+\tnvm->opcode_bits = 8;\n+\tnvm->delay_usec = 1;\n+\tnvm->type = igc_nvm_eeprom_spi;\n+\n+\n+\tnvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;\n+\tnvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?\n+\t\t\t    16 : 8;\n+\n+\tif (nvm->word_size == (1 << 15))\n+\t\tnvm->page_size = 128;\n+\n+\tnvm->ops.acquire = igc_acquire_nvm_i225;\n+\tnvm->ops.release = igc_release_nvm_i225;\n+\tnvm->ops.valid_led_default = igc_valid_led_default_i225;\n+\tif (igc_get_flash_presence_i225(hw)) {\n+\t\thw->nvm.type = igc_nvm_flash_hw;\n+\t\tnvm->ops.read    = igc_read_nvm_srrd_i225;\n+\t\tnvm->ops.write   = igc_write_nvm_srwr_i225;\n+\t\tnvm->ops.validate = igc_validate_nvm_checksum_i225;\n+\t\tnvm->ops.update   = igc_update_nvm_checksum_i225;\n+\t} else {\n+\t\thw->nvm.type = igc_nvm_invm;\n+\t\tnvm->ops.write    = igc_null_write_nvm;\n+\t\tnvm->ops.validate = igc_null_ops_generic;\n+\t\tnvm->ops.update   = igc_null_ops_generic;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_init_mac_params_i225 - Init MAC func ptrs.\n+ *  @hw: pointer to the HW structure\n+ **/\n+static s32 igc_init_mac_params_i225(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tstruct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;\n+\n+\tDEBUGFUNC(\"igc_init_mac_params_i225\");\n+\n+\t/* Initialize function pointer */\n+\tigc_init_mac_ops_generic(hw);\n+\n+\t/* Set media type */\n+\thw->phy.media_type = igc_media_type_copper;\n+\t/* Set mta register count */\n+\tmac->mta_reg_count = 128;\n+\t/* Set rar entry count */\n+\tmac->rar_entry_count = IGC_RAR_ENTRIES_BASE;\n+\n+\t/* reset */\n+\tmac->ops.reset_hw = igc_reset_hw_i225;\n+\t/* hw initialization */\n+\tmac->ops.init_hw = igc_init_hw_i225;\n+\t/* link setup */\n+\tmac->ops.setup_link = igc_setup_link_generic;\n+\t/* check for link */\n+\tmac->ops.check_for_link = igc_check_for_link_i225;\n+\t/* link info */\n+\tmac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic;\n+\t/* acquire SW_FW sync */\n+\tmac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;\n+\t/* release SW_FW sync */\n+\tmac->ops.release_swfw_sync = igc_release_swfw_sync_i225;\n+\n+\t/* Allow a single clear of the SW semaphore on I225 */\n+\tdev_spec->clear_semaphore_once = true;\n+\tmac->ops.setup_physical_interface = igc_setup_copper_link_i225;\n+\n+\t/* Set if part includes ASF firmware */\n+\tmac->asf_firmware_present = true;\n+\n+\t/* multicast address update */\n+\tmac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic;\n+\n+\tmac->ops.write_vfta = igc_write_vfta_generic;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_init_phy_params_i225 - Init PHY func ptrs.\n+ *  @hw: pointer to the HW structure\n+ **/\n+static s32 igc_init_phy_params_i225(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu32 ctrl_ext;\n+\n+\tDEBUGFUNC(\"igc_init_phy_params_i225\");\n+\n+\tphy->ops.read_i2c_byte = igc_read_i2c_byte_generic;\n+\tphy->ops.write_i2c_byte = igc_write_i2c_byte_generic;\n+\n+\tif (hw->phy.media_type != igc_media_type_copper) {\n+\t\tphy->type = igc_phy_none;\n+\t\tgoto out;\n+\t}\n+\n+\tphy->ops.power_up   = igc_power_up_phy_copper;\n+\tphy->ops.power_down = igc_power_down_phy_copper_base;\n+\n+\tphy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;\n+\n+\tphy->reset_delay_us\t= 100;\n+\n+\tphy->ops.acquire\t= igc_acquire_phy_base;\n+\tphy->ops.check_reset_block = igc_check_reset_block_generic;\n+\tphy->ops.commit\t\t= igc_phy_sw_reset_generic;\n+\tphy->ops.release\t= igc_release_phy_base;\n+\n+\tctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);\n+\n+\t/* Make sure the PHY is in a good state. Several people have reported\n+\t * firmware leaving the PHY's page select register set to something\n+\t * other than the default of zero, which causes the PHY ID read to\n+\t * access something other than the intended register.\n+\t */\n+\tret_val = hw->phy.ops.reset(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tIGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);\n+\tphy->ops.read_reg = igc_read_phy_reg_gpy;\n+\tphy->ops.write_reg = igc_write_phy_reg_gpy;\n+\n+\tret_val = igc_get_phy_id(hw);\n+\t/* Verify phy id and set remaining function pointers */\n+\tswitch (phy->id) {\n+\tcase I225_I_PHY_ID:\n+\t\tphy->type\t\t= igc_phy_i225;\n+\t\tphy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225;\n+\t\tphy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225;\n+\t\t/* TODO - complete with GPY PHY information */\n+\t\tbreak;\n+\tdefault:\n+\t\tret_val = -IGC_ERR_PHY;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_reset_hw_i225 - Reset hardware\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This resets the hardware into a known state.\n+ **/\n+static s32 igc_reset_hw_i225(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_reset_hw_i225\");\n+\n+\t/*\n+\t * Prevent the PCI-E bus from sticking if there is no TLP connection\n+\t * on the last TLP read/write transaction when MAC is reset.\n+\t */\n+\tret_val = igc_disable_pcie_master_generic(hw);\n+\tif (ret_val)\n+\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n+\n+\tDEBUGOUT(\"Masking off all interrupts\\n\");\n+\tIGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);\n+\n+\tIGC_WRITE_REG(hw, IGC_RCTL, 0);\n+\tIGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tmsec_delay(10);\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\n+\tDEBUGOUT(\"Issuing a global reset to MAC\\n\");\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_RST);\n+\n+\tret_val = igc_get_auto_rd_done_generic(hw);\n+\tif (ret_val) {\n+\t\t/*\n+\t\t * When auto config read does not complete, do not\n+\t\t * return with an error. This can happen in situations\n+\t\t * where there is no eeprom and prevents getting link.\n+\t\t */\n+\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n+\t}\n+\n+\t/* Clear any pending interrupt events. */\n+\tIGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);\n+\tIGC_READ_REG(hw, IGC_ICR);\n+\n+\t/* Install any alternate MAC address into RAR0 */\n+\tret_val = igc_check_alt_mac_addr_generic(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_acquire_nvm_i225 - Request for access to EEPROM\n+ * @hw: pointer to the HW structure\n+ *\n+ * Acquire the necessary semaphores for exclusive access to the EEPROM.\n+ * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n+ * Return successful if access grant bit set, else clear the request for\n+ * EEPROM access and return -IGC_ERR_NVM (-1).\n+ */\n+static s32 igc_acquire_nvm_i225(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_acquire_nvm_i225\");\n+\n+\tret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_release_nvm_i225 - Release exclusive access to EEPROM\n+ * @hw: pointer to the HW structure\n+ *\n+ * Stop any current commands to the EEPROM and clear the EEPROM request bit,\n+ * then release the semaphores acquired.\n+ */\n+static void igc_release_nvm_i225(struct igc_hw *hw)\n+{\n+\tDEBUGFUNC(\"igc_release_nvm_i225\");\n+\n+\tigc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);\n+}\n+\n+/* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore\n+ * @hw: pointer to the HW structure\n+ * @mask: specifies which semaphore to acquire\n+ *\n+ * Acquire the SW/FW semaphore to access the PHY or NVM.  The mask\n+ * will also specify which port we're acquiring the lock for.\n+ */\n+s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)\n+{\n+\tu32 swfw_sync;\n+\tu32 swmask = mask;\n+\tu32 fwmask = mask << 16;\n+\ts32 ret_val = IGC_SUCCESS;\n+\ts32 i = 0, timeout = 200; /* FIXME: find real value to use here */\n+\n+\tDEBUGFUNC(\"igc_acquire_swfw_sync_i225\");\n+\n+\twhile (i < timeout) {\n+\t\tif (igc_get_hw_semaphore_i225(hw)) {\n+\t\t\tret_val = -IGC_ERR_SWFW_SYNC;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tswfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);\n+\t\tif (!(swfw_sync & (fwmask | swmask)))\n+\t\t\tbreak;\n+\n+\t\t/* Firmware currently using resource (fwmask)\n+\t\t * or other software thread using resource (swmask)\n+\t\t */\n+\t\tigc_put_hw_semaphore_generic(hw);\n+\t\tmsec_delay_irq(5);\n+\t\ti++;\n+\t}\n+\n+\tif (i == timeout) {\n+\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n+\t\tret_val = -IGC_ERR_SWFW_SYNC;\n+\t\tgoto out;\n+\t}\n+\n+\tswfw_sync |= swmask;\n+\tIGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);\n+\n+\tigc_put_hw_semaphore_generic(hw);\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/* igc_release_swfw_sync_i225 - Release SW/FW semaphore\n+ * @hw: pointer to the HW structure\n+ * @mask: specifies which semaphore to acquire\n+ *\n+ * Release the SW/FW semaphore used to access the PHY or NVM.  The mask\n+ * will also specify which port we're releasing the lock for.\n+ */\n+void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)\n+{\n+\tu32 swfw_sync;\n+\n+\tDEBUGFUNC(\"igc_release_swfw_sync_i225\");\n+\n+\twhile (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS)\n+\t\t; /* Empty */\n+\n+\tswfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);\n+\tswfw_sync &= ~mask;\n+\tIGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);\n+\n+\tigc_put_hw_semaphore_generic(hw);\n+}\n+\n+/*\n+ * igc_setup_copper_link_i225 - Configure copper link settings\n+ * @hw: pointer to the HW structure\n+ *\n+ * Configures the link for auto-neg or forced speed and duplex.  Then we check\n+ * for link, once link is established calls to configure collision distance\n+ * and flow control are called.\n+ */\n+s32 igc_setup_copper_link_i225(struct igc_hw *hw)\n+{\n+\tu32 phpm_reg;\n+\ts32 ret_val;\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_setup_copper_link_i225\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tctrl |= IGC_CTRL_SLU;\n+\tctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\n+\tphpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM);\n+\tphpm_reg &= ~IGC_I225_PHPM_GO_LINKD;\n+\tIGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg);\n+\n+\tret_val = igc_setup_copper_link_generic(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_get_hw_semaphore_i225 - Acquire hardware semaphore\n+ * @hw: pointer to the HW structure\n+ *\n+ * Acquire the HW semaphore to access the PHY or NVM\n+ */\n+static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)\n+{\n+\tu32 swsm;\n+\ts32 timeout = hw->nvm.word_size + 1;\n+\ts32 i = 0;\n+\n+\tDEBUGFUNC(\"igc_get_hw_semaphore_i225\");\n+\n+\t/* Get the SW semaphore */\n+\twhile (i < timeout) {\n+\t\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\t\tif (!(swsm & IGC_SWSM_SMBI))\n+\t\t\tbreak;\n+\n+\t\tusec_delay(50);\n+\t\ti++;\n+\t}\n+\n+\tif (i == timeout) {\n+\t\t/* In rare circumstances, the SW semaphore may already be held\n+\t\t * unintentionally. Clear the semaphore once before giving up.\n+\t\t */\n+\t\tif (hw->dev_spec._i225.clear_semaphore_once) {\n+\t\t\thw->dev_spec._i225.clear_semaphore_once = false;\n+\t\t\tigc_put_hw_semaphore_generic(hw);\n+\t\t\tfor (i = 0; i < timeout; i++) {\n+\t\t\t\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\t\t\t\tif (!(swsm & IGC_SWSM_SMBI))\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tusec_delay(50);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* If we do not have the semaphore here, we have to give up. */\n+\t\tif (i == timeout) {\n+\t\t\tDEBUGOUT(\"Driver can't access device -\\n\");\n+\t\t\tDEBUGOUT(\"SMBI bit is set.\\n\");\n+\t\t\treturn -IGC_ERR_NVM;\n+\t\t}\n+\t}\n+\n+\t/* Get the FW semaphore. */\n+\tfor (i = 0; i < timeout; i++) {\n+\t\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\t\tIGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);\n+\n+\t\t/* Semaphore acquired if bit latched */\n+\t\tif (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)\n+\t\t\tbreak;\n+\n+\t\tusec_delay(50);\n+\t}\n+\n+\tif (i == timeout) {\n+\t\t/* Release semaphores */\n+\t\tigc_put_hw_semaphore_generic(hw);\n+\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of word in the Shadow Ram to read\n+ * @words: number of words to read\n+ * @data: word read from the Shadow Ram\n+ *\n+ * Reads a 16 bit word from the Shadow Ram using the EERD register.\n+ * Uses necessary synchronization semaphores.\n+ */\n+s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t     u16 *data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\tu16 i, count;\n+\n+\tDEBUGFUNC(\"igc_read_nvm_srrd_i225\");\n+\n+\t/* We cannot hold synchronization semaphores for too long,\n+\t * because of forceful takeover procedure. However it is more efficient\n+\t * to read in bursts than synchronizing access for each word.\n+\t */\n+\tfor (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {\n+\t\tcount = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?\n+\t\t\tIGC_EERD_EEWR_MAX_COUNT : (words - i);\n+\t\tif (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {\n+\t\t\tstatus = igc_read_nvm_eerd(hw, offset, count,\n+\t\t\t\t\t\t     data + i);\n+\t\t\thw->nvm.ops.release(hw);\n+\t\t} else {\n+\t\t\tstatus = IGC_ERR_SWFW_SYNC;\n+\t\t}\n+\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR\n+ * @hw: pointer to the HW structure\n+ * @offset: offset within the Shadow RAM to be written to\n+ * @words: number of words to write\n+ * @data: 16 bit word(s) to be written to the Shadow RAM\n+ *\n+ * Writes data to Shadow RAM at offset using EEWR register.\n+ *\n+ * If igc_update_nvm_checksum is not called after this function , the\n+ * data will not be committed to FLASH and also Shadow RAM will most likely\n+ * contain an invalid checksum.\n+ *\n+ * If error code is returned, data and Shadow RAM may be inconsistent - buffer\n+ * partially written.\n+ */\n+s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t      u16 *data)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\tu16 i, count;\n+\n+\tDEBUGFUNC(\"igc_write_nvm_srwr_i225\");\n+\n+\t/* We cannot hold synchronization semaphores for too long,\n+\t * because of forceful takeover procedure. However it is more efficient\n+\t * to write in bursts than synchronizing access for each word.\n+\t */\n+\tfor (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {\n+\t\tcount = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?\n+\t\t\tIGC_EERD_EEWR_MAX_COUNT : (words - i);\n+\t\tif (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {\n+\t\t\tstatus = __igc_write_nvm_srwr(hw, offset, count,\n+\t\t\t\t\t\t\tdata + i);\n+\t\t\thw->nvm.ops.release(hw);\n+\t\t} else {\n+\t\t\tstatus = IGC_ERR_SWFW_SYNC;\n+\t\t}\n+\n+\t\tif (status != IGC_SUCCESS)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR\n+ * @hw: pointer to the HW structure\n+ * @offset: offset within the Shadow Ram to be written to\n+ * @words: number of words to write\n+ * @data: 16 bit word(s) to be written to the Shadow Ram\n+ *\n+ * Writes data to Shadow Ram at offset using EEWR register.\n+ *\n+ * If igc_update_nvm_checksum is not called after this function , the\n+ * Shadow Ram will most likely contain an invalid checksum.\n+ */\n+static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t\t  u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 i, k, eewr = 0;\n+\tu32 attempts = 100000;\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"__igc_write_nvm_srwr\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * too many words for the offset, and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\tret_val = -IGC_ERR_NVM;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < words; i++) {\n+\t\teewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |\n+\t\t\t(data[i] << IGC_NVM_RW_REG_DATA) |\n+\t\t\tIGC_NVM_RW_REG_START;\n+\n+\t\tIGC_WRITE_REG(hw, IGC_SRWR, eewr);\n+\n+\t\tfor (k = 0; k < attempts; k++) {\n+\t\t\tif (IGC_NVM_RW_REG_DONE &\n+\t\t\t    IGC_READ_REG(hw, IGC_SRWR)) {\n+\t\t\t\tret_val = IGC_SUCCESS;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tusec_delay(5);\n+\t\t}\n+\n+\t\tif (ret_val != IGC_SUCCESS) {\n+\t\t\tDEBUGOUT(\"Shadow RAM write EEWR timed out\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/* igc_read_invm_version_i225 - Reads iNVM version and image type\n+ * @hw: pointer to the HW structure\n+ * @invm_ver: version structure for the version read\n+ *\n+ * Reads iNVM version and image type.\n+ */\n+s32 igc_read_invm_version_i225(struct igc_hw *hw,\n+\t\t\t\t struct igc_fw_version *invm_ver)\n+{\n+\tu32 *record = NULL;\n+\tu32 *next_record = NULL;\n+\tu32 i = 0;\n+\tu32 invm_dword = 0;\n+\tu32 invm_blocks = IGC_INVM_SIZE - (IGC_INVM_ULT_BYTES_SIZE /\n+\t\t\t\t\t     IGC_INVM_RECORD_SIZE_IN_BYTES);\n+\tu32 buffer[IGC_INVM_SIZE];\n+\ts32 status = -IGC_ERR_INVM_VALUE_NOT_FOUND;\n+\tu16 version = 0;\n+\n+\tDEBUGFUNC(\"igc_read_invm_version_i225\");\n+\n+\t/* Read iNVM memory */\n+\tfor (i = 0; i < IGC_INVM_SIZE; i++) {\n+\t\tinvm_dword = IGC_READ_REG(hw, IGC_INVM_DATA_REG(i));\n+\t\tbuffer[i] = invm_dword;\n+\t}\n+\n+\t/* Read version number */\n+\tfor (i = 1; i < invm_blocks; i++) {\n+\t\trecord = &buffer[invm_blocks - i];\n+\t\tnext_record = &buffer[invm_blocks - i + 1];\n+\n+\t\t/* Check if we have first version location used */\n+\t\tif (i == 1 && (*record & IGC_INVM_VER_FIELD_ONE) == 0) {\n+\t\t\tversion = 0;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Check if we have second version location used */\n+\t\telse if ((i == 1) &&\n+\t\t\t ((*record & IGC_INVM_VER_FIELD_TWO) == 0)) {\n+\t\t\tversion = (*record & IGC_INVM_VER_FIELD_ONE) >> 3;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Check if we have odd version location\n+\t\t * used and it is the last one used\n+\t\t */\n+\t\telse if ((((*record & IGC_INVM_VER_FIELD_ONE) == 0) &&\n+\t\t\t  ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&\n+\t\t\t   (i != 1))) {\n+\t\t\tversion = (*next_record & IGC_INVM_VER_FIELD_TWO)\n+\t\t\t\t  >> 13;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Check if we have even version location\n+\t\t * used and it is the last one used\n+\t\t */\n+\t\telse if (((*record & IGC_INVM_VER_FIELD_TWO) == 0) &&\n+\t\t\t ((*record & 0x3) == 0)) {\n+\t\t\tversion = (*record & IGC_INVM_VER_FIELD_ONE) >> 3;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (status == IGC_SUCCESS) {\n+\t\tinvm_ver->invm_major = (version & IGC_INVM_MAJOR_MASK)\n+\t\t\t\t\t>> IGC_INVM_MAJOR_SHIFT;\n+\t\tinvm_ver->invm_minor = version & IGC_INVM_MINOR_MASK;\n+\t}\n+\t/* Read Image Type */\n+\tfor (i = 1; i < invm_blocks; i++) {\n+\t\trecord = &buffer[invm_blocks - i];\n+\t\tnext_record = &buffer[invm_blocks - i + 1];\n+\n+\t\t/* Check if we have image type in first location used */\n+\t\tif (i == 1 && (*record & IGC_INVM_IMGTYPE_FIELD) == 0) {\n+\t\t\tinvm_ver->invm_img_type = 0;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Check if we have image type in first location used */\n+\t\telse if ((((*record & 0x3) == 0) &&\n+\t\t\t  ((*record & IGC_INVM_IMGTYPE_FIELD) == 0)) ||\n+\t\t\t    ((((*record & 0x3) != 0) && (i != 1)))) {\n+\t\t\tinvm_ver->invm_img_type =\n+\t\t\t\t(*next_record & IGC_INVM_IMGTYPE_FIELD) >> 23;\n+\t\t\tstatus = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+/* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum\n+ * @hw: pointer to the HW structure\n+ *\n+ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n+ * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n+ */\n+s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw)\n+{\n+\ts32 status = IGC_SUCCESS;\n+\ts32 (*read_op_ptr)(struct igc_hw *hw, u16 offset,\n+\t\t\tu16 count, u16 *data);\n+\n+\tDEBUGFUNC(\"igc_validate_nvm_checksum_i225\");\n+\n+\tif (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {\n+\t\t/* Replace the read function with semaphore grabbing with\n+\t\t * the one that skips this for a while.\n+\t\t * We have semaphore taken already here.\n+\t\t */\n+\t\tread_op_ptr = hw->nvm.ops.read;\n+\t\thw->nvm.ops.read = igc_read_nvm_eerd;\n+\n+\t\tstatus = igc_validate_nvm_checksum_generic(hw);\n+\n+\t\t/* Revert original read operation. */\n+\t\thw->nvm.ops.read = read_op_ptr;\n+\n+\t\thw->nvm.ops.release(hw);\n+\t} else {\n+\t\tstatus = IGC_ERR_SWFW_SYNC;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/* igc_update_nvm_checksum_i225 - Update EEPROM checksum\n+ * @hw: pointer to the HW structure\n+ *\n+ * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n+ * up to the checksum.  Then calculates the EEPROM checksum and writes the\n+ * value to the EEPROM. Next commit EEPROM data onto the Flash.\n+ */\n+s32 igc_update_nvm_checksum_i225(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 checksum = 0;\n+\tu16 i, nvm_data;\n+\n+\tDEBUGFUNC(\"igc_update_nvm_checksum_i225\");\n+\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n+\t * not continue or we could be in for a very long wait while every\n+\t * EEPROM read fails\n+\t */\n+\tret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);\n+\tif (ret_val != IGC_SUCCESS) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {\n+\t\t/* Do not use hw->nvm.ops.write, hw->nvm.ops.read\n+\t\t * because we do not want to take the synchronization\n+\t\t * semaphores twice here.\n+\t\t */\n+\n+\t\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n+\t\t\tret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);\n+\t\t\tif (ret_val) {\n+\t\t\t\thw->nvm.ops.release(hw);\n+\t\t\t\tDEBUGOUT(\"NVM Read Error while updating\\n\");\n+\t\t\t\tDEBUGOUT(\"checksum.\\n\");\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t\tchecksum += nvm_data;\n+\t\t}\n+\t\tchecksum = (u16)NVM_SUM - checksum;\n+\t\tret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,\n+\t\t\t\t\t\t &checksum);\n+\t\tif (ret_val != IGC_SUCCESS) {\n+\t\t\thw->nvm.ops.release(hw);\n+\t\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\thw->nvm.ops.release(hw);\n+\n+\t\tret_val = igc_update_flash_i225(hw);\n+\t} else {\n+\t\tret_val = IGC_ERR_SWFW_SYNC;\n+\t}\n+out:\n+\treturn ret_val;\n+}\n+\n+/* igc_get_flash_presence_i225 - Check if flash device is detected.\n+ * @hw: pointer to the HW structure\n+ */\n+bool igc_get_flash_presence_i225(struct igc_hw *hw)\n+{\n+\tu32 eec = 0;\n+\tbool ret_val = false;\n+\n+\tDEBUGFUNC(\"igc_get_flash_presence_i225\");\n+\n+\teec = IGC_READ_REG(hw, IGC_EECD);\n+\n+\tif (eec & IGC_EECD_FLASH_DETECTED_I225)\n+\t\tret_val = true;\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst\n+ * Counter in FLSWCNT register.\n+ *\n+ * @hw: pointer to the HW structure\n+ * @burst_counter: size in bytes of the Flash burst to read or write\n+ */\n+s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,\n+\t\t\t\t\t    u32 burst_counter)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_set_flsw_flash_burst_counter_i225\");\n+\n+\t/* Validate input data */\n+\tif (burst_counter < IGC_I225_SHADOW_RAM_SIZE) {\n+\t\t/* Write FLSWCNT - burst counter */\n+\t\tIGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter);\n+\t} else {\n+\t\tret_val = IGC_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_write_erase_flash_command_i225 - write/erase to a sector\n+ * region on a given address.\n+ *\n+ * @hw: pointer to the HW structure\n+ * @opcode: opcode to be used for the write command\n+ * @address: the offset to write into the FLASH image\n+ */\n+s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,\n+\t\t\t\t\t u32 address)\n+{\n+\tu32 flswctl = 0;\n+\ts32 timeout = IGC_NVM_GRANT_ATTEMPTS;\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_write_erase_flash_command_i225\");\n+\n+\tflswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);\n+\t/* Polling done bit on FLSWCTL register */\n+\twhile (timeout) {\n+\t\tif (flswctl & IGC_FLSWCTL_DONE)\n+\t\t\tbreak;\n+\t\tusec_delay(5);\n+\t\tflswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);\n+\t\ttimeout--;\n+\t}\n+\n+\tif (!timeout) {\n+\t\tDEBUGOUT(\"Flash transaction was not done\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\t/* Build and issue command on FLSWCTL register */\n+\tflswctl = address | opcode;\n+\tIGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl);\n+\n+\t/* Check if issued command is valid on FLSWCTL register */\n+\tflswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);\n+\tif (!(flswctl & IGC_FLSWCTL_CMDV)) {\n+\t\tDEBUGOUT(\"Write flash command failed\\n\");\n+\t\tret_val = IGC_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_update_flash_i225 - Commit EEPROM to the flash\n+ * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC\n+ * register makes the FW load the internal shadow RAM into the flash.\n+ * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0\n+ * then FW is not active so the SW is responsible shadow RAM dump.\n+ *\n+ * @hw: pointer to the HW structure\n+ */\n+s32 igc_update_flash_i225(struct igc_hw *hw)\n+{\n+\tu16 current_offset_data = 0;\n+\tu32 block_sw_protect = 1;\n+\tu16 base_address = 0x0;\n+\tu32 i, fw_valid_bit;\n+\tu16 current_offset;\n+\ts32 ret_val = 0;\n+\tu32 flup;\n+\n+\tDEBUGFUNC(\"igc_update_flash_i225\");\n+\n+\tblock_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) &\n+\t\t\t\t\t  IGC_FLSECU_BLK_SW_ACCESS_I225;\n+\tfw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) &\n+\t\t\t\t      IGC_FWSM_FW_VALID_I225;\n+\tif (fw_valid_bit) {\n+\t\tret_val = igc_pool_flash_update_done_i225(hw);\n+\t\tif (ret_val == -IGC_ERR_NVM) {\n+\t\t\tDEBUGOUT(\"Flash update time out\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tflup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, flup);\n+\n+\t\tret_val = igc_pool_flash_update_done_i225(hw);\n+\t\tif (ret_val == IGC_SUCCESS)\n+\t\t\tDEBUGOUT(\"Flash update complete\\n\");\n+\t\telse\n+\t\t\tDEBUGOUT(\"Flash update time out\\n\");\n+\t} else if (!block_sw_protect) {\n+\t\t/* FW is not active and security protection is disabled.\n+\t\t * therefore, SW is in charge of shadow RAM dump.\n+\t\t * Check which sector is valid. if sector 0 is valid,\n+\t\t * base address remains 0x0. otherwise, sector 1 is\n+\t\t * valid and it's base address is 0x1000\n+\t\t */\n+\t\tif (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225)\n+\t\t\tbase_address = 0x1000;\n+\n+\t\t/* Valid sector erase */\n+\t\tret_val = igc_write_erase_flash_command_i225(hw,\n+\t\t\t\t\t\t  IGC_I225_ERASE_CMD_OPCODE,\n+\t\t\t\t\t\t  base_address);\n+\t\tif (!ret_val) {\n+\t\t\tDEBUGOUT(\"Sector erase failed\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tcurrent_offset = base_address;\n+\n+\t\t/* Write */\n+\t\tfor (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) {\n+\t\t\t/* Set burst write length */\n+\t\t\tret_val = igc_set_flsw_flash_burst_counter_i225(hw,\n+\t\t\t\t\t\t\t\t\t  0x2);\n+\t\t\tif (ret_val != IGC_SUCCESS)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* Set address and opcode */\n+\t\t\tret_val = igc_write_erase_flash_command_i225(hw,\n+\t\t\t\t\t\tIGC_I225_WRITE_CMD_OPCODE,\n+\t\t\t\t\t\t2 * current_offset);\n+\t\t\tif (ret_val != IGC_SUCCESS)\n+\t\t\t\tbreak;\n+\n+\t\t\tret_val = igc_read_nvm_eerd(hw, current_offset,\n+\t\t\t\t\t\t      1, &current_offset_data);\n+\t\t\tif (ret_val) {\n+\t\t\t\tDEBUGOUT(\"Failed to read from EEPROM\\n\");\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\n+\t\t\t/* Write CurrentOffseData to FLSWDATA register */\n+\t\t\tIGC_WRITE_REG(hw, IGC_I225_FLSWDATA,\n+\t\t\t\t\tcurrent_offset_data);\n+\t\t\tcurrent_offset++;\n+\n+\t\t\t/* Wait till operation has finished */\n+\t\t\tret_val = igc_poll_eerd_eewr_done(hw,\n+\t\t\t\t\t\tIGC_NVM_POLL_READ);\n+\t\t\tif (ret_val)\n+\t\t\t\tbreak;\n+\n+\t\t\tusec_delay(1000);\n+\t\t}\n+\t}\n+out:\n+\treturn ret_val;\n+}\n+\n+/* igc_pool_flash_update_done_i225 - Pool FLUDONE status.\n+ * @hw: pointer to the HW structure\n+ */\n+s32 igc_pool_flash_update_done_i225(struct igc_hw *hw)\n+{\n+\ts32 ret_val = -IGC_ERR_NVM;\n+\tu32 i, reg;\n+\n+\tDEBUGFUNC(\"igc_pool_flash_update_done_i225\");\n+\n+\tfor (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) {\n+\t\treg = IGC_READ_REG(hw, IGC_EECD);\n+\t\tif (reg & IGC_EECD_FLUDONE_I225) {\n+\t\t\tret_val = IGC_SUCCESS;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusec_delay(5);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.\n+ * @hw: pointer to the HW structure\n+ * @link: bool indicating link status\n+ *\n+ * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC\n+ * settings, otherwise specify that there is no LTR requirement.\n+ */\n+static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)\n+{\n+\tu16 speed, duplex;\n+\tu32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;\n+\ts32 size;\n+\n+\tDEBUGFUNC(\"igc_set_ltr_i225\");\n+\n+\t/* If we do not have link, LTR thresholds are zero. */\n+\tif (link) {\n+\t\thw->mac.ops.get_link_up_info(hw, &speed, &duplex);\n+\n+\t\t/* Check if using copper interface with EEE enabled or if the\n+\t\t * link speed is 10 Mbps.\n+\t\t */\n+\t\tif (hw->phy.media_type == igc_media_type_copper &&\n+\t\t\t\t!hw->dev_spec._i225.eee_disable &&\n+\t\t\t\tspeed != SPEED_10) {\n+\t\t\t/* EEE enabled, so send LTRMAX threshold. */\n+\t\t\tltrc = IGC_READ_REG(hw, IGC_LTRC) |\n+\t\t\t\tIGC_LTRC_EEEMS_EN;\n+\t\t\tIGC_WRITE_REG(hw, IGC_LTRC, ltrc);\n+\n+\t\t\t/* Calculate tw_system (nsec). */\n+\t\t\tif (speed == SPEED_100)\n+\t\t\t\ttw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) &\n+\t\t\t\t\tIGC_TW_SYSTEM_100_MASK) >>\n+\t\t\t\t\tIGC_TW_SYSTEM_100_SHIFT) * 500;\n+\t\t\telse\n+\t\t\t\ttw_system = (IGC_READ_REG(hw, IGC_EEE_SU) &\n+\t\t\t\t\tIGC_TW_SYSTEM_1000_MASK) * 500;\n+\t\t} else {\n+\t\t\ttw_system = 0;\n+\t\t}\n+\n+\t\t/* Get the Rx packet buffer size. */\n+\t\tsize = IGC_READ_REG(hw, IGC_RXPBS) &\n+\t\t\tIGC_RXPBS_SIZE_I225_MASK;\n+\n+\t\t/* Calculations vary based on DMAC settings. */\n+\t\tif (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) {\n+\t\t\tsize -= (IGC_READ_REG(hw, IGC_DMACR) &\n+\t\t\t\t IGC_DMACR_DMACTHR_MASK) >>\n+\t\t\t\t IGC_DMACR_DMACTHR_SHIFT;\n+\t\t\t/* Convert size to bits. */\n+\t\t\tsize *= 1024 * 8;\n+\t\t} else {\n+\t\t\t/* Convert size to bytes, subtract the MTU, and then\n+\t\t\t * convert the size to bits.\n+\t\t\t */\n+\t\t\tsize *= 1024;\n+\t\t\tsize -= hw->dev_spec._i225.mtu;\n+\t\t\tsize *= 8;\n+\t\t}\n+\n+\t\tif (size < 0) {\n+\t\t\tDEBUGOUT1(\"Invalid effective Rx buffer size %d\\n\",\n+\t\t\t\t  size);\n+\t\t\treturn -IGC_ERR_CONFIG;\n+\t\t}\n+\n+\t\t/* Calculate the thresholds. Since speed is in Mbps, simplify\n+\t\t * the calculation by multiplying size/speed by 1000 for result\n+\t\t * to be in nsec before dividing by the scale in nsec. Set the\n+\t\t * scale such that the LTR threshold fits in the register.\n+\t\t */\n+\t\tltr_min = (1000 * size) / speed;\n+\t\tltr_max = ltr_min + tw_system;\n+\t\tscale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :\n+\t\t\t    IGC_LTRMINV_SCALE_32768;\n+\t\tscale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :\n+\t\t\t    IGC_LTRMAXV_SCALE_32768;\n+\t\tltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;\n+\t\tltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;\n+\n+\t\t/* Only write the LTR thresholds if they differ from before. */\n+\t\tltrv = IGC_READ_REG(hw, IGC_LTRMINV);\n+\t\tif (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {\n+\t\t\tltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |\n+\t\t\t      (scale_min << IGC_LTRMINV_SCALE_SHIFT);\n+\t\t\tIGC_WRITE_REG(hw, IGC_LTRMINV, ltrv);\n+\t\t}\n+\n+\t\tltrv = IGC_READ_REG(hw, IGC_LTRMAXV);\n+\t\tif (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {\n+\t\t\tltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |\n+\t\t\t      (scale_min << IGC_LTRMAXV_SCALE_SHIFT);\n+\t\t\tIGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv);\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/* igc_check_for_link_i225 - Check for link\n+ * @hw: pointer to the HW structure\n+ *\n+ * Checks to see of the link status of the hardware has changed.  If a\n+ * change in link status has been detected, then we read the PHY registers\n+ * to get the current speed/duplex if link exists.\n+ */\n+s32 igc_check_for_link_i225(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val;\n+\tbool link = false;\n+\n+\tDEBUGFUNC(\"igc_check_for_link_i225\");\n+\n+\t/* We only want to go out to the PHY registers to see if\n+\t * Auto-Neg has completed and/or if our link status has\n+\t * changed.  The get_link_status flag is set upon receiving\n+\t * a Link Status Change or Rx Sequence Error interrupt.\n+\t */\n+\tif (!mac->get_link_status) {\n+\t\tret_val = IGC_SUCCESS;\n+\t\tgoto out;\n+\t}\n+\n+\t/* First we want to see if the MII Status Register reports\n+\t * link.  If so, then we want to get the current speed/duplex\n+\t * of the PHY.\n+\t */\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tif (!link)\n+\t\tgoto out; /* No link detected */\n+\n+\tmac->get_link_status = false;\n+\n+\t/* Check if there was DownShift, must be checked\n+\t * immediately after link-up\n+\t */\n+\tigc_check_downshift_generic(hw);\n+\n+\t/* If we are forcing speed/duplex, then we simply return since\n+\t * we have already determined whether we have link or not.\n+\t */\n+\tif (!mac->autoneg)\n+\t\tgoto out;\n+\n+\t/* Auto-Neg is enabled.  Auto Speed Detection takes care\n+\t * of MAC speed/duplex configuration.  So we only need to\n+\t * configure Collision Distance in the MAC.\n+\t */\n+\tmac->ops.config_collision_dist(hw);\n+\n+\t/* Configure Flow Control now that Auto-Neg has completed.\n+\t * First, we need to restore the desired flow control\n+\t * settings because we may have had to re-autoneg with a\n+\t * different link partner.\n+\t */\n+\tret_val = igc_config_fc_after_link_up_generic(hw);\n+\tif (ret_val)\n+\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n+out:\n+\t/* Now that we are aware of our link settings, we can set the LTR\n+\t * thresholds.\n+\t */\n+\tret_val = igc_set_ltr_i225(hw, link);\n+\n+\treturn ret_val;\n+}\n+\n+/* igc_init_function_pointers_i225 - Init func ptrs.\n+ * @hw: pointer to the HW structure\n+ *\n+ * Called to initialize all function pointers and parameters.\n+ */\n+void igc_init_function_pointers_i225(struct igc_hw *hw)\n+{\n+\tigc_init_mac_ops_generic(hw);\n+\tigc_init_phy_ops_generic(hw);\n+\tigc_init_nvm_ops_generic(hw);\n+\thw->mac.ops.init_params = igc_init_mac_params_i225;\n+\thw->nvm.ops.init_params = igc_init_nvm_params_i225;\n+\thw->phy.ops.init_params = igc_init_phy_params_i225;\n+}\n+\n+/* igc_valid_led_default_i225 - Verify a valid default LED config\n+ * @hw: pointer to the HW structure\n+ * @data: pointer to the NVM (EEPROM)\n+ *\n+ * Read the EEPROM for the current default LED configuration.  If the\n+ * LED configuration is not valid, set to a valid LED configuration.\n+ */\n+static s32 igc_valid_led_default_i225(struct igc_hw *hw, u16 *data)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_valid_led_default_i225\");\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {\n+\t\tswitch (hw->phy.media_type) {\n+\t\tcase igc_media_type_internal_serdes:\n+\t\t\t*data = ID_LED_DEFAULT_I225_SERDES;\n+\t\t\tbreak;\n+\t\tcase igc_media_type_copper:\n+\t\tdefault:\n+\t\t\t*data = ID_LED_DEFAULT_I225;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+out:\n+\treturn ret_val;\n+}\n+\n+/* igc_get_cfg_done_i225 - Read config done bit\n+ * @hw: pointer to the HW structure\n+ *\n+ * Read the management control register for the config done bit for\n+ * completion status.  NOTE: silicon which is EEPROM-less will fail trying\n+ * to read the config done bit, so an error is *ONLY* logged and returns\n+ * IGC_SUCCESS.  If we were to return with error, EEPROM-less silicon\n+ * would not be able to be reset or change link.\n+ */\n+static s32 igc_get_cfg_done_i225(struct igc_hw *hw)\n+{\n+\ts32 timeout = PHY_CFG_TIMEOUT;\n+\tu32 mask = IGC_NVM_CFG_DONE_PORT_0;\n+\n+\tDEBUGFUNC(\"igc_get_cfg_done_i225\");\n+\n+\twhile (timeout) {\n+\t\tif (IGC_READ_REG(hw, IGC_EEMNGCTL_I225) & mask)\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t\ttimeout--;\n+\t}\n+\tif (!timeout)\n+\t\tDEBUGOUT(\"MNG configuration cycle has not completed.\\n\");\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/* igc_init_hw_i225 - Init hw for I225\n+ * @hw: pointer to the HW structure\n+ *\n+ * Called to initialize hw for i225 hw family.\n+ */\n+s32 igc_init_hw_i225(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_init_hw_i225\");\n+\n+\thw->phy.ops.get_cfg_done = igc_get_cfg_done_i225;\n+\tret_val = igc_init_hw_base(hw);\n+\treturn ret_val;\n+}\n+\n+/*\n+ * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state\n+ * @hw: pointer to the HW structure\n+ * @active: true to enable LPLU, false to disable\n+ *\n+ * Note: since I225 does not actually support LPLU, this function\n+ * simply enables/disables 1G and 2.5G speeds in D0.\n+ */\n+s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active)\n+{\n+\tu32 data;\n+\n+\tDEBUGFUNC(\"igc_set_d0_lplu_state_i225\");\n+\n+\tdata = IGC_READ_REG(hw, IGC_I225_PHPM);\n+\n+\tif (active) {\n+\t\tdata |= IGC_I225_PHPM_DIS_1000;\n+\t\tdata |= IGC_I225_PHPM_DIS_2500;\n+\t} else {\n+\t\tdata &= ~IGC_I225_PHPM_DIS_1000;\n+\t\tdata &= ~IGC_I225_PHPM_DIS_2500;\n+\t}\n+\n+\tIGC_WRITE_REG(hw, IGC_I225_PHPM, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/*\n+ * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state\n+ * @hw: pointer to the HW structure\n+ * @active: true to enable LPLU, false to disable\n+ *\n+ * Note: since I225 does not actually support LPLU, this function\n+ * simply enables/disables 100M, 1G and 2.5G speeds in D3.\n+ */\n+s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active)\n+{\n+\tu32 data;\n+\n+\tDEBUGFUNC(\"igc_set_d3_lplu_state_i225\");\n+\n+\tdata = IGC_READ_REG(hw, IGC_I225_PHPM);\n+\n+\tif (active) {\n+\t\tdata |= IGC_I225_PHPM_DIS_100_D3;\n+\t\tdata |= IGC_I225_PHPM_DIS_1000_D3;\n+\t\tdata |= IGC_I225_PHPM_DIS_2500_D3;\n+\t} else {\n+\t\tdata &= ~IGC_I225_PHPM_DIS_100_D3;\n+\t\tdata &= ~IGC_I225_PHPM_DIS_1000_D3;\n+\t\tdata &= ~IGC_I225_PHPM_DIS_2500_D3;\n+\t}\n+\n+\tIGC_WRITE_REG(hw, IGC_I225_PHPM, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_eee_i225 - Enable/disable EEE support\n+ *  @hw: pointer to the HW structure\n+ *  @adv2p5G: boolean flag enabling 2.5G EEE advertisement\n+ *  @adv1G: boolean flag enabling 1G EEE advertisement\n+ *  @adv100M: boolean flag enabling 100M EEE advertisement\n+ *\n+ *  Enable/disable EEE based on setting in dev_spec structure.\n+ *\n+ **/\n+s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,\n+\t\t       bool adv100M)\n+{\n+\tu32 ipcnfg, eeer;\n+\n+\tDEBUGFUNC(\"igc_set_eee_i225\");\n+\n+\tif (hw->mac.type != igc_i225 ||\n+\t    hw->phy.media_type != igc_media_type_copper)\n+\t\tgoto out;\n+\tipcnfg = IGC_READ_REG(hw, IGC_IPCNFG);\n+\teeer = IGC_READ_REG(hw, IGC_EEER);\n+\n+\t/* enable or disable per user setting */\n+\tif (!(hw->dev_spec._i225.eee_disable)) {\n+\t\tu32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU);\n+\n+\t\tif (adv100M)\n+\t\t\tipcnfg |= IGC_IPCNFG_EEE_100M_AN;\n+\t\telse\n+\t\t\tipcnfg &= ~IGC_IPCNFG_EEE_100M_AN;\n+\n+\t\tif (adv1G)\n+\t\t\tipcnfg |= IGC_IPCNFG_EEE_1G_AN;\n+\t\telse\n+\t\t\tipcnfg &= ~IGC_IPCNFG_EEE_1G_AN;\n+\n+\t\tif (adv2p5G)\n+\t\t\tipcnfg |= IGC_IPCNFG_EEE_2_5G_AN;\n+\t\telse\n+\t\t\tipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN;\n+\n+\t\teeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |\n+\t\t\tIGC_EEER_LPI_FC);\n+\n+\t\t/* This bit should not be set in normal operation. */\n+\t\tif (eee_su & IGC_EEE_SU_LPI_CLK_STP)\n+\t\t\tDEBUGOUT(\"LPI Clock Stop Bit should not be set!\\n\");\n+\t} else {\n+\t\tipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN |\n+\t\t\tIGC_IPCNFG_EEE_100M_AN);\n+\t\teeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |\n+\t\t\tIGC_EEER_LPI_FC);\n+\t}\n+\tIGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg);\n+\tIGC_WRITE_REG(hw, IGC_EEER, eeer);\n+\tIGC_READ_REG(hw, IGC_IPCNFG);\n+\tIGC_READ_REG(hw, IGC_EEER);\n+out:\n+\n+\treturn IGC_SUCCESS;\n+}\ndiff --git a/drivers/net/igc/base/e1000_i225.h b/drivers/net/igc/base/e1000_i225.h\nnew file mode 100644\nindex 0000000..bae75ac\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_i225.h\n@@ -0,0 +1,110 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_I225_H_\n+#define _IGC_I225_H_\n+\n+bool igc_get_flash_presence_i225(struct igc_hw *hw);\n+s32 igc_update_flash_i225(struct igc_hw *hw);\n+s32 igc_update_nvm_checksum_i225(struct igc_hw *hw);\n+s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw);\n+s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset,\n+\t\t\t      u16 words, u16 *data);\n+s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset,\n+\t\t\t     u16 words, u16 *data);\n+s32 igc_read_invm_version_i225(struct igc_hw *hw,\n+\t\t\t\t struct igc_fw_version *invm_ver);\n+s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,\n+\t\t\t\t\t    u32 burst_counter);\n+s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,\n+\t\t\t\t\t u32 address);\n+s32 igc_check_for_link_i225(struct igc_hw *hw);\n+s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);\n+void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);\n+s32 igc_init_hw_i225(struct igc_hw *hw);\n+s32 igc_setup_copper_link_i225(struct igc_hw *hw);\n+s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active);\n+s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active);\n+s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,\n+\t\t       bool adv100M);\n+\n+#define ID_LED_DEFAULT_I225\t\t((ID_LED_OFF1_ON2  << 8) | \\\n+\t\t\t\t\t (ID_LED_DEF1_DEF2 <<  4) | \\\n+\t\t\t\t\t (ID_LED_OFF1_OFF2))\n+#define ID_LED_DEFAULT_I225_SERDES\t((ID_LED_DEF1_DEF2 << 8) | \\\n+\t\t\t\t\t (ID_LED_DEF1_DEF2 <<  4) | \\\n+\t\t\t\t\t (ID_LED_OFF1_ON2))\n+\n+/* NVM offset defaults for I225 devices */\n+#define NVM_INIT_CTRL_2_DEFAULT_I225\t0X7243\n+#define NVM_INIT_CTRL_4_DEFAULT_I225\t0x00C1\n+#define NVM_LED_1_CFG_DEFAULT_I225\t0x0184\n+#define NVM_LED_0_2_CFG_DEFAULT_I225\t0x200C\n+\n+#define IGC_MRQC_ENABLE_RSS_4Q\t\t0x00000002\n+#define IGC_MRQC_ENABLE_VMDQ\t\t\t0x00000003\n+#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q\t\t0x00000005\n+#define IGC_MRQC_RSS_FIELD_IPV4_UDP\t\t0x00400000\n+#define IGC_MRQC_RSS_FIELD_IPV6_UDP\t\t0x00800000\n+#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX\t0x01000000\n+#define IGC_I225_SHADOW_RAM_SIZE\t\t4096\n+#define IGC_I225_ERASE_CMD_OPCODE\t\t0x02000000\n+#define IGC_I225_WRITE_CMD_OPCODE\t\t0x01000000\n+#define IGC_FLSWCTL_DONE\t\t\t0x40000000\n+#define IGC_FLSWCTL_CMDV\t\t\t0x10000000\n+\n+/* SRRCTL bit definitions */\n+#define IGC_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n+#define IGC_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n+#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n+#define IGC_SRRCTL_DESCTYPE_MASK\t\t0x0E000000\n+#define IGC_SRRCTL_DROP_EN\t\t\t0x80000000\n+#define IGC_SRRCTL_BSIZEPKT_MASK\t\t0x0000007F\n+#define IGC_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n+\n+#define IGC_RXDADV_RSSTYPE_MASK\t0x0000000F\n+#define IGC_RXDADV_RSSTYPE_SHIFT\t12\n+#define IGC_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n+#define IGC_RXDADV_HDRBUFLEN_SHIFT\t5\n+#define IGC_RXDADV_SPLITHEADER_EN\t0x00001000\n+#define IGC_RXDADV_SPH\t\t0x8000\n+#define IGC_RXDADV_STAT_TS\t\t0x10000 /* Pkt was time stamped */\n+#define IGC_RXDADV_ERR_HBO\t\t0x00800000\n+\n+/* RSS Hash results */\n+#define IGC_RXDADV_RSSTYPE_NONE\t0x00000000\n+#define IGC_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n+#define IGC_RXDADV_RSSTYPE_IPV4\t0x00000002\n+#define IGC_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n+#define IGC_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n+#define IGC_RXDADV_RSSTYPE_IPV6\t0x00000005\n+#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n+#define IGC_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n+#define IGC_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n+#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n+\n+/* RSS Packet Types as indicated in the receive descriptor */\n+#define IGC_RXDADV_PKTTYPE_ILMASK\t0x000000F0\n+#define IGC_RXDADV_PKTTYPE_TLMASK\t0x00000F00\n+#define IGC_RXDADV_PKTTYPE_NONE\t0x00000000\n+#define IGC_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPV4 hdr present */\n+#define IGC_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPV4 hdr + extensions */\n+#define IGC_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPV6 hdr present */\n+#define IGC_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPV6 hdr + extensions */\n+#define IGC_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n+#define IGC_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n+#define IGC_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n+#define IGC_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n+\n+#define IGC_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n+#define IGC_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n+#define IGC_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n+#define IGC_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n+#define IGC_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n+#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_ich8lan.h b/drivers/net/igc/base/e1000_ich8lan.h\nnew file mode 100644\nindex 0000000..608716c\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_ich8lan.h\n@@ -0,0 +1,296 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_ICH8LAN_H_\n+#define _IGC_ICH8LAN_H_\n+\n+#define ICH_FLASH_GFPREG\t\t0x0000\n+#define ICH_FLASH_HSFSTS\t\t0x0004\n+#define ICH_FLASH_HSFCTL\t\t0x0006\n+#define ICH_FLASH_FADDR\t\t\t0x0008\n+#define ICH_FLASH_FDATA0\t\t0x0010\n+\n+/* Requires up to 10 seconds when MNG might be accessing part. */\n+#define ICH_FLASH_READ_COMMAND_TIMEOUT\t10000000\n+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT\t10000000\n+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT\t10000000\n+#define ICH_FLASH_LINEAR_ADDR_MASK\t0x00FFFFFF\n+#define ICH_FLASH_CYCLE_REPEAT_COUNT\t10\n+\n+#define ICH_CYCLE_READ\t\t\t0\n+#define ICH_CYCLE_WRITE\t\t\t2\n+#define ICH_CYCLE_ERASE\t\t\t3\n+\n+#define FLASH_GFPREG_BASE_MASK\t\t0x1FFF\n+#define FLASH_SECTOR_ADDR_SHIFT\t\t12\n+\n+#define ICH_FLASH_SEG_SIZE_256\t\t256\n+#define ICH_FLASH_SEG_SIZE_4K\t\t4096\n+#define ICH_FLASH_SEG_SIZE_8K\t\t8192\n+#define ICH_FLASH_SEG_SIZE_64K\t\t65536\n+\n+#define IGC_ICH_FWSM_RSPCIPHY\t0x00000040 /* Reset PHY on PCI Reset */\n+/* FW established a valid mode */\n+#define IGC_ICH_FWSM_FW_VALID\t0x00008000\n+#define IGC_ICH_FWSM_PCIM2PCI\t0x01000000 /* ME PCIm-to-PCI active */\n+#define IGC_ICH_FWSM_PCIM2PCI_COUNT\t2000\n+\n+#define IGC_ICH_MNG_IAMT_MODE\t\t0x2\n+\n+#define IGC_FWSM_WLOCK_MAC_MASK\t0x0380\n+#define IGC_FWSM_WLOCK_MAC_SHIFT\t7\n+#define IGC_FWSM_ULP_CFG_DONE\t\t0x00000400  /* Low power cfg done */\n+\n+/* Shared Receive Address Registers */\n+#define IGC_SHRAL_PCH_LPT(_i)\t\t(0x05408 + ((_i) * 8))\n+#define IGC_SHRAH_PCH_LPT(_i)\t\t(0x0540C + ((_i) * 8))\n+\n+#define IGC_H2ME\t\t0x05B50    /* Host to ME */\n+#define IGC_H2ME_ULP\t\t0x00000800 /* ULP Indication Bit */\n+#define IGC_H2ME_ENFORCE_SETTINGS\t0x00001000 /* Enforce Settings */\n+\n+#define ID_LED_DEFAULT_ICH8LAN\t((ID_LED_DEF1_DEF2 << 12) | \\\n+\t\t\t\t (ID_LED_OFF1_OFF2 <<  8) | \\\n+\t\t\t\t (ID_LED_OFF1_ON2  <<  4) | \\\n+\t\t\t\t (ID_LED_DEF1_DEF2))\n+\n+#define IGC_ICH_NVM_SIG_WORD\t\t0x13\n+#define IGC_ICH_NVM_SIG_MASK\t\t0xC000\n+#define IGC_ICH_NVM_VALID_SIG_MASK\t0xC0\n+#define IGC_ICH_NVM_SIG_VALUE\t\t0x80\n+\n+#define IGC_ICH8_LAN_INIT_TIMEOUT\t1500\n+\n+/* FEXT register bit definition */\n+#define IGC_FEXT_PHY_CABLE_DISCONNECTED\t0x00000004\n+\n+#define IGC_FEXTNVM_SW_CONFIG\t\t1\n+#define IGC_FEXTNVM_SW_CONFIG_ICH8M\t(1 << 27) /* different on ICH8M */\n+\n+#define IGC_FEXTNVM3_PHY_CFG_COUNTER_MASK\t0x0C000000\n+#define IGC_FEXTNVM3_PHY_CFG_COUNTER_50MSEC\t0x08000000\n+\n+#define IGC_FEXTNVM4_BEACON_DURATION_MASK\t0x7\n+#define IGC_FEXTNVM4_BEACON_DURATION_8USEC\t0x7\n+#define IGC_FEXTNVM4_BEACON_DURATION_16USEC\t0x3\n+\n+#define IGC_FEXTNVM6_REQ_PLL_CLK\t0x00000100\n+#define IGC_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION\t0x00000200\n+#define IGC_FEXTNVM6_K1_OFF_ENABLE\t0x80000000\n+/* bit for disabling packet buffer read */\n+#define IGC_FEXTNVM7_DISABLE_PB_READ\t0x00040000\n+#define IGC_FEXTNVM7_SIDE_CLK_UNGATE\t0x00000004\n+#define IGC_FEXTNVM7_DISABLE_SMB_PERST\t0x00000020\n+#define IGC_FEXTNVM9_IOSFSB_CLKGATE_DIS\t0x00000800\n+#define IGC_FEXTNVM9_IOSFSB_CLKREQ_DIS\t0x00001000\n+#define IGC_FEXTNVM11_DISABLE_PB_READ\t\t0x00000200\n+#define IGC_FEXTNVM11_DISABLE_MULR_FIX\t0x00002000\n+\n+/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */\n+#define IGC_RXDCTL_THRESH_UNIT_DESC\t0x01000000\n+\n+#define NVM_SIZE_MULTIPLIER 4096  /*multiplier for NVMS field*/\n+#define IGC_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/\n+#define IGC_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */\n+#define IGC_TARC0_CB_MULTIQ_3_REQ\t0x30000000\n+#define IGC_TARC0_CB_MULTIQ_2_REQ\t0x20000000\n+#define PCIE_ICH8_SNOOP_ALL\tPCIE_NO_SNOOP_ALL\n+\n+#define IGC_ICH_RAR_ENTRIES\t7\n+#define IGC_PCH2_RAR_ENTRIES\t5 /* RAR[0], SHRA[0-3] */\n+#define IGC_PCH_LPT_RAR_ENTRIES\t12 /* RAR[0], SHRA[0-10] */\n+\n+#define PHY_PAGE_SHIFT\t\t5\n+#define PHY_REG(page, reg)\t(((page) << PHY_PAGE_SHIFT) | \\\n+\t\t\t\t ((reg) & MAX_PHY_REG_ADDRESS))\n+#define IGP3_KMRN_DIAG\tPHY_REG(770, 19) /* KMRN Diagnostic */\n+#define IGP3_VR_CTRL\tPHY_REG(776, 18) /* Voltage Regulator Control */\n+\n+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS\t\t0x0002\n+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK\t0x0300\n+#define IGP3_VR_CTRL_MODE_SHUTDOWN\t\t0x0200\n+\n+/* PHY Wakeup Registers and defines */\n+#define BM_PORT_GEN_CFG\t\tPHY_REG(BM_PORT_CTRL_PAGE, 17)\n+#define BM_RCTL\t\t\tPHY_REG(BM_WUC_PAGE, 0)\n+#define BM_WUC\t\t\tPHY_REG(BM_WUC_PAGE, 1)\n+#define BM_WUFC\t\t\tPHY_REG(BM_WUC_PAGE, 2)\n+#define BM_WUS\t\t\tPHY_REG(BM_WUC_PAGE, 3)\n+#define BM_RAR_L(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))\n+#define BM_RAR_M(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))\n+#define BM_RAR_H(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))\n+#define BM_RAR_CTRL(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))\n+#define BM_MTA(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))\n+\n+#define BM_RCTL_UPE\t\t0x0001 /* Unicast Promiscuous Mode */\n+#define BM_RCTL_MPE\t\t0x0002 /* Multicast Promiscuous Mode */\n+#define BM_RCTL_MO_SHIFT\t3      /* Multicast Offset Shift */\n+#define BM_RCTL_MO_MASK\t\t(3 << 3) /* Multicast Offset Mask */\n+#define BM_RCTL_BAM\t\t0x0020 /* Broadcast Accept Mode */\n+#define BM_RCTL_PMCF\t\t0x0040 /* Pass MAC Control Frames */\n+#define BM_RCTL_RFCE\t\t0x0080 /* Rx Flow Control Enable */\n+\n+#define HV_LED_CONFIG\t\tPHY_REG(768, 30) /* LED Configuration */\n+#define HV_MUX_DATA_CTRL\tPHY_REG(776, 16)\n+#define HV_MUX_DATA_CTRL_GEN_TO_MAC\t0x0400\n+#define HV_MUX_DATA_CTRL_FORCE_SPEED\t0x0004\n+#define HV_STATS_PAGE\t778\n+/* Half-duplex collision counts */\n+#define HV_SCC_UPPER\tPHY_REG(HV_STATS_PAGE, 16) /* Single Collision */\n+#define HV_SCC_LOWER\tPHY_REG(HV_STATS_PAGE, 17)\n+#define HV_ECOL_UPPER\tPHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */\n+#define HV_ECOL_LOWER\tPHY_REG(HV_STATS_PAGE, 19)\n+#define HV_MCC_UPPER\tPHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */\n+#define HV_MCC_LOWER\tPHY_REG(HV_STATS_PAGE, 21)\n+#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */\n+#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)\n+#define HV_COLC_UPPER\tPHY_REG(HV_STATS_PAGE, 25) /* Collision */\n+#define HV_COLC_LOWER\tPHY_REG(HV_STATS_PAGE, 26)\n+#define HV_DC_UPPER\tPHY_REG(HV_STATS_PAGE, 27) /* Defer Count */\n+#define HV_DC_LOWER\tPHY_REG(HV_STATS_PAGE, 28)\n+#define HV_TNCRS_UPPER\tPHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */\n+#define HV_TNCRS_LOWER\tPHY_REG(HV_STATS_PAGE, 30)\n+\n+#define IGC_FCRTV_PCH\t0x05F40 /* PCH Flow Control Refresh Timer Value */\n+\n+#define IGC_NVM_K1_CONFIG\t0x1B /* NVM K1 Config Word */\n+#define IGC_NVM_K1_ENABLE\t0x1  /* NVM Enable K1 bit */\n+#define K1_ENTRY_LATENCY\t0\n+#define K1_MIN_TIME\t\t1\n+\n+/* SMBus Control Phy Register */\n+#define CV_SMB_CTRL\t\tPHY_REG(769, 23)\n+#define CV_SMB_CTRL_FORCE_SMBUS\t0x0001\n+\n+/* I218 Ultra Low Power Configuration 1 Register */\n+#define I218_ULP_CONFIG1\t\tPHY_REG(779, 16)\n+#define I218_ULP_CONFIG1_START\t\t0x0001 /* Start auto ULP config */\n+#define I218_ULP_CONFIG1_IND\t\t0x0004 /* Pwr up from ULP indication */\n+#define I218_ULP_CONFIG1_STICKY_ULP\t0x0010 /* Set sticky ULP mode */\n+#define I218_ULP_CONFIG1_INBAND_EXIT\t0x0020 /* Inband on ULP exit */\n+#define I218_ULP_CONFIG1_WOL_HOST\t0x0040 /* WoL Host on ULP exit */\n+#define I218_ULP_CONFIG1_RESET_TO_SMBUS\t0x0100 /* Reset to SMBus mode */\n+/* enable ULP even if when phy powered down via lanphypc */\n+#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC\t0x0400\n+/* disable clear of sticky ULP on PERST */\n+#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST\t0x0800\n+#define I218_ULP_CONFIG1_DISABLE_SMB_PERST\t0x1000 /* Disable on PERST# */\n+\n+\n+/* SMBus Address Phy Register */\n+#define HV_SMB_ADDR\t\tPHY_REG(768, 26)\n+#define HV_SMB_ADDR_MASK\t0x007F\n+#define HV_SMB_ADDR_PEC_EN\t0x0200\n+#define HV_SMB_ADDR_VALID\t0x0080\n+#define HV_SMB_ADDR_FREQ_MASK\t\t0x1100\n+#define HV_SMB_ADDR_FREQ_LOW_SHIFT\t8\n+#define HV_SMB_ADDR_FREQ_HIGH_SHIFT\t12\n+\n+/* Strapping Option Register - RO */\n+#define IGC_STRAP\t\t\t0x0000C\n+#define IGC_STRAP_SMBUS_ADDRESS_MASK\t0x00FE0000\n+#define IGC_STRAP_SMBUS_ADDRESS_SHIFT\t17\n+#define IGC_STRAP_SMT_FREQ_MASK\t0x00003000\n+#define IGC_STRAP_SMT_FREQ_SHIFT\t12\n+\n+/* OEM Bits Phy Register */\n+#define HV_OEM_BITS\t\tPHY_REG(768, 25)\n+#define HV_OEM_BITS_LPLU\t0x0004 /* Low Power Link Up */\n+#define HV_OEM_BITS_GBE_DIS\t0x0040 /* Gigabit Disable */\n+#define HV_OEM_BITS_RESTART_AN\t0x0400 /* Restart Auto-negotiation */\n+\n+/* KMRN Mode Control */\n+#define HV_KMRN_MODE_CTRL\tPHY_REG(769, 16)\n+#define HV_KMRN_MDIO_SLOW\t0x0400\n+\n+/* KMRN FIFO Control and Status */\n+#define HV_KMRN_FIFO_CTRLSTA\t\t\tPHY_REG(770, 16)\n+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK\t0x7000\n+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT\t12\n+\n+/* PHY Power Management Control */\n+#define HV_PM_CTRL\t\tPHY_REG(770, 17)\n+#define HV_PM_CTRL_K1_CLK_REQ\t\t0x200\n+#define HV_PM_CTRL_K1_ENABLE\t\t0x4000\n+\n+#define I217_PLL_CLOCK_GATE_REG\tPHY_REG(772, 28)\n+#define I217_PLL_CLOCK_GATE_MASK\t0x07FF\n+\n+#define SW_FLAG_TIMEOUT\t\t1000 /* SW Semaphore flag timeout in ms */\n+\n+/* Inband Control */\n+#define I217_INBAND_CTRL\t\t\t\tPHY_REG(770, 18)\n+#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK\t0x3F00\n+#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT\t8\n+\n+/* Low Power Idle GPIO Control */\n+#define I217_LPI_GPIO_CTRL\t\t\tPHY_REG(772, 18)\n+#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI\t\t0x0800\n+\n+/* PHY Low Power Idle Control */\n+#define I82579_LPI_CTRL\t\t\t\tPHY_REG(772, 20)\n+#define I82579_LPI_CTRL_100_ENABLE\t\t0x2000\n+#define I82579_LPI_CTRL_1000_ENABLE\t\t0x4000\n+#define I82579_LPI_CTRL_ENABLE_MASK\t\t0x6000\n+\n+/* 82579 DFT Control */\n+#define I82579_DFT_CTRL\t\t\tPHY_REG(769, 20)\n+#define I82579_DFT_CTRL_GATE_PHY_RESET\t0x0040 /* Gate PHY Reset on MAC Reset */\n+\n+/* Extended Management Interface (EMI) Registers */\n+#define I82579_EMI_ADDR\t\t0x10\n+#define I82579_EMI_DATA\t\t0x11\n+#define I82579_LPI_UPDATE_TIMER\t0x4805 /* in 40ns units + 40 ns base value */\n+#define I82579_MSE_THRESHOLD\t0x084F /* 82579 Mean Square Error Threshold */\n+#define I82577_MSE_THRESHOLD\t0x0887 /* 82577 Mean Square Error Threshold */\n+#define I82579_MSE_LINK_DOWN\t0x2411 /* MSE count before dropping link */\n+#define I82579_RX_CONFIG\t\t0x3412 /* Receive configuration */\n+#define I82579_LPI_PLL_SHUT\t\t0x4412 /* LPI PLL Shut Enable */\n+#define I82579_EEE_PCS_STATUS\t\t0x182E\t/* IEEE MMD Register 3.1 >> 8 */\n+#define I82579_EEE_CAPABILITY\t\t0x0410 /* IEEE MMD Register 3.20 */\n+#define I82579_EEE_ADVERTISEMENT\t0x040E /* IEEE MMD Register 7.60 */\n+#define I82579_EEE_LP_ABILITY\t\t0x040F /* IEEE MMD Register 7.61 */\n+#define I82579_EEE_100_SUPPORTED\t(1 << 1) /* 100BaseTx EEE */\n+#define I82579_EEE_1000_SUPPORTED\t(1 << 2) /* 1000BaseTx EEE */\n+#define I82579_LPI_100_PLL_SHUT\t(1 << 2) /* 100M LPI PLL Shut Enabled */\n+#define I217_EEE_PCS_STATUS\t0x9401   /* IEEE MMD Register 3.1 */\n+#define I217_EEE_CAPABILITY\t0x8000   /* IEEE MMD Register 3.20 */\n+#define I217_EEE_ADVERTISEMENT\t0x8001   /* IEEE MMD Register 7.60 */\n+#define I217_EEE_LP_ABILITY\t0x8002   /* IEEE MMD Register 7.61 */\n+#define I217_RX_CONFIG\t\t0xB20C /* Receive configuration */\n+\n+#define IGC_EEE_RX_LPI_RCVD\t0x0400\t/* Tx LP idle received */\n+#define IGC_EEE_TX_LPI_RCVD\t0x0800\t/* Rx LP idle received */\n+\n+/* Intel Rapid Start Technology Support */\n+#define I217_PROXY_CTRL\t\tBM_PHY_REG(BM_WUC_PAGE, 70)\n+#define I217_PROXY_CTRL_AUTO_DISABLE\t0x0080\n+#define I217_CGFREG\t\t\tPHY_REG(772, 29)\n+#define I217_CGFREG_ENABLE_MTA_RESET\t0x0002\n+#define I217_MEMPWR\t\t\tPHY_REG(772, 26)\n+#define I217_MEMPWR_DISABLE_SMB_RELEASE\t0x0010\n+\n+/* Receive Address Initial CRC Calculation */\n+#define IGC_PCH_RAICC(_n)\t(0x05F50 + ((_n) * 4))\n+\n+#define IGC_PCI_VENDOR_ID_REGISTER\t0x00\n+\n+#define IGC_PCI_REVISION_ID_REG\t0x08\n+void igc_set_kmrn_lock_loss_workaround_ich8lan(struct igc_hw *hw,\n+\t\t\t\t\t\t bool state);\n+void igc_igp3_phy_powerdown_workaround_ich8lan(struct igc_hw *hw);\n+void igc_gig_downshift_workaround_ich8lan(struct igc_hw *hw);\n+void igc_suspend_workarounds_ich8lan(struct igc_hw *hw);\n+u32 igc_resume_workarounds_pchlan(struct igc_hw *hw);\n+s32 igc_configure_k1_ich8lan(struct igc_hw *hw, bool k1_enable);\n+s32 igc_configure_k0s_lpt(struct igc_hw *hw, u8 entry_latency, u8 min_time);\n+void igc_copy_rx_addrs_to_phy_ich8lan(struct igc_hw *hw);\n+s32 igc_lv_jumbo_workaround_ich8lan(struct igc_hw *hw, bool enable);\n+s32 igc_read_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 *data);\n+s32 igc_write_emi_reg_locked(struct igc_hw *hw, u16 addr, u16 data);\n+s32 igc_set_eee_pchlan(struct igc_hw *hw);\n+s32 igc_enable_ulp_lpt_lp(struct igc_hw *hw, bool to_sx);\n+s32 igc_disable_ulp_lpt_lp(struct igc_hw *hw, bool force);\n+#endif /* _IGC_ICH8LAN_H_ */\n+void igc_demote_ltr(struct igc_hw *hw, bool demote, bool link);\ndiff --git a/drivers/net/igc/base/e1000_mac.c b/drivers/net/igc/base/e1000_mac.c\nnew file mode 100644\nindex 0000000..2c8fcd4\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_mac.c\n@@ -0,0 +1,2100 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+static s32 igc_validate_mdi_setting_generic(struct igc_hw *hw);\n+static void igc_set_lan_id_multi_port_pcie(struct igc_hw *hw);\n+static void igc_config_collision_dist_generic(struct igc_hw *hw);\n+static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index);\n+\n+/**\n+ *  igc_init_mac_ops_generic - Initialize MAC function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Setups up the function pointers to no-op functions\n+ **/\n+void igc_init_mac_ops_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tDEBUGFUNC(\"igc_init_mac_ops_generic\");\n+\n+\t/* General Setup */\n+\tmac->ops.init_params = igc_null_ops_generic;\n+\tmac->ops.init_hw = igc_null_ops_generic;\n+\tmac->ops.reset_hw = igc_null_ops_generic;\n+\tmac->ops.setup_physical_interface = igc_null_ops_generic;\n+\tmac->ops.get_bus_info = igc_null_ops_generic;\n+\tmac->ops.set_lan_id = igc_set_lan_id_multi_port_pcie;\n+\tmac->ops.read_mac_addr = igc_read_mac_addr_generic;\n+\tmac->ops.config_collision_dist = igc_config_collision_dist_generic;\n+\tmac->ops.clear_hw_cntrs = igc_null_mac_generic;\n+\t/* LED */\n+\tmac->ops.cleanup_led = igc_null_ops_generic;\n+\tmac->ops.setup_led = igc_null_ops_generic;\n+\tmac->ops.blink_led = igc_null_ops_generic;\n+\tmac->ops.led_on = igc_null_ops_generic;\n+\tmac->ops.led_off = igc_null_ops_generic;\n+\t/* LINK */\n+\tmac->ops.setup_link = igc_null_ops_generic;\n+\tmac->ops.get_link_up_info = igc_null_link_info;\n+\tmac->ops.check_for_link = igc_null_ops_generic;\n+\t/* Management */\n+\tmac->ops.check_mng_mode = igc_null_mng_mode;\n+\t/* VLAN, MC, etc. */\n+\tmac->ops.update_mc_addr_list = igc_null_update_mc;\n+\tmac->ops.clear_vfta = igc_null_mac_generic;\n+\tmac->ops.write_vfta = igc_null_write_vfta;\n+\tmac->ops.rar_set = igc_rar_set_generic;\n+\tmac->ops.validate_mdi_setting = igc_validate_mdi_setting_generic;\n+}\n+\n+/**\n+ *  igc_null_ops_generic - No-op function, returns 0\n+ *  @hw: pointer to the HW structure\n+ **/\n+s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_null_ops_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_mac_generic - No-op function, return void\n+ *  @hw: pointer to the HW structure\n+ **/\n+void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_null_mac_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+}\n+\n+/**\n+ *  igc_null_link_info - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @s: dummy variable\n+ *  @d: dummy variable\n+ **/\n+s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t u16 IGC_UNUSEDARG * s, u16 IGC_UNUSEDARG * d)\n+{\n+\tDEBUGFUNC(\"igc_null_link_info\");\n+\tUNREFERENCED_3PARAMETER(hw, s, d);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_mng_mode - No-op function, return false\n+ *  @hw: pointer to the HW structure\n+ **/\n+bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_null_mng_mode\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+\treturn false;\n+}\n+\n+/**\n+ *  igc_null_update_mc - No-op function, return void\n+ *  @hw: pointer to the HW structure\n+ *  @h: dummy variable\n+ *  @a: dummy variable\n+ **/\n+void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t  u8 IGC_UNUSEDARG * h, u32 IGC_UNUSEDARG a)\n+{\n+\tDEBUGFUNC(\"igc_null_update_mc\");\n+\tUNREFERENCED_3PARAMETER(hw, h, a);\n+}\n+\n+/**\n+ *  igc_null_write_vfta - No-op function, return void\n+ *  @hw: pointer to the HW structure\n+ *  @a: dummy variable\n+ *  @b: dummy variable\n+ **/\n+void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t   u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b)\n+{\n+\tDEBUGFUNC(\"igc_null_write_vfta\");\n+\tUNREFERENCED_3PARAMETER(hw, a, b);\n+}\n+\n+/**\n+ *  igc_null_rar_set - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @h: dummy variable\n+ *  @a: dummy variable\n+ **/\n+int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\tu8 IGC_UNUSEDARG * h, u32 IGC_UNUSEDARG a)\n+{\n+\tDEBUGFUNC(\"igc_null_rar_set\");\n+\tUNREFERENCED_3PARAMETER(hw, h, a);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_bus_info_pci_generic - Get PCI(x) bus information\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Determines and stores the system bus information for a particular\n+ *  network interface.  The following bus information is determined and stored:\n+ *  bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.\n+ **/\n+s32 igc_get_bus_info_pci_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\tu32 status = IGC_READ_REG(hw, IGC_STATUS);\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_get_bus_info_pci_generic\");\n+\n+\t/* PCI or PCI-X? */\n+\tbus->type = (status & IGC_STATUS_PCIX_MODE)\n+\t\t\t? igc_bus_type_pcix\n+\t\t\t: igc_bus_type_pci;\n+\n+\t/* Bus speed */\n+\tif (bus->type == igc_bus_type_pci) {\n+\t\tbus->speed = (status & IGC_STATUS_PCI66)\n+\t\t\t     ? igc_bus_speed_66\n+\t\t\t     : igc_bus_speed_33;\n+\t} else {\n+\t\tswitch (status & IGC_STATUS_PCIX_SPEED) {\n+\t\tcase IGC_STATUS_PCIX_SPEED_66:\n+\t\t\tbus->speed = igc_bus_speed_66;\n+\t\t\tbreak;\n+\t\tcase IGC_STATUS_PCIX_SPEED_100:\n+\t\t\tbus->speed = igc_bus_speed_100;\n+\t\t\tbreak;\n+\t\tcase IGC_STATUS_PCIX_SPEED_133:\n+\t\t\tbus->speed = igc_bus_speed_133;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbus->speed = igc_bus_speed_reserved;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Bus width */\n+\tbus->width = (status & IGC_STATUS_BUS64)\n+\t\t     ? igc_bus_width_64\n+\t\t     : igc_bus_width_32;\n+\n+\t/* Which PCI(-X) function? */\n+\tmac->ops.set_lan_id(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_bus_info_pcie_generic - Get PCIe bus information\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Determines and stores the system bus information for a particular\n+ *  network interface.  The following bus information is determined and stored:\n+ *  bus speed, bus width, type (PCIe), and PCIe function.\n+ **/\n+s32 igc_get_bus_info_pcie_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\ts32 ret_val;\n+\tu16 pcie_link_status;\n+\n+\tDEBUGFUNC(\"igc_get_bus_info_pcie_generic\");\n+\n+\tbus->type = igc_bus_type_pci_express;\n+\n+\tret_val = igc_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,\n+\t\t\t\t\t  &pcie_link_status);\n+\tif (ret_val) {\n+\t\tbus->width = igc_bus_width_unknown;\n+\t\tbus->speed = igc_bus_speed_unknown;\n+\t} else {\n+\t\tswitch (pcie_link_status & PCIE_LINK_SPEED_MASK) {\n+\t\tcase PCIE_LINK_SPEED_2500:\n+\t\t\tbus->speed = igc_bus_speed_2500;\n+\t\t\tbreak;\n+\t\tcase PCIE_LINK_SPEED_5000:\n+\t\t\tbus->speed = igc_bus_speed_5000;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbus->speed = igc_bus_speed_unknown;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tbus->width = (enum igc_bus_width)((pcie_link_status &\n+\t\t\t      PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);\n+\t}\n+\n+\tmac->ops.set_lan_id(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n+ *\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Determines the LAN function id by reading memory-mapped registers\n+ *  and swaps the port value if requested.\n+ **/\n+static void igc_set_lan_id_multi_port_pcie(struct igc_hw *hw)\n+{\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\tu32 reg;\n+\n+\t/* The status register reports the correct function number\n+\t * for the device regardless of function swap state.\n+\t */\n+\treg = IGC_READ_REG(hw, IGC_STATUS);\n+\tbus->func = (reg & IGC_STATUS_FUNC_MASK) >> IGC_STATUS_FUNC_SHIFT;\n+}\n+\n+/**\n+ *  igc_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Determines the LAN function id by reading PCI config space.\n+ **/\n+void igc_set_lan_id_multi_port_pci(struct igc_hw *hw)\n+{\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\tu16 pci_header_type;\n+\tu32 status;\n+\n+\tigc_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);\n+\tif (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {\n+\t\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\t\tbus->func = (status & IGC_STATUS_FUNC_MASK)\n+\t\t\t    >> IGC_STATUS_FUNC_SHIFT;\n+\t} else {\n+\t\tbus->func = 0;\n+\t}\n+}\n+\n+/**\n+ *  igc_set_lan_id_single_port - Set LAN id for a single port device\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets the LAN function id to zero for a single port device.\n+ **/\n+void igc_set_lan_id_single_port(struct igc_hw *hw)\n+{\n+\tstruct igc_bus_info *bus = &hw->bus;\n+\n+\tbus->func = 0;\n+}\n+\n+/**\n+ *  igc_clear_vfta_generic - Clear VLAN filter table\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Clears the register array which contains the VLAN filter table by\n+ *  setting all the values to 0.\n+ **/\n+void igc_clear_vfta_generic(struct igc_hw *hw)\n+{\n+\tu32 offset;\n+\n+\tDEBUGFUNC(\"igc_clear_vfta_generic\");\n+\n+\tfor (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) {\n+\t\tIGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t}\n+}\n+\n+/**\n+ *  igc_write_vfta_generic - Write value to VLAN filter table\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset in VLAN filter table\n+ *  @value: register value written to VLAN filter table\n+ *\n+ *  Writes value at the given offset in the register array which stores\n+ *  the VLAN filter table.\n+ **/\n+void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)\n+{\n+\tDEBUGFUNC(\"igc_write_vfta_generic\");\n+\n+\tIGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);\n+\tIGC_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ *  igc_init_rx_addrs_generic - Initialize receive address's\n+ *  @hw: pointer to the HW structure\n+ *  @rar_count: receive address registers\n+ *\n+ *  Setup the receive address registers by setting the base receive address\n+ *  register to the devices MAC address and clearing all the other receive\n+ *  address registers to 0.\n+ **/\n+void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)\n+{\n+\tu32 i;\n+\tu8 mac_addr[ETH_ADDR_LEN] = {0};\n+\n+\tDEBUGFUNC(\"igc_init_rx_addrs_generic\");\n+\n+\t/* Setup the receive address */\n+\tDEBUGOUT(\"Programming MAC Address into RAR[0]\\n\");\n+\n+\thw->mac.ops.rar_set(hw, hw->mac.addr, 0);\n+\n+\t/* Zero out the other (rar_entry_count - 1) receive addresses */\n+\tDEBUGOUT1(\"Clearing RAR[1-%u]\\n\", rar_count - 1);\n+\tfor (i = 1; i < rar_count; i++)\n+\t\thw->mac.ops.rar_set(hw, mac_addr, i);\n+}\n+\n+/**\n+ *  igc_check_alt_mac_addr_generic - Check for alternate MAC addr\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks the nvm for an alternate MAC address.  An alternate MAC address\n+ *  can be setup by pre-boot software and must be treated like a permanent\n+ *  address and must override the actual permanent MAC address. If an\n+ *  alternate MAC address is found it is programmed into RAR0, replacing\n+ *  the permanent address that was installed into RAR0 by the Si on reset.\n+ *  This function will return SUCCESS unless it encounters an error while\n+ *  reading the EEPROM.\n+ **/\n+s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)\n+{\n+\tu32 i;\n+\ts32 ret_val;\n+\tu16 offset, nvm_alt_mac_addr_offset, nvm_data;\n+\tu8 alt_mac_addr[ETH_ADDR_LEN];\n+\n+\tDEBUGFUNC(\"igc_check_alt_mac_addr_generic\");\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* not supported on older hardware or 82573 */\n+\tif (hw->mac.type < igc_82571 || hw->mac.type == igc_82573)\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* Alternate MAC address is handled by the option ROM for 82580\n+\t * and newer. SW support not required.\n+\t */\n+\tif (hw->mac.type >= igc_82580)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,\n+\t\t\t\t   &nvm_alt_mac_addr_offset);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (nvm_alt_mac_addr_offset == 0xFFFF ||\n+\t    nvm_alt_mac_addr_offset == 0x0000)\n+\t\t/* There is no Alternate MAC Address */\n+\t\treturn IGC_SUCCESS;\n+\n+\tif (hw->bus.func == IGC_FUNC_1)\n+\t\tnvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;\n+\tif (hw->bus.func == IGC_FUNC_2)\n+\t\tnvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN2;\n+\n+\tif (hw->bus.func == IGC_FUNC_3)\n+\t\tnvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN3;\n+\tfor (i = 0; i < ETH_ADDR_LEN; i += 2) {\n+\t\toffset = nvm_alt_mac_addr_offset + (i >> 1);\n+\t\tret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\n+\t\talt_mac_addr[i] = (u8)(nvm_data & 0xFF);\n+\t\talt_mac_addr[i + 1] = (u8)(nvm_data >> 8);\n+\t}\n+\n+\t/* if multicast bit is set, the alternate address will not be used */\n+\tif (alt_mac_addr[0] & 0x01) {\n+\t\tDEBUGOUT(\"Ignoring Alternate Mac Address with MC bit set\\n\");\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\t/* We have a valid alternate MAC address, and we want to treat it the\n+\t * same as the normal permanent MAC address stored by the HW into the\n+\t * RAR. Do this by mapping this address into RAR0.\n+\t */\n+\thw->mac.ops.rar_set(hw, alt_mac_addr, 0);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_rar_set_generic - Set receive address register\n+ *  @hw: pointer to the HW structure\n+ *  @addr: pointer to the receive address\n+ *  @index: receive address array register\n+ *\n+ *  Sets the receive address array register at index to the address passed\n+ *  in by addr.\n+ **/\n+static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)\n+{\n+\tu32 rar_low, rar_high;\n+\n+\tDEBUGFUNC(\"igc_rar_set_generic\");\n+\n+\t/* HW expects these in little endian so we reverse the byte order\n+\t * from network order (big endian) to little endian\n+\t */\n+\trar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |\n+\t\t   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));\n+\n+\trar_high = ((u32)addr[4] | ((u32)addr[5] << 8));\n+\n+\t/* If MAC address zero, no need to set the AV bit */\n+\tif (rar_low || rar_high)\n+\t\trar_high |= IGC_RAH_AV;\n+\n+\t/* Some bridges will combine consecutive 32-bit writes into\n+\t * a single burst write, which will malfunction on some parts.\n+\t * The flushes avoid this.\n+\t */\n+\tIGC_WRITE_REG(hw, IGC_RAL(index), rar_low);\n+\tIGC_WRITE_FLUSH(hw);\n+\tIGC_WRITE_REG(hw, IGC_RAH(index), rar_high);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_hash_mc_addr_generic - Generate a multicast hash value\n+ *  @hw: pointer to the HW structure\n+ *  @mc_addr: pointer to a multicast address\n+ *\n+ *  Generates a multicast address hash value which is used to determine\n+ *  the multicast filter table array address and new table value.\n+ **/\n+u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)\n+{\n+\tu32 hash_value, hash_mask;\n+\tu8 bit_shift = 0;\n+\n+\tDEBUGFUNC(\"igc_hash_mc_addr_generic\");\n+\n+\t/* Register count multiplied by bits per register */\n+\thash_mask = (hw->mac.mta_reg_count * 32) - 1;\n+\n+\t/* For a mc_filter_type of 0, bit_shift is the number of left-shifts\n+\t * where 0xFF would still fall within the hash mask.\n+\t */\n+\twhile (hash_mask >> bit_shift != 0xFF)\n+\t\tbit_shift++;\n+\n+\t/* The portion of the address that is used for the hash table\n+\t * is determined by the mc_filter_type setting.\n+\t * The algorithm is such that there is a total of 8 bits of shifting.\n+\t * The bit_shift for a mc_filter_type of 0 represents the number of\n+\t * left-shifts where the MSB of mc_addr[5] would still fall within\n+\t * the hash_mask.  Case 0 does this exactly.  Since there are a total\n+\t * of 8 bits of shifting, then mc_addr[4] will shift right the\n+\t * remaining number of bits. Thus 8 - bit_shift.  The rest of the\n+\t * cases are a variation of this algorithm...essentially raising the\n+\t * number of bits to shift mc_addr[5] left, while still keeping the\n+\t * 8-bit shifting total.\n+\t *\n+\t * For example, given the following Destination MAC Address and an\n+\t * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),\n+\t * we can see that the bit_shift for case 0 is 4.  These are the hash\n+\t * values resulting from each mc_filter_type...\n+\t * [0] [1] [2] [3] [4] [5]\n+\t * 01  AA  00  12  34  56\n+\t * LSB\t\t MSB\n+\t *\n+\t * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563\n+\t * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6\n+\t * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163\n+\t * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634\n+\t */\n+\tswitch (hw->mac.mc_filter_type) {\n+\tdefault:\n+\tcase 0:\n+\t\tbreak;\n+\tcase 1:\n+\t\tbit_shift += 1;\n+\t\tbreak;\n+\tcase 2:\n+\t\tbit_shift += 2;\n+\t\tbreak;\n+\tcase 3:\n+\t\tbit_shift += 4;\n+\t\tbreak;\n+\t}\n+\n+\thash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |\n+\t\t\t\t  (((u16)mc_addr[5]) << bit_shift)));\n+\n+\treturn hash_value;\n+}\n+\n+/**\n+ *  igc_update_mc_addr_list_generic - Update Multicast addresses\n+ *  @hw: pointer to the HW structure\n+ *  @mc_addr_list: array of multicast addresses to program\n+ *  @mc_addr_count: number of multicast addresses to program\n+ *\n+ *  Updates entire Multicast Table Array.\n+ *  The caller must have a packed mc_addr_list of multicast addresses.\n+ **/\n+void igc_update_mc_addr_list_generic(struct igc_hw *hw,\n+\t\t\t\t       u8 *mc_addr_list, u32 mc_addr_count)\n+{\n+\tu32 hash_value, hash_bit, hash_reg;\n+\tint i;\n+\n+\tDEBUGFUNC(\"igc_update_mc_addr_list_generic\");\n+\n+\t/* clear mta_shadow */\n+\tmemset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));\n+\n+\t/* update mta_shadow from mc_addr_list */\n+\tfor (i = 0; (u32)i < mc_addr_count; i++) {\n+\t\thash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);\n+\n+\t\thash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);\n+\t\thash_bit = hash_value & 0x1F;\n+\n+\t\thw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);\n+\t\tmc_addr_list += (ETH_ADDR_LEN);\n+\t}\n+\n+\t/* replace the entire MTA table */\n+\tfor (i = hw->mac.mta_reg_count - 1; i >= 0; i--)\n+\t\tIGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);\n+\tIGC_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ *  igc_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  In certain situations, a system BIOS may report that the PCIx maximum\n+ *  memory read byte count (MMRBC) value is higher than than the actual\n+ *  value. We check the PCIx command register with the current PCIx status\n+ *  register.\n+ **/\n+void igc_pcix_mmrbc_workaround_generic(struct igc_hw *hw)\n+{\n+\tu16 cmd_mmrbc;\n+\tu16 pcix_cmd;\n+\tu16 pcix_stat_hi_word;\n+\tu16 stat_mmrbc;\n+\n+\tDEBUGFUNC(\"igc_pcix_mmrbc_workaround_generic\");\n+\n+\t/* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */\n+\tif (hw->bus.type != igc_bus_type_pcix)\n+\t\treturn;\n+\n+\tigc_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);\n+\tigc_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);\n+\tcmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>\n+\t\t     PCIX_COMMAND_MMRBC_SHIFT;\n+\tstat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>\n+\t\t      PCIX_STATUS_HI_MMRBC_SHIFT;\n+\tif (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)\n+\t\tstat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;\n+\tif (cmd_mmrbc > stat_mmrbc) {\n+\t\tpcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;\n+\t\tpcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;\n+\t\tigc_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);\n+\t}\n+}\n+\n+/**\n+ *  igc_clear_hw_cntrs_base_generic - Clear base hardware counters\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Clears the base hardware counters by reading the counter registers.\n+ **/\n+void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)\n+{\n+\tDEBUGFUNC(\"igc_clear_hw_cntrs_base_generic\");\n+\n+\tIGC_READ_REG(hw, IGC_CRCERRS);\n+\tIGC_READ_REG(hw, IGC_SYMERRS);\n+\tIGC_READ_REG(hw, IGC_MPC);\n+\tIGC_READ_REG(hw, IGC_SCC);\n+\tIGC_READ_REG(hw, IGC_ECOL);\n+\tIGC_READ_REG(hw, IGC_MCC);\n+\tIGC_READ_REG(hw, IGC_LATECOL);\n+\tIGC_READ_REG(hw, IGC_COLC);\n+\tIGC_READ_REG(hw, IGC_DC);\n+\tIGC_READ_REG(hw, IGC_SEC);\n+\tIGC_READ_REG(hw, IGC_RLEC);\n+\tIGC_READ_REG(hw, IGC_XONRXC);\n+\tIGC_READ_REG(hw, IGC_XONTXC);\n+\tIGC_READ_REG(hw, IGC_XOFFRXC);\n+\tIGC_READ_REG(hw, IGC_XOFFTXC);\n+\tIGC_READ_REG(hw, IGC_FCRUC);\n+\tIGC_READ_REG(hw, IGC_GPRC);\n+\tIGC_READ_REG(hw, IGC_BPRC);\n+\tIGC_READ_REG(hw, IGC_MPRC);\n+\tIGC_READ_REG(hw, IGC_GPTC);\n+\tIGC_READ_REG(hw, IGC_GORCL);\n+\tIGC_READ_REG(hw, IGC_GORCH);\n+\tIGC_READ_REG(hw, IGC_GOTCL);\n+\tIGC_READ_REG(hw, IGC_GOTCH);\n+\tIGC_READ_REG(hw, IGC_RNBC);\n+\tIGC_READ_REG(hw, IGC_RUC);\n+\tIGC_READ_REG(hw, IGC_RFC);\n+\tIGC_READ_REG(hw, IGC_ROC);\n+\tIGC_READ_REG(hw, IGC_RJC);\n+\tIGC_READ_REG(hw, IGC_TORL);\n+\tIGC_READ_REG(hw, IGC_TORH);\n+\tIGC_READ_REG(hw, IGC_TOTL);\n+\tIGC_READ_REG(hw, IGC_TOTH);\n+\tIGC_READ_REG(hw, IGC_TPR);\n+\tIGC_READ_REG(hw, IGC_TPT);\n+\tIGC_READ_REG(hw, IGC_MPTC);\n+\tIGC_READ_REG(hw, IGC_BPTC);\n+}\n+\n+/**\n+ *  igc_check_for_copper_link_generic - Check for link (Copper)\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks to see of the link status of the hardware has changed.  If a\n+ *  change in link status has been detected, then we read the PHY registers\n+ *  to get the current speed/duplex if link exists.\n+ **/\n+s32 igc_check_for_copper_link_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_check_for_copper_link\");\n+\n+\t/* We only want to go out to the PHY registers to see if Auto-Neg\n+\t * has completed and/or if our link status has changed.  The\n+\t * get_link_status flag is set upon receiving a Link Status\n+\t * Change or Rx Sequence Error interrupt.\n+\t */\n+\tif (!mac->get_link_status)\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* First we want to see if the MII Status Register reports\n+\t * link.  If so, then we want to get the current speed/duplex\n+\t * of the PHY.\n+\t */\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!link)\n+\t\treturn IGC_SUCCESS; /* No link detected */\n+\n+\tmac->get_link_status = false;\n+\n+\t/* Check if there was DownShift, must be checked\n+\t * immediately after link-up\n+\t */\n+\tigc_check_downshift_generic(hw);\n+\n+\t/* If we are forcing speed/duplex, then we simply return since\n+\t * we have already determined whether we have link or not.\n+\t */\n+\tif (!mac->autoneg)\n+\t\treturn -IGC_ERR_CONFIG;\n+\n+\t/* Auto-Neg is enabled.  Auto Speed Detection takes care\n+\t * of MAC speed/duplex configuration.  So we only need to\n+\t * configure Collision Distance in the MAC.\n+\t */\n+\tmac->ops.config_collision_dist(hw);\n+\n+\t/* Configure Flow Control now that Auto-Neg has completed.\n+\t * First, we need to restore the desired flow control\n+\t * settings because we may have had to re-autoneg with a\n+\t * different link partner.\n+\t */\n+\tret_val = igc_config_fc_after_link_up_generic(hw);\n+\tif (ret_val)\n+\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_check_for_fiber_link_generic - Check for link (Fiber)\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks for link up on the hardware.  If link is not up and we have\n+ *  a signal, then we need to force link up.\n+ **/\n+s32 igc_check_for_fiber_link_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu32 rxcw;\n+\tu32 ctrl;\n+\tu32 status;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_check_for_fiber_link_generic\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\trxcw = IGC_READ_REG(hw, IGC_RXCW);\n+\n+\t/* If we don't have link (auto-negotiation failed or link partner\n+\t * cannot auto-negotiate), the cable is plugged in (we have signal),\n+\t * and our link partner is not trying to auto-negotiate with us (we\n+\t * are receiving idles or data), we need to force link up. We also\n+\t * need to give auto-negotiation time to complete, in case the cable\n+\t * was just plugged in. The autoneg_failed flag does this.\n+\t */\n+\t/* (ctrl & IGC_CTRL_SWDPIN1) == 1 == have signal */\n+\tif ((ctrl & IGC_CTRL_SWDPIN1) && !(status & IGC_STATUS_LU) &&\n+\t    !(rxcw & IGC_RXCW_C)) {\n+\t\tif (!mac->autoneg_failed) {\n+\t\t\tmac->autoneg_failed = true;\n+\t\t\treturn IGC_SUCCESS;\n+\t\t}\n+\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n+\n+\t\t/* Disable auto-negotiation in the TXCW register */\n+\t\tIGC_WRITE_REG(hw, IGC_TXCW, (mac->txcw & ~IGC_TXCW_ANE));\n+\n+\t\t/* Force link-up and also force full-duplex. */\n+\t\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\t\tctrl |= (IGC_CTRL_SLU | IGC_CTRL_FD);\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\n+\t\t/* Configure Flow Control after forcing link up. */\n+\t\tret_val = igc_config_fc_after_link_up_generic(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t} else if ((ctrl & IGC_CTRL_SLU) && (rxcw & IGC_RXCW_C)) {\n+\t\t/* If we are forcing link and we are receiving /C/ ordered\n+\t\t * sets, re-enable auto-negotiation in the TXCW register\n+\t\t * and disable forced link in the Device Control register\n+\t\t * in an attempt to auto-negotiate with our link partner.\n+\t\t */\n+\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n+\t\tIGC_WRITE_REG(hw, IGC_TXCW, mac->txcw);\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, (ctrl & ~IGC_CTRL_SLU));\n+\n+\t\tmac->serdes_has_link = true;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_check_for_serdes_link_generic - Check for link (Serdes)\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks for link up on the hardware.  If link is not up and we have\n+ *  a signal, then we need to force link up.\n+ **/\n+s32 igc_check_for_serdes_link_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu32 rxcw;\n+\tu32 ctrl;\n+\tu32 status;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_check_for_serdes_link_generic\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\trxcw = IGC_READ_REG(hw, IGC_RXCW);\n+\n+\t/* If we don't have link (auto-negotiation failed or link partner\n+\t * cannot auto-negotiate), and our link partner is not trying to\n+\t * auto-negotiate with us (we are receiving idles or data),\n+\t * we need to force link up. We also need to give auto-negotiation\n+\t * time to complete.\n+\t */\n+\t/* (ctrl & IGC_CTRL_SWDPIN1) == 1 == have signal */\n+\tif (!(status & IGC_STATUS_LU) && !(rxcw & IGC_RXCW_C)) {\n+\t\tif (!mac->autoneg_failed) {\n+\t\t\tmac->autoneg_failed = true;\n+\t\t\treturn IGC_SUCCESS;\n+\t\t}\n+\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n+\n+\t\t/* Disable auto-negotiation in the TXCW register */\n+\t\tIGC_WRITE_REG(hw, IGC_TXCW, (mac->txcw & ~IGC_TXCW_ANE));\n+\n+\t\t/* Force link-up and also force full-duplex. */\n+\t\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\t\tctrl |= (IGC_CTRL_SLU | IGC_CTRL_FD);\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\n+\t\t/* Configure Flow Control after forcing link up. */\n+\t\tret_val = igc_config_fc_after_link_up_generic(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t} else if ((ctrl & IGC_CTRL_SLU) && (rxcw & IGC_RXCW_C)) {\n+\t\t/* If we are forcing link and we are receiving /C/ ordered\n+\t\t * sets, re-enable auto-negotiation in the TXCW register\n+\t\t * and disable forced link in the Device Control register\n+\t\t * in an attempt to auto-negotiate with our link partner.\n+\t\t */\n+\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n+\t\tIGC_WRITE_REG(hw, IGC_TXCW, mac->txcw);\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, (ctrl & ~IGC_CTRL_SLU));\n+\n+\t\tmac->serdes_has_link = true;\n+\t} else if (!(IGC_TXCW_ANE & IGC_READ_REG(hw, IGC_TXCW))) {\n+\t\t/* If we force link for non-auto-negotiation switch, check\n+\t\t * link status based on MAC synchronization for internal\n+\t\t * serdes media type.\n+\t\t */\n+\t\t/* SYNCH bit and IV bit are sticky. */\n+\t\tusec_delay(10);\n+\t\trxcw = IGC_READ_REG(hw, IGC_RXCW);\n+\t\tif (rxcw & IGC_RXCW_SYNCH) {\n+\t\t\tif (!(rxcw & IGC_RXCW_IV)) {\n+\t\t\t\tmac->serdes_has_link = true;\n+\t\t\t\tDEBUGOUT(\"SERDES: Link up - forced.\\n\");\n+\t\t\t}\n+\t\t} else {\n+\t\t\tmac->serdes_has_link = false;\n+\t\t\tDEBUGOUT(\"SERDES: Link down - force failed.\\n\");\n+\t\t}\n+\t}\n+\n+\tif (IGC_TXCW_ANE & IGC_READ_REG(hw, IGC_TXCW)) {\n+\t\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\t\tif (status & IGC_STATUS_LU) {\n+\t\t\t/* SYNCH bit and IV bit are sticky, so reread rxcw. */\n+\t\t\tusec_delay(10);\n+\t\t\trxcw = IGC_READ_REG(hw, IGC_RXCW);\n+\t\t\tif (rxcw & IGC_RXCW_SYNCH) {\n+\t\t\t\tif (!(rxcw & IGC_RXCW_IV)) {\n+\t\t\t\t\tmac->serdes_has_link = true;\n+\t\t\t\t\tDEBUGOUT(\"SERDES: Link up - autoneg completed successfully.\\n\");\n+\t\t\t\t} else {\n+\t\t\t\t\tmac->serdes_has_link = false;\n+\t\t\t\t\tDEBUGOUT(\"SERDES: Link down - invalid codewords detected in autoneg.\\n\");\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tmac->serdes_has_link = false;\n+\t\t\t\tDEBUGOUT(\"SERDES: Link down - no sync.\\n\");\n+\t\t\t}\n+\t\t} else {\n+\t\t\tmac->serdes_has_link = false;\n+\t\t\tDEBUGOUT(\"SERDES: Link down - autoneg failed\\n\");\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_default_fc_generic - Set flow control default values\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Read the EEPROM for the default values for flow control and store the\n+ *  values.\n+ **/\n+s32 igc_set_default_fc_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 nvm_data;\n+\tu16 nvm_offset = 0;\n+\n+\tDEBUGFUNC(\"igc_set_default_fc_generic\");\n+\n+\t/* Read and store word 0x0F of the EEPROM. This word contains bits\n+\t * that determine the hardware's default PAUSE (flow control) mode,\n+\t * a bit that determines whether the HW defaults to enabling or\n+\t * disabling auto-negotiation, and the direction of the\n+\t * SW defined pins. If there is no SW over-ride of the flow\n+\t * control setting, then the variable hw->fc will\n+\t * be initialized based on a value in the EEPROM.\n+\t */\n+\tif (hw->mac.type == igc_i350) {\n+\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);\n+\t\tret_val = hw->nvm.ops.read(hw,\n+\t\t\t\t\t   NVM_INIT_CONTROL2_REG +\n+\t\t\t\t\t   nvm_offset,\n+\t\t\t\t\t   1, &nvm_data);\n+\t} else {\n+\t\tret_val = hw->nvm.ops.read(hw,\n+\t\t\t\t\t   NVM_INIT_CONTROL2_REG,\n+\t\t\t\t\t   1, &nvm_data);\n+\t}\n+\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (!(nvm_data & NVM_WORD0F_PAUSE_MASK))\n+\t\thw->fc.requested_mode = igc_fc_none;\n+\telse if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==\n+\t\t NVM_WORD0F_ASM_DIR)\n+\t\thw->fc.requested_mode = igc_fc_tx_pause;\n+\telse\n+\t\thw->fc.requested_mode = igc_fc_full;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_setup_link_generic - Setup flow control and link settings\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Determines which flow control settings to use, then configures flow\n+ *  control.  Calls the appropriate media-specific link configuration\n+ *  function.  Assuming the adapter has a valid link partner, a valid link\n+ *  should be established.  Assumes the hardware has previously been reset\n+ *  and the transmitter and receiver are not enabled.\n+ **/\n+s32 igc_setup_link_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_setup_link_generic\");\n+\n+\t/* In the case of the phy reset being blocked, we already have a link.\n+\t * We do not need to set it up again.\n+\t */\n+\tif (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* If requested flow control is set to default, set flow control\n+\t * based on the EEPROM flow control settings.\n+\t */\n+\tif (hw->fc.requested_mode == igc_fc_default)\n+\t\thw->fc.requested_mode = igc_fc_full;\n+\n+\t/* Save off the requested flow control mode for use later.  Depending\n+\t * on the link partner's capabilities, we may or may not use this mode.\n+\t */\n+\thw->fc.current_mode = hw->fc.requested_mode;\n+\n+\tDEBUGOUT1(\"After fix-ups FlowControl is now = %x\\n\",\n+\t\thw->fc.current_mode);\n+\n+\t/* Call the necessary media_type subroutine to configure the link. */\n+\tret_val = hw->mac.ops.setup_physical_interface(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Initialize the flow control address, type, and PAUSE timer\n+\t * registers to their default values.  This is done even if flow\n+\t * control is disabled, because it does not hurt anything to\n+\t * initialize these registers.\n+\t */\n+\tDEBUGOUT(\"Initializing the Flow Control address, type and timer regs\\n\");\n+\tIGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);\n+\tIGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);\n+\tIGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);\n+\n+\tIGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);\n+\n+\treturn igc_set_fc_watermarks_generic(hw);\n+}\n+\n+/**\n+ *  igc_commit_fc_settings_generic - Configure flow control\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Write the flow control settings to the Transmit Config Word Register (TXCW)\n+ *  base on the flow control settings in igc_mac_info.\n+ **/\n+s32 igc_commit_fc_settings_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu32 txcw;\n+\n+\tDEBUGFUNC(\"igc_commit_fc_settings_generic\");\n+\n+\t/* Check for a software override of the flow control settings, and\n+\t * setup the device accordingly.  If auto-negotiation is enabled, then\n+\t * software will have to set the \"PAUSE\" bits to the correct value in\n+\t * the Transmit Config Word Register (TXCW) and re-start auto-\n+\t * negotiation.  However, if auto-negotiation is disabled, then\n+\t * software will have to manually configure the two flow control enable\n+\t * bits in the CTRL register.\n+\t *\n+\t * The possible values of the \"fc\" parameter are:\n+\t *      0:  Flow control is completely disabled\n+\t *      1:  Rx flow control is enabled (we can receive pause frames,\n+\t *          but not send pause frames).\n+\t *      2:  Tx flow control is enabled (we can send pause frames but we\n+\t *          do not support receiving pause frames).\n+\t *      3:  Both Rx and Tx flow control (symmetric) are enabled.\n+\t */\n+\tswitch (hw->fc.current_mode) {\n+\tcase igc_fc_none:\n+\t\t/* Flow control completely disabled by a software over-ride. */\n+\t\ttxcw = (IGC_TXCW_ANE | IGC_TXCW_FD);\n+\t\tbreak;\n+\tcase igc_fc_rx_pause:\n+\t\t/* Rx Flow control is enabled and Tx Flow control is disabled\n+\t\t * by a software over-ride. Since there really isn't a way to\n+\t\t * advertise that we are capable of Rx Pause ONLY, we will\n+\t\t * advertise that we support both symmetric and asymmetric Rx\n+\t\t * PAUSE.  Later, we will disable the adapter's ability to send\n+\t\t * PAUSE frames.\n+\t\t */\n+\t\ttxcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_PAUSE_MASK);\n+\t\tbreak;\n+\tcase igc_fc_tx_pause:\n+\t\t/* Tx Flow control is enabled, and Rx Flow control is disabled,\n+\t\t * by a software over-ride.\n+\t\t */\n+\t\ttxcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_ASM_DIR);\n+\t\tbreak;\n+\tcase igc_fc_full:\n+\t\t/* Flow control (both Rx and Tx) is enabled by a software\n+\t\t * over-ride.\n+\t\t */\n+\t\ttxcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_PAUSE_MASK);\n+\t\tbreak;\n+\tdefault:\n+\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tIGC_WRITE_REG(hw, IGC_TXCW, txcw);\n+\tmac->txcw = txcw;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_poll_fiber_serdes_link_generic - Poll for link up\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Polls for link up by reading the status register, if link fails to come\n+ *  up with auto-negotiation, then the link is forced if a signal is detected.\n+ **/\n+s32 igc_poll_fiber_serdes_link_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu32 i, status;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_poll_fiber_serdes_link_generic\");\n+\n+\t/* If we have a signal (the cable is plugged in, or assumed true for\n+\t * serdes media) then poll for a \"Link-Up\" indication in the Device\n+\t * Status Register.  Time-out if a link isn't seen in 500 milliseconds\n+\t * seconds (Auto-negotiation should complete in less than 500\n+\t * milliseconds even if the other end is doing it in SW).\n+\t */\n+\tfor (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {\n+\t\tmsec_delay(10);\n+\t\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\t\tif (status & IGC_STATUS_LU)\n+\t\t\tbreak;\n+\t}\n+\tif (i == FIBER_LINK_UP_LIMIT) {\n+\t\tDEBUGOUT(\"Never got a valid link from auto-neg!!!\\n\");\n+\t\tmac->autoneg_failed = true;\n+\t\t/* AutoNeg failed to achieve a link, so we'll call\n+\t\t * mac->check_for_link. This routine will force the\n+\t\t * link up if we detect a signal. This will allow us to\n+\t\t * communicate with non-autonegotiating link partners.\n+\t\t */\n+\t\tret_val = mac->ops.check_for_link(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error while checking for link\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t\tmac->autoneg_failed = false;\n+\t} else {\n+\t\tmac->autoneg_failed = false;\n+\t\tDEBUGOUT(\"Valid Link Found\\n\");\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_setup_fiber_serdes_link_generic - Setup link for fiber/serdes\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Configures collision distance and flow control for fiber and serdes\n+ *  links.  Upon successful setup, poll for link.\n+ **/\n+s32 igc_setup_fiber_serdes_link_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_setup_fiber_serdes_link_generic\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\n+\t/* Take the link out of reset */\n+\tctrl &= ~IGC_CTRL_LRST;\n+\n+\thw->mac.ops.config_collision_dist(hw);\n+\n+\tret_val = igc_commit_fc_settings_generic(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Since auto-negotiation is enabled, take the link out of reset (the\n+\t * link will be in reset, because we previously reset the chip). This\n+\t * will restart auto-negotiation.  If auto-negotiation is successful\n+\t * then the link-up status bit will be set and the flow control enable\n+\t * bits (RFCE and TFCE) will be set according to their negotiated value.\n+\t */\n+\tDEBUGOUT(\"Auto-negotiation enabled\\n\");\n+\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\tIGC_WRITE_FLUSH(hw);\n+\tmsec_delay(1);\n+\n+\t/* For these adapters, the SW definable pin 1 is set when the optics\n+\t * detect a signal.  If we have a signal, then poll for a \"Link-Up\"\n+\t * indication.\n+\t */\n+\tif (hw->phy.media_type == igc_media_type_internal_serdes ||\n+\t    (IGC_READ_REG(hw, IGC_CTRL) & IGC_CTRL_SWDPIN1)) {\n+\t\tret_val = igc_poll_fiber_serdes_link_generic(hw);\n+\t} else {\n+\t\tDEBUGOUT(\"No signal detected\\n\");\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_config_collision_dist_generic - Configure collision distance\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Configures the collision distance to the default value and is used\n+ *  during link setup.\n+ **/\n+static void igc_config_collision_dist_generic(struct igc_hw *hw)\n+{\n+\tu32 tctl;\n+\n+\tDEBUGFUNC(\"igc_config_collision_dist_generic\");\n+\n+\ttctl = IGC_READ_REG(hw, IGC_TCTL);\n+\n+\ttctl &= ~IGC_TCTL_COLD;\n+\ttctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;\n+\n+\tIGC_WRITE_REG(hw, IGC_TCTL, tctl);\n+\tIGC_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ *  igc_set_fc_watermarks_generic - Set flow control high/low watermarks\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets the flow control high/low threshold (watermark) registers.  If\n+ *  flow control XON frame transmission is enabled, then set XON frame\n+ *  transmission as well.\n+ **/\n+s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)\n+{\n+\tu32 fcrtl = 0, fcrth = 0;\n+\n+\tDEBUGFUNC(\"igc_set_fc_watermarks_generic\");\n+\n+\t/* Set the flow control receive threshold registers.  Normally,\n+\t * these registers will be set to a default threshold that may be\n+\t * adjusted later by the driver's runtime code.  However, if the\n+\t * ability to transmit pause frames is not enabled, then these\n+\t * registers will be set to 0.\n+\t */\n+\tif (hw->fc.current_mode & igc_fc_tx_pause) {\n+\t\t/* We need to set up the Receive Threshold high and low water\n+\t\t * marks as well as (optionally) enabling the transmission of\n+\t\t * XON frames.\n+\t\t */\n+\t\tfcrtl = hw->fc.low_water;\n+\t\tif (hw->fc.send_xon)\n+\t\t\tfcrtl |= IGC_FCRTL_XONE;\n+\n+\t\tfcrth = hw->fc.high_water;\n+\t}\n+\tIGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);\n+\tIGC_WRITE_REG(hw, IGC_FCRTH, fcrth);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_force_mac_fc_generic - Force the MAC's flow control settings\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the\n+ *  device control register to reflect the adapter settings.  TFCE and RFCE\n+ *  need to be explicitly set by software when a copper PHY is used because\n+ *  autonegotiation is managed by the PHY rather than the MAC.  Software must\n+ *  also configure these bits when link is forced on a fiber connection.\n+ **/\n+s32 igc_force_mac_fc_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_force_mac_fc_generic\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\n+\t/* Because we didn't get link via the internal auto-negotiation\n+\t * mechanism (we either forced link or we got link via PHY\n+\t * auto-neg), we have to manually enable/disable transmit an\n+\t * receive flow control.\n+\t *\n+\t * The \"Case\" statement below enables/disable flow control\n+\t * according to the \"hw->fc.current_mode\" parameter.\n+\t *\n+\t * The possible values of the \"fc\" parameter are:\n+\t *      0:  Flow control is completely disabled\n+\t *      1:  Rx flow control is enabled (we can receive pause\n+\t *          frames but not send pause frames).\n+\t *      2:  Tx flow control is enabled (we can send pause frames\n+\t *          frames but we do not receive pause frames).\n+\t *      3:  Both Rx and Tx flow control (symmetric) is enabled.\n+\t *  other:  No other values should be possible at this point.\n+\t */\n+\tDEBUGOUT1(\"hw->fc.current_mode = %u\\n\", hw->fc.current_mode);\n+\n+\tswitch (hw->fc.current_mode) {\n+\tcase igc_fc_none:\n+\t\tctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));\n+\t\tbreak;\n+\tcase igc_fc_rx_pause:\n+\t\tctrl &= (~IGC_CTRL_TFCE);\n+\t\tctrl |= IGC_CTRL_RFCE;\n+\t\tbreak;\n+\tcase igc_fc_tx_pause:\n+\t\tctrl &= (~IGC_CTRL_RFCE);\n+\t\tctrl |= IGC_CTRL_TFCE;\n+\t\tbreak;\n+\tcase igc_fc_full:\n+\t\tctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);\n+\t\tbreak;\n+\tdefault:\n+\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_config_fc_after_link_up_generic - Configures flow control after link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Checks the status of auto-negotiation after link up to ensure that the\n+ *  speed and duplex were not forced.  If the link needed to be forced, then\n+ *  flow control needs to be forced also.  If auto-negotiation is enabled\n+ *  and did not fail, then we configure flow control based on our link\n+ *  partner.\n+ **/\n+s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;\n+\tu16 speed, duplex;\n+\n+\tDEBUGFUNC(\"igc_config_fc_after_link_up_generic\");\n+\n+\t/* Check for the case where we have fiber media and auto-neg failed\n+\t * so we had to force link.  In this case, we need to force the\n+\t * configuration of the MAC to match the \"fc\" parameter.\n+\t */\n+\tif (mac->autoneg_failed) {\n+\t\tif (hw->phy.media_type == igc_media_type_copper)\n+\t\t\tret_val = igc_force_mac_fc_generic(hw);\n+\t}\n+\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Check for the case where we have copper media and auto-neg is\n+\t * enabled.  In this case, we need to check and see if Auto-Neg\n+\t * has completed, and if so, how the PHY and link partner has\n+\t * flow control configured.\n+\t */\n+\tif (hw->phy.media_type == igc_media_type_copper && mac->autoneg) {\n+\t\t/* Read the MII Status Register and check to see if AutoNeg\n+\t\t * has completed.  We read this twice because this reg has\n+\t\t * some \"sticky\" (latched) bits.\n+\t\t */\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {\n+\t\t\tDEBUGOUT(\"Copper PHY and Auto Neg has not completed.\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\n+\t\t/* The AutoNeg process has completed, so we now need to\n+\t\t * read both the Auto Negotiation Advertisement\n+\t\t * Register (Address 4) and the Auto_Negotiation Base\n+\t\t * Page Ability Register (Address 5) to determine how\n+\t\t * flow control was negotiated.\n+\t\t */\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,\n+\t\t\t\t\t       &mii_nway_adv_reg);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,\n+\t\t\t\t\t       &mii_nway_lp_ability_reg);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Two bits in the Auto Negotiation Advertisement Register\n+\t\t * (Address 4) and two bits in the Auto Negotiation Base\n+\t\t * Page Ability Register (Address 5) determine flow control\n+\t\t * for both the PHY and the link partner.  The following\n+\t\t * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,\n+\t\t * 1999, describes these PAUSE resolution bits and how flow\n+\t\t * control is determined based upon these settings.\n+\t\t * NOTE:  DC = Don't Care\n+\t\t *\n+\t\t *   LOCAL DEVICE  |   LINK PARTNER\n+\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution\n+\t\t *-------|---------|-------|---------|--------------------\n+\t\t *   0   |    0    |  DC   |   DC    | igc_fc_none\n+\t\t *   0   |    1    |   0   |   DC    | igc_fc_none\n+\t\t *   0   |    1    |   1   |    0    | igc_fc_none\n+\t\t *   0   |    1    |   1   |    1    | igc_fc_tx_pause\n+\t\t *   1   |    0    |   0   |   DC    | igc_fc_none\n+\t\t *   1   |   DC    |   1   |   DC    | igc_fc_full\n+\t\t *   1   |    1    |   0   |    0    | igc_fc_none\n+\t\t *   1   |    1    |   0   |    1    | igc_fc_rx_pause\n+\t\t *\n+\t\t * Are both PAUSE bits set to 1?  If so, this implies\n+\t\t * Symmetric Flow Control is enabled at both ends.  The\n+\t\t * ASM_DIR bits are irrelevant per the spec.\n+\t\t *\n+\t\t * For Symmetric Flow Control:\n+\t\t *\n+\t\t *   LOCAL DEVICE  |   LINK PARTNER\n+\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n+\t\t *-------|---------|-------|---------|--------------------\n+\t\t *   1   |   DC    |   1   |   DC    | IGC_fc_full\n+\t\t *\n+\t\t */\n+\t\tif ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n+\t\t    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {\n+\t\t\t/* Now we need to check if the user selected Rx ONLY\n+\t\t\t * of pause frames.  In this case, we had to advertise\n+\t\t\t * FULL flow control because we could not advertise Rx\n+\t\t\t * ONLY. Hence, we must now check to see if we need to\n+\t\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n+\t\t\t */\n+\t\t\tif (hw->fc.requested_mode == igc_fc_full) {\n+\t\t\t\thw->fc.current_mode = igc_fc_full;\n+\t\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n+\t\t\t} else {\n+\t\t\t\thw->fc.current_mode = igc_fc_rx_pause;\n+\t\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n+\t\t\t}\n+\t\t}\n+\t\t/* For receiving PAUSE frames ONLY.\n+\t\t *\n+\t\t *   LOCAL DEVICE  |   LINK PARTNER\n+\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n+\t\t *-------|---------|-------|---------|--------------------\n+\t\t *   0   |    1    |   1   |    1    | igc_fc_tx_pause\n+\t\t */\n+\t\telse if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n+\t\t\t  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n+\t\t\t  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n+\t\t\t  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n+\t\t\thw->fc.current_mode = igc_fc_tx_pause;\n+\t\t\tDEBUGOUT(\"Flow Control = Tx PAUSE frames only.\\n\");\n+\t\t}\n+\t\t/* For transmitting PAUSE frames ONLY.\n+\t\t *\n+\t\t *   LOCAL DEVICE  |   LINK PARTNER\n+\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n+\t\t *-------|---------|-------|---------|--------------------\n+\t\t *   1   |    1    |   0   |    1    | igc_fc_rx_pause\n+\t\t */\n+\t\telse if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n+\t\t\t (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n+\t\t\t !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n+\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n+\t\t\thw->fc.current_mode = igc_fc_rx_pause;\n+\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n+\t\t} else {\n+\t\t\t/* Per the IEEE spec, at this point flow control\n+\t\t\t * should be disabled.\n+\t\t\t */\n+\t\t\thw->fc.current_mode = igc_fc_none;\n+\t\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n+\t\t}\n+\n+\t\t/* Now we need to do one last check...  If we auto-\n+\t\t * negotiated to HALF DUPLEX, flow control should not be\n+\t\t * enabled per IEEE 802.3 spec.\n+\t\t */\n+\t\tret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error getting link speed and duplex\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\n+\t\tif (duplex == HALF_DUPLEX)\n+\t\t\thw->fc.current_mode = igc_fc_none;\n+\n+\t\t/* Now we call a subroutine to actually force the MAC\n+\t\t * controller to use the correct flow control settings.\n+\t\t */\n+\t\tret_val = igc_force_mac_fc_generic(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex\n+ *  @hw: pointer to the HW structure\n+ *  @speed: stores the current speed\n+ *  @duplex: stores the current duplex\n+ *\n+ *  Read the status register for the current speed/duplex and store the current\n+ *  speed and duplex for copper connections.\n+ **/\n+s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,\n+\t\t\t\t\t      u16 *duplex)\n+{\n+\tu32 status;\n+\n+\tDEBUGFUNC(\"igc_get_speed_and_duplex_copper_generic\");\n+\n+\tstatus = IGC_READ_REG(hw, IGC_STATUS);\n+\tif (status & IGC_STATUS_SPEED_1000) {\n+\t\t/* For I225, STATUS will indicate 1G speed in both 1 Gbps\n+\t\t * and 2.5 Gbps link modes. An additional bit is used\n+\t\t * to differentiate between 1 Gbps and 2.5 Gbps.\n+\t\t */\n+\t\tif (hw->mac.type == igc_i225 &&\n+\t\t    (status & IGC_STATUS_SPEED_2500)) {\n+\t\t\t*speed = SPEED_2500;\n+\t\t\tDEBUGOUT(\"2500 Mbs, \");\n+\t\t} else {\n+\t\t\t*speed = SPEED_1000;\n+\t\t\tDEBUGOUT(\"1000 Mbs, \");\n+\t\t}\n+\t} else if (status & IGC_STATUS_SPEED_100) {\n+\t\t*speed = SPEED_100;\n+\t\tDEBUGOUT(\"100 Mbs, \");\n+\t} else {\n+\t\t*speed = SPEED_10;\n+\t\tDEBUGOUT(\"10 Mbs, \");\n+\t}\n+\n+\tif (status & IGC_STATUS_FD) {\n+\t\t*duplex = FULL_DUPLEX;\n+\t\tDEBUGOUT(\"Full Duplex\\n\");\n+\t} else {\n+\t\t*duplex = HALF_DUPLEX;\n+\t\tDEBUGOUT(\"Half Duplex\\n\");\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex\n+ *  @hw: pointer to the HW structure\n+ *  @speed: stores the current speed\n+ *  @duplex: stores the current duplex\n+ *\n+ *  Sets the speed and duplex to gigabit full duplex (the only possible option)\n+ *  for fiber/serdes links.\n+ **/\n+s32\n+igc_get_speed_and_duplex_fiber_serdes_generic(struct igc_hw *hw,\n+\t\t\t\tu16 *speed, u16 *duplex)\n+{\n+\tDEBUGFUNC(\"igc_get_speed_and_duplex_fiber_serdes_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\t*speed = SPEED_1000;\n+\t*duplex = FULL_DUPLEX;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_hw_semaphore_generic - Acquire hardware semaphore\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Acquire the HW semaphore to access the PHY or NVM\n+ **/\n+s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)\n+{\n+\tu32 swsm;\n+\ts32 timeout = hw->nvm.word_size + 1;\n+\ts32 i = 0;\n+\n+\tDEBUGFUNC(\"igc_get_hw_semaphore_generic\");\n+\n+\t/* Get the SW semaphore */\n+\twhile (i < timeout) {\n+\t\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\t\tif (!(swsm & IGC_SWSM_SMBI))\n+\t\t\tbreak;\n+\n+\t\tusec_delay(50);\n+\t\ti++;\n+\t}\n+\n+\tif (i == timeout) {\n+\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\t/* Get the FW semaphore. */\n+\tfor (i = 0; i < timeout; i++) {\n+\t\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\t\tIGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);\n+\n+\t\t/* Semaphore acquired if bit latched */\n+\t\tif (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)\n+\t\t\tbreak;\n+\n+\t\tusec_delay(50);\n+\t}\n+\n+\tif (i == timeout) {\n+\t\t/* Release semaphores */\n+\t\tigc_put_hw_semaphore_generic(hw);\n+\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_put_hw_semaphore_generic - Release hardware semaphore\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Release hardware semaphore used to access the PHY or NVM\n+ **/\n+void igc_put_hw_semaphore_generic(struct igc_hw *hw)\n+{\n+\tu32 swsm;\n+\n+\tDEBUGFUNC(\"igc_put_hw_semaphore_generic\");\n+\n+\tswsm = IGC_READ_REG(hw, IGC_SWSM);\n+\n+\tswsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);\n+\n+\tIGC_WRITE_REG(hw, IGC_SWSM, swsm);\n+}\n+\n+/**\n+ *  igc_get_auto_rd_done_generic - Check for auto read completion\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Check EEPROM for Auto Read done bit.\n+ **/\n+s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)\n+{\n+\ts32 i = 0;\n+\n+\tDEBUGFUNC(\"igc_get_auto_rd_done_generic\");\n+\n+\twhile (i < AUTO_READ_DONE_TIMEOUT) {\n+\t\tif (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t\ti++;\n+\t}\n+\n+\tif (i == AUTO_READ_DONE_TIMEOUT) {\n+\t\tDEBUGOUT(\"Auto read by HW from NVM has not completed.\\n\");\n+\t\treturn -IGC_ERR_RESET;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_valid_led_default_generic - Verify a valid default LED config\n+ *  @hw: pointer to the HW structure\n+ *  @data: pointer to the NVM (EEPROM)\n+ *\n+ *  Read the EEPROM for the current default LED configuration.  If the\n+ *  LED configuration is not valid, set to a valid LED configuration.\n+ **/\n+s32 igc_valid_led_default_generic(struct igc_hw *hw, u16 *data)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_valid_led_default_generic\");\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)\n+\t\t*data = ID_LED_DEFAULT;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_id_led_init_generic -\n+ *  @hw: pointer to the HW structure\n+ *\n+ **/\n+s32 igc_id_led_init_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\ts32 ret_val;\n+\tconst u32 ledctl_mask = 0x000000FF;\n+\tconst u32 ledctl_on = IGC_LEDCTL_MODE_LED_ON;\n+\tconst u32 ledctl_off = IGC_LEDCTL_MODE_LED_OFF;\n+\tu16 data, i, temp;\n+\tconst u16 led_mask = 0x0F;\n+\n+\tDEBUGFUNC(\"igc_id_led_init_generic\");\n+\n+\tret_val = hw->nvm.ops.valid_led_default(hw, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tmac->ledctl_default = IGC_READ_REG(hw, IGC_LEDCTL);\n+\tmac->ledctl_mode1 = mac->ledctl_default;\n+\tmac->ledctl_mode2 = mac->ledctl_default;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\ttemp = (data >> (i << 2)) & led_mask;\n+\t\tswitch (temp) {\n+\t\tcase ID_LED_ON1_DEF2:\n+\t\tcase ID_LED_ON1_ON2:\n+\t\tcase ID_LED_ON1_OFF2:\n+\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n+\t\t\tmac->ledctl_mode1 |= ledctl_on << (i << 3);\n+\t\t\tbreak;\n+\t\tcase ID_LED_OFF1_DEF2:\n+\t\tcase ID_LED_OFF1_ON2:\n+\t\tcase ID_LED_OFF1_OFF2:\n+\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n+\t\t\tmac->ledctl_mode1 |= ledctl_off << (i << 3);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Do nothing */\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (temp) {\n+\t\tcase ID_LED_DEF1_ON2:\n+\t\tcase ID_LED_ON1_ON2:\n+\t\tcase ID_LED_OFF1_ON2:\n+\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n+\t\t\tmac->ledctl_mode2 |= ledctl_on << (i << 3);\n+\t\t\tbreak;\n+\t\tcase ID_LED_DEF1_OFF2:\n+\t\tcase ID_LED_ON1_OFF2:\n+\t\tcase ID_LED_OFF1_OFF2:\n+\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n+\t\t\tmac->ledctl_mode2 |= ledctl_off << (i << 3);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Do nothing */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_setup_led_generic - Configures SW controllable LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This prepares the SW controllable LED for use and saves the current state\n+ *  of the LED so it can be later restored.\n+ **/\n+s32 igc_setup_led_generic(struct igc_hw *hw)\n+{\n+\tu32 ledctl;\n+\n+\tDEBUGFUNC(\"igc_setup_led_generic\");\n+\n+\tif (hw->mac.ops.setup_led != igc_setup_led_generic)\n+\t\treturn -IGC_ERR_CONFIG;\n+\n+\tif (hw->phy.media_type == igc_media_type_fiber) {\n+\t\tledctl = IGC_READ_REG(hw, IGC_LEDCTL);\n+\t\thw->mac.ledctl_default = ledctl;\n+\t\t/* Turn off LED0 */\n+\t\tledctl &= ~(IGC_LEDCTL_LED0_IVRT | IGC_LEDCTL_LED0_BLINK |\n+\t\t\t    IGC_LEDCTL_LED0_MODE_MASK);\n+\t\tledctl |= (IGC_LEDCTL_MODE_LED_OFF <<\n+\t\t\t   IGC_LEDCTL_LED0_MODE_SHIFT);\n+\t\tIGC_WRITE_REG(hw, IGC_LEDCTL, ledctl);\n+\t} else if (hw->phy.media_type == igc_media_type_copper) {\n+\t\tIGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode1);\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_cleanup_led_generic - Set LED config to default operation\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Remove the current LED configuration and set the LED configuration\n+ *  to the default value, saved from the EEPROM.\n+ **/\n+s32 igc_cleanup_led_generic(struct igc_hw *hw)\n+{\n+\tDEBUGFUNC(\"igc_cleanup_led_generic\");\n+\n+\tIGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_default);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_blink_led_generic - Blink LED\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Blink the LEDs which are set to be on.\n+ **/\n+s32 igc_blink_led_generic(struct igc_hw *hw)\n+{\n+\tu32 ledctl_blink = 0;\n+\tu32 i;\n+\n+\tDEBUGFUNC(\"igc_blink_led_generic\");\n+\n+\tif (hw->phy.media_type == igc_media_type_fiber) {\n+\t\t/* always blink LED0 for PCI-E fiber */\n+\t\tledctl_blink = IGC_LEDCTL_LED0_BLINK |\n+\t\t     (IGC_LEDCTL_MODE_LED_ON << IGC_LEDCTL_LED0_MODE_SHIFT);\n+\t} else {\n+\t\t/* Set the blink bit for each LED that's \"on\" (0x0E)\n+\t\t * (or \"off\" if inverted) in ledctl_mode2.  The blink\n+\t\t * logic in hardware only works when mode is set to \"on\"\n+\t\t * so it must be changed accordingly when the mode is\n+\t\t * \"off\" and inverted.\n+\t\t */\n+\t\tledctl_blink = hw->mac.ledctl_mode2;\n+\t\tfor (i = 0; i < 32; i += 8) {\n+\t\t\tu32 mode = (hw->mac.ledctl_mode2 >> i) &\n+\t\t\t    IGC_LEDCTL_LED0_MODE_MASK;\n+\t\t\tu32 led_default = hw->mac.ledctl_default >> i;\n+\n+\t\t\tif ((!(led_default & IGC_LEDCTL_LED0_IVRT) &&\n+\t\t\t     mode == IGC_LEDCTL_MODE_LED_ON) ||\n+\t\t\t    ((led_default & IGC_LEDCTL_LED0_IVRT) &&\n+\t\t\t     mode == IGC_LEDCTL_MODE_LED_OFF)) {\n+\t\t\t\tledctl_blink &=\n+\t\t\t\t    ~(IGC_LEDCTL_LED0_MODE_MASK << i);\n+\t\t\t\tledctl_blink |= (IGC_LEDCTL_LED0_BLINK |\n+\t\t\t\t\t\t IGC_LEDCTL_MODE_LED_ON) << i;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tIGC_WRITE_REG(hw, IGC_LEDCTL, ledctl_blink);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_led_on_generic - Turn LED on\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Turn LED on.\n+ **/\n+s32 igc_led_on_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_led_on_generic\");\n+\n+\tswitch (hw->phy.media_type) {\n+\tcase igc_media_type_fiber:\n+\t\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\t\tctrl &= ~IGC_CTRL_SWDPIN0;\n+\t\tctrl |= IGC_CTRL_SWDPIO0;\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\t\tbreak;\n+\tcase igc_media_type_copper:\n+\t\tIGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode2);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_led_off_generic - Turn LED off\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Turn LED off.\n+ **/\n+s32 igc_led_off_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_led_off_generic\");\n+\n+\tswitch (hw->phy.media_type) {\n+\tcase igc_media_type_fiber:\n+\t\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\t\tctrl |= IGC_CTRL_SWDPIN0;\n+\t\tctrl |= IGC_CTRL_SWDPIO0;\n+\t\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\t\tbreak;\n+\tcase igc_media_type_copper:\n+\t\tIGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode1);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_set_pcie_no_snoop_generic - Set PCI-express capabilities\n+ *  @hw: pointer to the HW structure\n+ *  @no_snoop: bitmap of snoop events\n+ *\n+ *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.\n+ **/\n+void igc_set_pcie_no_snoop_generic(struct igc_hw *hw, u32 no_snoop)\n+{\n+\tu32 gcr;\n+\n+\tDEBUGFUNC(\"igc_set_pcie_no_snoop_generic\");\n+\n+\tif (hw->bus.type != igc_bus_type_pci_express)\n+\t\treturn;\n+\n+\tif (no_snoop) {\n+\t\tgcr = IGC_READ_REG(hw, IGC_GCR);\n+\t\tgcr &= ~(PCIE_NO_SNOOP_ALL);\n+\t\tgcr |= no_snoop;\n+\t\tIGC_WRITE_REG(hw, IGC_GCR, gcr);\n+\t}\n+}\n+\n+/**\n+ *  igc_disable_pcie_master_generic - Disables PCI-express master access\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Returns IGC_SUCCESS if successful, else returns -10\n+ *  (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused\n+ *  the master requests to be disabled.\n+ *\n+ *  Disables PCI-Express master access and verifies there are no pending\n+ *  requests.\n+ **/\n+s32 igc_disable_pcie_master_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl;\n+\ts32 timeout = MASTER_DISABLE_TIMEOUT;\n+\n+\tDEBUGFUNC(\"igc_disable_pcie_master_generic\");\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tctrl |= IGC_CTRL_GIO_MASTER_DISABLE;\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\n+\twhile (timeout) {\n+\t\tif (!(IGC_READ_REG(hw, IGC_STATUS) &\n+\t\t      IGC_STATUS_GIO_MASTER_ENABLE) ||\n+\t\t\t\tIGC_REMOVED(hw->hw_addr))\n+\t\t\tbreak;\n+\t\tusec_delay(100);\n+\t\ttimeout--;\n+\t}\n+\n+\tif (!timeout) {\n+\t\tDEBUGOUT(\"Master requests are pending.\\n\");\n+\t\treturn -IGC_ERR_MASTER_REQUESTS_PENDING;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_reset_adaptive_generic - Reset Adaptive Interframe Spacing\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reset the Adaptive Interframe Spacing throttle to default values.\n+ **/\n+void igc_reset_adaptive_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\n+\tDEBUGFUNC(\"igc_reset_adaptive_generic\");\n+\n+\tif (!mac->adaptive_ifs) {\n+\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tmac->current_ifs_val = 0;\n+\tmac->ifs_min_val = IFS_MIN;\n+\tmac->ifs_max_val = IFS_MAX;\n+\tmac->ifs_step_size = IFS_STEP;\n+\tmac->ifs_ratio = IFS_RATIO;\n+\n+\tmac->in_ifs_mode = false;\n+\tIGC_WRITE_REG(hw, IGC_AIT, 0);\n+}\n+\n+/**\n+ *  igc_update_adaptive_generic - Update Adaptive Interframe Spacing\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Update the Adaptive Interframe Spacing Throttle value based on the\n+ *  time between transmitted packets and time between collisions.\n+ **/\n+void igc_update_adaptive_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\n+\tDEBUGFUNC(\"igc_update_adaptive_generic\");\n+\n+\tif (!mac->adaptive_ifs) {\n+\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {\n+\t\tif (mac->tx_packet_delta > MIN_NUM_XMITS) {\n+\t\t\tmac->in_ifs_mode = true;\n+\t\t\tif (mac->current_ifs_val < mac->ifs_max_val) {\n+\t\t\t\tif (!mac->current_ifs_val)\n+\t\t\t\t\tmac->current_ifs_val = mac->ifs_min_val;\n+\t\t\t\telse\n+\t\t\t\t\tmac->current_ifs_val +=\n+\t\t\t\t\t\tmac->ifs_step_size;\n+\t\t\t\tIGC_WRITE_REG(hw, IGC_AIT,\n+\t\t\t\t\t\tmac->current_ifs_val);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tif (mac->in_ifs_mode &&\n+\t\t    mac->tx_packet_delta <= MIN_NUM_XMITS) {\n+\t\t\tmac->current_ifs_val = 0;\n+\t\t\tmac->in_ifs_mode = false;\n+\t\t\tIGC_WRITE_REG(hw, IGC_AIT, 0);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ *  igc_validate_mdi_setting_generic - Verify MDI/MDIx settings\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Verify that when not using auto-negotiation that MDI/MDIx is correctly\n+ *  set, which is forced to MDI mode only.\n+ **/\n+static s32 igc_validate_mdi_setting_generic(struct igc_hw *hw)\n+{\n+\tDEBUGFUNC(\"igc_validate_mdi_setting_generic\");\n+\n+\tif (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {\n+\t\tDEBUGOUT(\"Invalid MDI setting detected\\n\");\n+\t\thw->phy.mdix = 1;\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Validate the MDI/MDIx setting, allowing for auto-crossover during forced\n+ *  operation.\n+ **/\n+s32\n+igc_validate_mdi_setting_crossover_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_validate_mdi_setting_crossover_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register\n+ *  @hw: pointer to the HW structure\n+ *  @reg: 32bit register offset such as IGC_SCTL\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Writes an address/data control type register.  There are several of these\n+ *  and they all have the format address << 8 | data and bit 31 is polled for\n+ *  completion.\n+ **/\n+s32 igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,\n+\t\t\t\t      u32 offset, u8 data)\n+{\n+\tu32 i, regvalue = 0;\n+\n+\tDEBUGFUNC(\"igc_write_8bit_ctrl_reg_generic\");\n+\n+\t/* Set up the address and data */\n+\tregvalue = ((u32)data) | (offset << IGC_GEN_CTL_ADDRESS_SHIFT);\n+\tIGC_WRITE_REG(hw, reg, regvalue);\n+\n+\t/* Poll the ready bit to see if the MDI read completed */\n+\tfor (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {\n+\t\tusec_delay(5);\n+\t\tregvalue = IGC_READ_REG(hw, reg);\n+\t\tif (regvalue & IGC_GEN_CTL_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(regvalue & IGC_GEN_CTL_READY)) {\n+\t\tDEBUGOUT1(\"Reg %08x did not indicate ready\\n\", reg);\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\ndiff --git a/drivers/net/igc/base/e1000_mac.h b/drivers/net/igc/base/e1000_mac.h\nnew file mode 100644\nindex 0000000..f3c029d\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_mac.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_MAC_H_\n+#define _IGC_MAC_H_\n+\n+void igc_init_mac_ops_generic(struct igc_hw *hw);\n+#define IGC_REMOVED(a) (0)\n+void igc_null_mac_generic(struct igc_hw *hw);\n+s32  igc_null_ops_generic(struct igc_hw *hw);\n+s32  igc_null_link_info(struct igc_hw *hw, u16 *s, u16 *d);\n+bool igc_null_mng_mode(struct igc_hw *hw);\n+void igc_null_update_mc(struct igc_hw *hw, u8 *h, u32 a);\n+void igc_null_write_vfta(struct igc_hw *hw, u32 a, u32 b);\n+int  igc_null_rar_set(struct igc_hw *hw, u8 *h, u32 a);\n+s32  igc_blink_led_generic(struct igc_hw *hw);\n+s32  igc_check_for_copper_link_generic(struct igc_hw *hw);\n+s32  igc_check_for_fiber_link_generic(struct igc_hw *hw);\n+s32  igc_check_for_serdes_link_generic(struct igc_hw *hw);\n+s32  igc_cleanup_led_generic(struct igc_hw *hw);\n+s32  igc_commit_fc_settings_generic(struct igc_hw *hw);\n+s32  igc_poll_fiber_serdes_link_generic(struct igc_hw *hw);\n+s32  igc_config_fc_after_link_up_generic(struct igc_hw *hw);\n+s32  igc_disable_pcie_master_generic(struct igc_hw *hw);\n+s32  igc_force_mac_fc_generic(struct igc_hw *hw);\n+s32  igc_get_auto_rd_done_generic(struct igc_hw *hw);\n+s32  igc_get_bus_info_pci_generic(struct igc_hw *hw);\n+s32  igc_get_bus_info_pcie_generic(struct igc_hw *hw);\n+void igc_set_lan_id_single_port(struct igc_hw *hw);\n+void igc_set_lan_id_multi_port_pci(struct igc_hw *hw);\n+s32  igc_get_hw_semaphore_generic(struct igc_hw *hw);\n+s32  igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,\n+\t\t\t\t\t       u16 *duplex);\n+s32  igc_get_speed_and_duplex_fiber_serdes_generic(struct igc_hw *hw,\n+\t\t\t\t\t\t     u16 *speed, u16 *duplex);\n+s32  igc_id_led_init_generic(struct igc_hw *hw);\n+s32  igc_led_on_generic(struct igc_hw *hw);\n+s32  igc_led_off_generic(struct igc_hw *hw);\n+void igc_update_mc_addr_list_generic(struct igc_hw *hw,\n+\t\t\t\t       u8 *mc_addr_list, u32 mc_addr_count);\n+s32  igc_set_default_fc_generic(struct igc_hw *hw);\n+s32  igc_set_fc_watermarks_generic(struct igc_hw *hw);\n+s32  igc_setup_fiber_serdes_link_generic(struct igc_hw *hw);\n+s32  igc_setup_led_generic(struct igc_hw *hw);\n+s32  igc_setup_link_generic(struct igc_hw *hw);\n+s32  igc_validate_mdi_setting_crossover_generic(struct igc_hw *hw);\n+s32  igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,\n+\t\t\t\t       u32 offset, u8 data);\n+\n+u32  igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr);\n+\n+void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw);\n+void igc_clear_vfta_generic(struct igc_hw *hw);\n+void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count);\n+void igc_pcix_mmrbc_workaround_generic(struct igc_hw *hw);\n+void igc_put_hw_semaphore_generic(struct igc_hw *hw);\n+s32  igc_check_alt_mac_addr_generic(struct igc_hw *hw);\n+void igc_reset_adaptive_generic(struct igc_hw *hw);\n+void igc_set_pcie_no_snoop_generic(struct igc_hw *hw, u32 no_snoop);\n+void igc_update_adaptive_generic(struct igc_hw *hw);\n+void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value);\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_manage.c b/drivers/net/igc/base/e1000_manage.c\nnew file mode 100644\nindex 0000000..61ab213\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_manage.c\n@@ -0,0 +1,547 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+#include \"e1000_manage.h\"\n+\n+/**\n+ *  igc_calculate_checksum - Calculate checksum for buffer\n+ *  @buffer: pointer to EEPROM\n+ *  @length: size of EEPROM to calculate a checksum for\n+ *\n+ *  Calculates the checksum for some buffer on a specified length.  The\n+ *  checksum calculated is returned.\n+ **/\n+u8 igc_calculate_checksum(u8 *buffer, u32 length)\n+{\n+\tu32 i;\n+\tu8 sum = 0;\n+\n+\tDEBUGFUNC(\"igc_calculate_checksum\");\n+\n+\tif (!buffer)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < length; i++)\n+\t\tsum += buffer[i];\n+\n+\treturn (u8)(0 - sum);\n+}\n+\n+/**\n+ *  igc_mng_enable_host_if_generic - Checks host interface is enabled\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Returns IGC_success upon success, else IGC_ERR_HOST_INTERFACE_COMMAND\n+ *\n+ *  This function checks whether the HOST IF is enabled for command operation\n+ *  and also checks whether the previous command is completed.  It busy waits\n+ *  in case of previous command is not completed.\n+ **/\n+s32 igc_mng_enable_host_if_generic(struct igc_hw *hw)\n+{\n+\tu32 hicr;\n+\tu8 i;\n+\n+\tDEBUGFUNC(\"igc_mng_enable_host_if_generic\");\n+\n+\tif (!hw->mac.arc_subsystem_valid) {\n+\t\tDEBUGOUT(\"ARC subsystem not valid.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Check that the host interface is enabled. */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\tif (!(hicr & IGC_HICR_EN)) {\n+\t\tDEBUGOUT(\"IGC_HOST_EN bit disabled.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\t/* check the previous command is completed */\n+\tfor (i = 0; i < IGC_MNG_DHCP_COMMAND_TIMEOUT; i++) {\n+\t\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\t\tif (!(hicr & IGC_HICR_C))\n+\t\t\tbreak;\n+\t\tmsec_delay_irq(1);\n+\t}\n+\n+\tif (i == IGC_MNG_DHCP_COMMAND_TIMEOUT) {\n+\t\tDEBUGOUT(\"Previous command timeout failed .\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_check_mng_mode_generic - Generic check management mode\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the firmware semaphore register and returns true (>0) if\n+ *  manageability is enabled, else false (0).\n+ **/\n+bool igc_check_mng_mode_generic(struct igc_hw *hw)\n+{\n+\tu32 fwsm = IGC_READ_REG(hw, IGC_FWSM);\n+\n+\tDEBUGFUNC(\"igc_check_mng_mode_generic\");\n+\n+\n+\treturn (fwsm & IGC_FWSM_MODE_MASK) ==\n+\t\t(IGC_MNG_IAMT_MODE << IGC_FWSM_MODE_SHIFT);\n+}\n+\n+/**\n+ *  igc_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Enables packet filtering on transmit packets if manageability is enabled\n+ *  and host interface is enabled.\n+ **/\n+bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;\n+\tu32 *buffer = (u32 *)&hw->mng_cookie;\n+\tu32 offset;\n+\ts32 ret_val, hdr_csum, csum;\n+\tu8 i, len;\n+\n+\tDEBUGFUNC(\"igc_enable_tx_pkt_filtering_generic\");\n+\n+\thw->mac.tx_pkt_filtering = true;\n+\n+\t/* No manageability, no filtering */\n+\tif (!hw->mac.ops.check_mng_mode(hw)) {\n+\t\thw->mac.tx_pkt_filtering = false;\n+\t\treturn hw->mac.tx_pkt_filtering;\n+\t}\n+\n+\t/* If we can't read from the host interface for whatever\n+\t * reason, disable filtering.\n+\t */\n+\tret_val = igc_mng_enable_host_if_generic(hw);\n+\tif (ret_val != IGC_SUCCESS) {\n+\t\thw->mac.tx_pkt_filtering = false;\n+\t\treturn hw->mac.tx_pkt_filtering;\n+\t}\n+\n+\t/* Read in the header.  Length and offset are in dwords. */\n+\tlen    = IGC_MNG_DHCP_COOKIE_LENGTH >> 2;\n+\toffset = IGC_MNG_DHCP_COOKIE_OFFSET >> 2;\n+\tfor (i = 0; i < len; i++)\n+\t\t*(buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF,\n+\t\t\t\t\t\t\t   offset + i);\n+\thdr_csum = hdr->checksum;\n+\thdr->checksum = 0;\n+\tcsum = igc_calculate_checksum((u8 *)hdr,\n+\t\t\t\t\tIGC_MNG_DHCP_COOKIE_LENGTH);\n+\t/* If either the checksums or signature don't match, then\n+\t * the cookie area isn't considered valid, in which case we\n+\t * take the safe route of assuming Tx filtering is enabled.\n+\t */\n+\tif (hdr_csum != csum || hdr->signature != IGC_IAMT_SIGNATURE) {\n+\t\thw->mac.tx_pkt_filtering = true;\n+\t\treturn hw->mac.tx_pkt_filtering;\n+\t}\n+\n+\t/* Cookie area is valid, make the final check for filtering. */\n+\tif (!(hdr->status & IGC_MNG_DHCP_COOKIE_STATUS_PARSING))\n+\t\thw->mac.tx_pkt_filtering = false;\n+\n+\treturn hw->mac.tx_pkt_filtering;\n+}\n+\n+/**\n+ *  igc_mng_write_cmd_header_generic - Writes manageability command header\n+ *  @hw: pointer to the HW structure\n+ *  @hdr: pointer to the host interface command header\n+ *\n+ *  Writes the command header after does the checksum calculation.\n+ **/\n+s32 igc_mng_write_cmd_header_generic(struct igc_hw *hw,\n+\t\t\t\t      struct igc_host_mng_command_header *hdr)\n+{\n+\tu16 i, length = sizeof(struct igc_host_mng_command_header);\n+\n+\tDEBUGFUNC(\"igc_mng_write_cmd_header_generic\");\n+\n+\t/* Write the whole command header structure with new checksum. */\n+\n+\thdr->checksum = igc_calculate_checksum((u8 *)hdr, length);\n+\n+\tlength >>= 2;\n+\t/* Write the relevant command block into the ram area. */\n+\tfor (i = 0; i < length; i++) {\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,\n+\t\t\t\t\t*((u32 *)hdr + i));\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_mng_host_if_write_generic - Write to the manageability host interface\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: pointer to the host interface buffer\n+ *  @length: size of the buffer\n+ *  @offset: location in the buffer to write to\n+ *  @sum: sum of the data (not checksum)\n+ *\n+ *  This function writes the buffer content at the offset given on the host if.\n+ *  It also does alignment considerations to do the writes in most efficient\n+ *  way.  Also fills up the sum of the buffer in *buffer parameter.\n+ **/\n+s32 igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,\n+\t\t\t\t    u16 length, u16 offset, u8 *sum)\n+{\n+\tu8 *tmp;\n+\tu8 *bufptr = buffer;\n+\tu32 data = 0;\n+\tu16 remaining, i, j, prev_bytes;\n+\n+\tDEBUGFUNC(\"igc_mng_host_if_write_generic\");\n+\n+\t/* sum = only sum of the data and it is not checksum */\n+\n+\tif (length == 0 || offset + length > IGC_HI_MAX_MNG_DATA_LENGTH)\n+\t\treturn -IGC_ERR_PARAM;\n+\n+\ttmp = (u8 *)&data;\n+\tprev_bytes = offset & 0x3;\n+\toffset >>= 2;\n+\n+\tif (prev_bytes) {\n+\t\tdata = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset);\n+\t\tfor (j = prev_bytes; j < sizeof(u32); j++) {\n+\t\t\t*(tmp + j) = *bufptr++;\n+\t\t\t*sum += *(tmp + j);\n+\t\t}\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset, data);\n+\t\tlength -= j - prev_bytes;\n+\t\toffset++;\n+\t}\n+\n+\tremaining = length & 0x3;\n+\tlength -= remaining;\n+\n+\t/* Calculate length in DWORDs */\n+\tlength >>= 2;\n+\n+\t/* The device driver writes the relevant command block into the\n+\t * ram area.\n+\t */\n+\tfor (i = 0; i < length; i++) {\n+\t\tfor (j = 0; j < sizeof(u32); j++) {\n+\t\t\t*(tmp + j) = *bufptr++;\n+\t\t\t*sum += *(tmp + j);\n+\t\t}\n+\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,\n+\t\t\t\t\t    data);\n+\t}\n+\tif (remaining) {\n+\t\tfor (j = 0; j < sizeof(u32); j++) {\n+\t\t\tif (j < remaining)\n+\t\t\t\t*(tmp + j) = *bufptr++;\n+\t\t\telse\n+\t\t\t\t*(tmp + j) = 0;\n+\n+\t\t\t*sum += *(tmp + j);\n+\t\t}\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,\n+\t\t\t\t\t    data);\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_mng_write_dhcp_info_generic - Writes DHCP info to host interface\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: pointer to the host interface\n+ *  @length: size of the buffer\n+ *\n+ *  Writes the DHCP information to the host interface.\n+ **/\n+s32 igc_mng_write_dhcp_info_generic(struct igc_hw *hw, u8 *buffer,\n+\t\t\t\t      u16 length)\n+{\n+\tstruct igc_host_mng_command_header hdr;\n+\ts32 ret_val;\n+\tu32 hicr;\n+\n+\tDEBUGFUNC(\"igc_mng_write_dhcp_info_generic\");\n+\n+\thdr.command_id = IGC_MNG_DHCP_TX_PAYLOAD_CMD;\n+\thdr.command_length = length;\n+\thdr.reserved1 = 0;\n+\thdr.reserved2 = 0;\n+\thdr.checksum = 0;\n+\n+\t/* Enable the host interface */\n+\tret_val = igc_mng_enable_host_if_generic(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Populate the host interface with the contents of \"buffer\". */\n+\tret_val = igc_mng_host_if_write_generic(hw, buffer, length,\n+\t\t\t\t\t\tsizeof(hdr), &hdr.checksum);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Write the manageability command header */\n+\tret_val = igc_mng_write_cmd_header_generic(hw, &hdr);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Tell the ARC a new command is pending. */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\tIGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_enable_mng_pass_thru - Check if management passthrough is needed\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Verifies the hardware needs to leave interface enabled so that frames can\n+ *  be directed to and from the management interface.\n+ **/\n+bool igc_enable_mng_pass_thru(struct igc_hw *hw)\n+{\n+\tu32 manc;\n+\tu32 fwsm, factps;\n+\n+\tDEBUGFUNC(\"igc_enable_mng_pass_thru\");\n+\n+\tif (!hw->mac.asf_firmware_present)\n+\t\treturn false;\n+\n+\tmanc = IGC_READ_REG(hw, IGC_MANC);\n+\n+\tif (!(manc & IGC_MANC_RCV_TCO_EN))\n+\t\treturn false;\n+\n+\tif (hw->mac.has_fwsm) {\n+\t\tfwsm = IGC_READ_REG(hw, IGC_FWSM);\n+\t\tfactps = IGC_READ_REG(hw, IGC_FACTPS);\n+\n+\t\tif (!(factps & IGC_FACTPS_MNGCG) &&\n+\t\t    ((fwsm & IGC_FWSM_MODE_MASK) ==\n+\t\t     (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT)))\n+\t\t\treturn true;\n+\t} else if ((hw->mac.type == igc_82574) ||\n+\t\t   (hw->mac.type == igc_82583)) {\n+\t\tu16 data;\n+\t\ts32 ret_val;\n+\n+\t\tfactps = IGC_READ_REG(hw, IGC_FACTPS);\n+\t\tret_val = igc_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);\n+\t\tif (ret_val)\n+\t\t\treturn false;\n+\n+\t\tif (!(factps & IGC_FACTPS_MNGCG) &&\n+\t\t    ((data & IGC_NVM_INIT_CTRL2_MNGM) ==\n+\t\t     (igc_mng_mode_pt << 13)))\n+\t\t\treturn true;\n+\t} else if ((manc & IGC_MANC_SMBUS_EN) &&\n+\t\t   !(manc & IGC_MANC_ASF_EN)) {\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+/**\n+ *  igc_host_interface_command - Writes buffer to host interface\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: contains a command to write\n+ *  @length: the byte length of the buffer, must be multiple of 4 bytes\n+ *\n+ *  Writes a buffer to the Host Interface.  Upon success, returns IGC_SUCCESS\n+ *  else returns IGC_ERR_HOST_INTERFACE_COMMAND.\n+ **/\n+s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length)\n+{\n+\tu32 hicr, i;\n+\n+\tDEBUGFUNC(\"igc_host_interface_command\");\n+\n+\tif (!(hw->mac.arc_subsystem_valid)) {\n+\t\tDEBUGOUT(\"Hardware doesn't support host interface command.\\n\");\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tif (!hw->mac.asf_firmware_present) {\n+\t\tDEBUGOUT(\"Firmware is not present.\\n\");\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tif (length == 0 || length & 0x3 ||\n+\t    length > IGC_HI_MAX_BLOCK_BYTE_LENGTH) {\n+\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Check that the host interface is enabled. */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\tif (!(hicr & IGC_HICR_EN)) {\n+\t\tDEBUGOUT(\"IGC_HOST_EN bit disabled.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Calculate length in DWORDs */\n+\tlength >>= 2;\n+\n+\t/* The device driver writes the relevant command block\n+\t * into the ram area.\n+\t */\n+\tfor (i = 0; i < length; i++)\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,\n+\t\t\t\t\t    *((u32 *)buffer + i));\n+\n+\t/* Setting this bit tells the ARC that a new command is pending. */\n+\tIGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);\n+\n+\tfor (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {\n+\t\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\t\tif (!(hicr & IGC_HICR_C))\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t}\n+\n+\t/* Check command successful completion. */\n+\tif (i == IGC_HI_COMMAND_TIMEOUT ||\n+\t    (!(IGC_READ_REG(hw, IGC_HICR) & IGC_HICR_SV))) {\n+\t\tDEBUGOUT(\"Command has failed with no status valid.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\tfor (i = 0; i < length; i++)\n+\t\t*((u32 *)buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw,\n+\t\t\t\t\t\t\t\t  IGC_HOST_IF,\n+\t\t\t\t\t\t\t\t  i);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_load_firmware - Writes proxy FW code buffer to host interface\n+ *                        and execute.\n+ *  @hw: pointer to the HW structure\n+ *  @buffer: contains a firmware to write\n+ *  @length: the byte length of the buffer, must be multiple of 4 bytes\n+ *\n+ *  Upon success returns IGC_SUCCESS, returns IGC_ERR_CONFIG if not enabled\n+ *  in HW else returns IGC_ERR_HOST_INTERFACE_COMMAND.\n+ **/\n+s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length)\n+{\n+\tu32 hicr, hibba, fwsm, icr, i;\n+\n+\tDEBUGFUNC(\"igc_load_firmware\");\n+\n+\tif (hw->mac.type < igc_i210) {\n+\t\tDEBUGOUT(\"Hardware doesn't support loading FW by the driver\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\t/* Check that the host interface is enabled. */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\tif (!(hicr & IGC_HICR_EN)) {\n+\t\tDEBUGOUT(\"IGC_HOST_EN bit disabled.\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\tif (!(hicr & IGC_HICR_MEMORY_BASE_EN)) {\n+\t\tDEBUGOUT(\"IGC_HICR_MEMORY_BASE_EN bit disabled.\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tif (length == 0 || length & 0x3 || length > IGC_HI_FW_MAX_LENGTH) {\n+\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n+\t\treturn -IGC_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\t/* Clear notification from ROM-FW by reading ICR register */\n+\ticr = IGC_READ_REG(hw, IGC_ICR_V2);\n+\n+\t/* Reset ROM-FW */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\thicr |= IGC_HICR_FW_RESET_ENABLE;\n+\tIGC_WRITE_REG(hw, IGC_HICR, hicr);\n+\thicr |= IGC_HICR_FW_RESET;\n+\tIGC_WRITE_REG(hw, IGC_HICR, hicr);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\t/* Wait till MAC notifies about its readiness after ROM-FW reset */\n+\tfor (i = 0; i < (IGC_HI_COMMAND_TIMEOUT * 2); i++) {\n+\t\ticr = IGC_READ_REG(hw, IGC_ICR_V2);\n+\t\tif (icr & IGC_ICR_MNG)\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t}\n+\n+\t/* Check for timeout */\n+\tif (i == IGC_HI_COMMAND_TIMEOUT) {\n+\t\tDEBUGOUT(\"FW reset failed.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Wait till MAC is ready to accept new FW code */\n+\tfor (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {\n+\t\tfwsm = IGC_READ_REG(hw, IGC_FWSM);\n+\t\tif ((fwsm & IGC_FWSM_FW_VALID) &&\n+\t\t    ((fwsm & IGC_FWSM_MODE_MASK) >> IGC_FWSM_MODE_SHIFT ==\n+\t\t    IGC_FWSM_HI_EN_ONLY_MODE))\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t}\n+\n+\t/* Check for timeout */\n+\tif (i == IGC_HI_COMMAND_TIMEOUT) {\n+\t\tDEBUGOUT(\"FW reset failed.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Calculate length in DWORDs */\n+\tlength >>= 2;\n+\n+\t/* The device driver writes the relevant FW code block\n+\t * into the ram area in DWORDs via 1kB ram addressing window.\n+\t */\n+\tfor (i = 0; i < length; i++) {\n+\t\tif (!(i % IGC_HI_FW_BLOCK_DWORD_LENGTH)) {\n+\t\t\t/* Point to correct 1kB ram window */\n+\t\t\thibba = IGC_HI_FW_BASE_ADDRESS +\n+\t\t\t\t((IGC_HI_FW_BLOCK_DWORD_LENGTH << 2) *\n+\t\t\t\t(i / IGC_HI_FW_BLOCK_DWORD_LENGTH));\n+\n+\t\t\tIGC_WRITE_REG(hw, IGC_HIBBA, hibba);\n+\t\t}\n+\n+\t\tIGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF,\n+\t\t\t\t\t    i % IGC_HI_FW_BLOCK_DWORD_LENGTH,\n+\t\t\t\t\t    *((u32 *)buffer + i));\n+\t}\n+\n+\t/* Setting this bit tells the ARC that a new FW is ready to execute. */\n+\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\tIGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);\n+\n+\tfor (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {\n+\t\thicr = IGC_READ_REG(hw, IGC_HICR);\n+\t\tif (!(hicr & IGC_HICR_C))\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t}\n+\n+\t/* Check for successful FW start. */\n+\tif (i == IGC_HI_COMMAND_TIMEOUT) {\n+\t\tDEBUGOUT(\"New FW did not start within timeout period.\\n\");\n+\t\treturn -IGC_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\ndiff --git a/drivers/net/igc/base/e1000_manage.h b/drivers/net/igc/base/e1000_manage.h\nnew file mode 100644\nindex 0000000..e4e5459\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_manage.h\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_MANAGE_H_\n+#define _IGC_MANAGE_H_\n+\n+bool igc_check_mng_mode_generic(struct igc_hw *hw);\n+bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw);\n+s32  igc_mng_enable_host_if_generic(struct igc_hw *hw);\n+s32  igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,\n+\t\t\t\t     u16 length, u16 offset, u8 *sum);\n+s32  igc_mng_write_cmd_header_generic(struct igc_hw *hw,\n+\t\t\t\t     struct igc_host_mng_command_header *hdr);\n+s32  igc_mng_write_dhcp_info_generic(struct igc_hw *hw,\n+\t\t\t\t       u8 *buffer, u16 length);\n+bool igc_enable_mng_pass_thru(struct igc_hw *hw);\n+u8 igc_calculate_checksum(u8 *buffer, u32 length);\n+s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length);\n+s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length);\n+\n+enum igc_mng_mode {\n+\tigc_mng_mode_none = 0,\n+\tigc_mng_mode_asf,\n+\tigc_mng_mode_pt,\n+\tigc_mng_mode_ipmi,\n+\tigc_mng_mode_host_if_only\n+};\n+\n+#define IGC_FACTPS_MNGCG\t\t\t0x20000000\n+\n+#define IGC_FWSM_MODE_MASK\t\t\t0xE\n+#define IGC_FWSM_MODE_SHIFT\t\t\t1\n+#define IGC_FWSM_FW_VALID\t\t\t0x00008000\n+#define IGC_FWSM_HI_EN_ONLY_MODE\t\t0x4\n+\n+#define IGC_MNG_IAMT_MODE\t\t\t0x3\n+#define IGC_MNG_DHCP_COOKIE_LENGTH\t\t0x10\n+#define IGC_MNG_DHCP_COOKIE_OFFSET\t\t0x6F0\n+#define IGC_MNG_DHCP_COMMAND_TIMEOUT\t\t10\n+#define IGC_MNG_DHCP_TX_PAYLOAD_CMD\t\t64\n+#define IGC_MNG_DHCP_COOKIE_STATUS_PARSING\t0x1\n+#define IGC_MNG_DHCP_COOKIE_STATUS_VLAN\t0x2\n+\n+#define IGC_VFTA_ENTRY_SHIFT\t\t\t5\n+#define IGC_VFTA_ENTRY_MASK\t\t\t0x7F\n+#define IGC_VFTA_ENTRY_BIT_SHIFT_MASK\t\t0x1F\n+\n+#define IGC_HI_MAX_BLOCK_BYTE_LENGTH\t\t1792 /* Num of bytes in range */\n+#define IGC_HI_MAX_BLOCK_DWORD_LENGTH\t\t448 /* Num of dwords in range */\n+#define IGC_HI_COMMAND_TIMEOUT\t\t500 /* Process HI cmd limit */\n+#define IGC_HI_FW_BASE_ADDRESS\t\t0x10000\n+#define IGC_HI_FW_MAX_LENGTH\t\t\t(64 * 1024) /* Num of bytes */\n+#define IGC_HI_FW_BLOCK_DWORD_LENGTH\t\t256 /* Num of DWORDs per page */\n+#define IGC_HICR_MEMORY_BASE_EN\t\t0x200 /* MB Enable bit - RO */\n+#define IGC_HICR_EN\t\t\t0x01  /* Enable bit - RO */\n+/* Driver sets this bit when done to put command in RAM */\n+#define IGC_HICR_C\t\t\t0x02\n+#define IGC_HICR_SV\t\t\t0x04  /* Status Validity */\n+#define IGC_HICR_FW_RESET_ENABLE\t0x40\n+#define IGC_HICR_FW_RESET\t\t0x80\n+\n+/* Intel(R) Active Management Technology signature */\n+#define IGC_IAMT_SIGNATURE\t\t0x544D4149\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_nvm.c b/drivers/net/igc/base/e1000_nvm.c\nnew file mode 100644\nindex 0000000..5545a93\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_nvm.c\n@@ -0,0 +1,1324 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+static void igc_reload_nvm_generic(struct igc_hw *hw);\n+\n+/**\n+ *  igc_init_nvm_ops_generic - Initialize NVM function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Setups up the function pointers to no-op functions\n+ **/\n+void igc_init_nvm_ops_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tDEBUGFUNC(\"igc_init_nvm_ops_generic\");\n+\n+\t/* Initialize function pointers */\n+\tnvm->ops.init_params = igc_null_ops_generic;\n+\tnvm->ops.acquire = igc_null_ops_generic;\n+\tnvm->ops.read = igc_null_read_nvm;\n+\tnvm->ops.release = igc_null_nvm_generic;\n+\tnvm->ops.reload = igc_reload_nvm_generic;\n+\tnvm->ops.update = igc_null_ops_generic;\n+\tnvm->ops.valid_led_default = igc_null_led_default;\n+\tnvm->ops.validate = igc_null_ops_generic;\n+\tnvm->ops.write = igc_null_write_nvm;\n+}\n+\n+/**\n+ *  igc_null_nvm_read - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @a: dummy variable\n+ *  @b: dummy variable\n+ *  @c: dummy variable\n+ **/\n+s32 igc_null_read_nvm(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\tu16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b,\n+\t\t\tu16 IGC_UNUSEDARG * c)\n+{\n+\tDEBUGFUNC(\"igc_null_read_nvm\");\n+\tUNREFERENCED_4PARAMETER(hw, a, b, c);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_nvm_generic - No-op function, return void\n+ *  @hw: pointer to the HW structure\n+ **/\n+void igc_null_nvm_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_null_nvm_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+}\n+\n+/**\n+ *  igc_null_led_default - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @data: dummy variable\n+ **/\n+s32 igc_null_led_default(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t   u16 IGC_UNUSEDARG * data)\n+{\n+\tDEBUGFUNC(\"igc_null_led_default\");\n+\tUNREFERENCED_2PARAMETER(hw, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_write_nvm - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @a: dummy variable\n+ *  @b: dummy variable\n+ *  @c: dummy variable\n+ **/\n+s32 igc_null_write_nvm(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t u16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b,\n+\t\t\t u16 IGC_UNUSEDARG * c)\n+{\n+\tDEBUGFUNC(\"igc_null_write_nvm\");\n+\tUNREFERENCED_4PARAMETER(hw, a, b, c);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_raise_eec_clk - Raise EEPROM clock\n+ *  @hw: pointer to the HW structure\n+ *  @eecd: pointer to the EEPROM\n+ *\n+ *  Enable/Raise the EEPROM clock bit.\n+ **/\n+static void igc_raise_eec_clk(struct igc_hw *hw, u32 *eecd)\n+{\n+\t*eecd = *eecd | IGC_EECD_SK;\n+\tIGC_WRITE_REG(hw, IGC_EECD, *eecd);\n+\tIGC_WRITE_FLUSH(hw);\n+\tusec_delay(hw->nvm.delay_usec);\n+}\n+\n+/**\n+ *  igc_lower_eec_clk - Lower EEPROM clock\n+ *  @hw: pointer to the HW structure\n+ *  @eecd: pointer to the EEPROM\n+ *\n+ *  Clear/Lower the EEPROM clock bit.\n+ **/\n+static void igc_lower_eec_clk(struct igc_hw *hw, u32 *eecd)\n+{\n+\t*eecd = *eecd & ~IGC_EECD_SK;\n+\tIGC_WRITE_REG(hw, IGC_EECD, *eecd);\n+\tIGC_WRITE_FLUSH(hw);\n+\tusec_delay(hw->nvm.delay_usec);\n+}\n+\n+/**\n+ *  igc_shift_out_eec_bits - Shift data bits our to the EEPROM\n+ *  @hw: pointer to the HW structure\n+ *  @data: data to send to the EEPROM\n+ *  @count: number of bits to shift out\n+ *\n+ *  We need to shift 'count' bits out to the EEPROM.  So, the value in the\n+ *  \"data\" parameter will be shifted out to the EEPROM one bit at a time.\n+ *  In order to do this, \"data\" must be broken down into bits.\n+ **/\n+static void igc_shift_out_eec_bits(struct igc_hw *hw, u16 data, u16 count)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 eecd = IGC_READ_REG(hw, IGC_EECD);\n+\tu32 mask;\n+\n+\tDEBUGFUNC(\"igc_shift_out_eec_bits\");\n+\n+\tmask = 0x01 << (count - 1);\n+\tif (nvm->type == igc_nvm_eeprom_microwire)\n+\t\teecd &= ~IGC_EECD_DO;\n+\telse if (nvm->type == igc_nvm_eeprom_spi)\n+\t\teecd |= IGC_EECD_DO;\n+\n+\tdo {\n+\t\teecd &= ~IGC_EECD_DI;\n+\n+\t\tif (data & mask)\n+\t\t\teecd |= IGC_EECD_DI;\n+\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\n+\t\tusec_delay(nvm->delay_usec);\n+\n+\t\tigc_raise_eec_clk(hw, &eecd);\n+\t\tigc_lower_eec_clk(hw, &eecd);\n+\n+\t\tmask >>= 1;\n+\t} while (mask);\n+\n+\teecd &= ~IGC_EECD_DI;\n+\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+}\n+\n+/**\n+ *  igc_shift_in_eec_bits - Shift data bits in from the EEPROM\n+ *  @hw: pointer to the HW structure\n+ *  @count: number of bits to shift in\n+ *\n+ *  In order to read a register from the EEPROM, we need to shift 'count' bits\n+ *  in from the EEPROM.  Bits are \"shifted in\" by raising the clock input to\n+ *  the EEPROM (setting the SK bit), and then reading the value of the data out\n+ *  \"DO\" bit.  During this \"shifting in\" process the data in \"DI\" bit should\n+ *  always be clear.\n+ **/\n+static u16 igc_shift_in_eec_bits(struct igc_hw *hw, u16 count)\n+{\n+\tu32 eecd;\n+\tu32 i;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_shift_in_eec_bits\");\n+\n+\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\n+\teecd &= ~(IGC_EECD_DO | IGC_EECD_DI);\n+\tdata = 0;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tdata <<= 1;\n+\t\tigc_raise_eec_clk(hw, &eecd);\n+\n+\t\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\n+\t\teecd &= ~IGC_EECD_DI;\n+\t\tif (eecd & IGC_EECD_DO)\n+\t\t\tdata |= 1;\n+\n+\t\tigc_lower_eec_clk(hw, &eecd);\n+\t}\n+\n+\treturn data;\n+}\n+\n+/**\n+ *  igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion\n+ *  @hw: pointer to the HW structure\n+ *  @ee_reg: EEPROM flag for polling\n+ *\n+ *  Polls the EEPROM status bit for either read or write completion based\n+ *  upon the value of 'ee_reg'.\n+ **/\n+s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg)\n+{\n+\tu32 attempts = 100000;\n+\tu32 i, reg = 0;\n+\n+\tDEBUGFUNC(\"igc_poll_eerd_eewr_done\");\n+\n+\tfor (i = 0; i < attempts; i++) {\n+\t\tif (ee_reg == IGC_NVM_POLL_READ)\n+\t\t\treg = IGC_READ_REG(hw, IGC_EERD);\n+\t\telse\n+\t\t\treg = IGC_READ_REG(hw, IGC_EEWR);\n+\n+\t\tif (reg & IGC_NVM_RW_REG_DONE)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tusec_delay(5);\n+\t}\n+\n+\treturn -IGC_ERR_NVM;\n+}\n+\n+/**\n+ *  igc_acquire_nvm_generic - Generic request for access to EEPROM\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Set the EEPROM access request bit and wait for EEPROM access grant bit.\n+ *  Return successful if access grant bit set, else clear the request for\n+ *  EEPROM access and return -IGC_ERR_NVM (-1).\n+ **/\n+s32 igc_acquire_nvm_generic(struct igc_hw *hw)\n+{\n+\tu32 eecd = IGC_READ_REG(hw, IGC_EECD);\n+\ts32 timeout = IGC_NVM_GRANT_ATTEMPTS;\n+\n+\tDEBUGFUNC(\"igc_acquire_nvm_generic\");\n+\n+\tIGC_WRITE_REG(hw, IGC_EECD, eecd | IGC_EECD_REQ);\n+\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\n+\twhile (timeout) {\n+\t\tif (eecd & IGC_EECD_GNT)\n+\t\t\tbreak;\n+\t\tusec_delay(5);\n+\t\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\t\ttimeout--;\n+\t}\n+\n+\tif (!timeout) {\n+\t\teecd &= ~IGC_EECD_REQ;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tDEBUGOUT(\"Could not acquire NVM grant\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_standby_nvm - Return EEPROM to standby state\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Return the EEPROM to a standby state.\n+ **/\n+static void igc_standby_nvm(struct igc_hw *hw)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 eecd = IGC_READ_REG(hw, IGC_EECD);\n+\n+\tDEBUGFUNC(\"igc_standby_nvm\");\n+\n+\tif (nvm->type == igc_nvm_eeprom_microwire) {\n+\t\teecd &= ~(IGC_EECD_CS | IGC_EECD_SK);\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t\tusec_delay(nvm->delay_usec);\n+\n+\t\tigc_raise_eec_clk(hw, &eecd);\n+\n+\t\t/* Select EEPROM */\n+\t\teecd |= IGC_EECD_CS;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t\tusec_delay(nvm->delay_usec);\n+\n+\t\tigc_lower_eec_clk(hw, &eecd);\n+\t} else if (nvm->type == igc_nvm_eeprom_spi) {\n+\t\t/* Toggle CS to flush commands */\n+\t\teecd |= IGC_EECD_CS;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t\tusec_delay(nvm->delay_usec);\n+\t\teecd &= ~IGC_EECD_CS;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t\tusec_delay(nvm->delay_usec);\n+\t}\n+}\n+\n+/**\n+ *  igc_stop_nvm - Terminate EEPROM command\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Terminates the current command by inverting the EEPROM's chip select pin.\n+ **/\n+void igc_stop_nvm(struct igc_hw *hw)\n+{\n+\tu32 eecd;\n+\n+\tDEBUGFUNC(\"igc_stop_nvm\");\n+\n+\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\tif (hw->nvm.type == igc_nvm_eeprom_spi) {\n+\t\t/* Pull CS high */\n+\t\teecd |= IGC_EECD_CS;\n+\t\tigc_lower_eec_clk(hw, &eecd);\n+\t} else if (hw->nvm.type == igc_nvm_eeprom_microwire) {\n+\t\t/* CS on Microwire is active-high */\n+\t\teecd &= ~(IGC_EECD_CS | IGC_EECD_DI);\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tigc_raise_eec_clk(hw, &eecd);\n+\t\tigc_lower_eec_clk(hw, &eecd);\n+\t}\n+}\n+\n+/**\n+ *  igc_release_nvm_generic - Release exclusive access to EEPROM\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Stop any current commands to the EEPROM and clear the EEPROM request bit.\n+ **/\n+void igc_release_nvm_generic(struct igc_hw *hw)\n+{\n+\tu32 eecd;\n+\n+\tDEBUGFUNC(\"igc_release_nvm_generic\");\n+\n+\tigc_stop_nvm(hw);\n+\n+\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\teecd &= ~IGC_EECD_REQ;\n+\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+}\n+\n+/**\n+ *  igc_ready_nvm_eeprom - Prepares EEPROM for read/write\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Setups the EEPROM for reading and writing.\n+ **/\n+static s32 igc_ready_nvm_eeprom(struct igc_hw *hw)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 eecd = IGC_READ_REG(hw, IGC_EECD);\n+\tu8 spi_stat_reg;\n+\n+\tDEBUGFUNC(\"igc_ready_nvm_eeprom\");\n+\n+\tif (nvm->type == igc_nvm_eeprom_microwire) {\n+\t\t/* Clear SK and DI */\n+\t\teecd &= ~(IGC_EECD_DI | IGC_EECD_SK);\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\t/* Set CS */\n+\t\teecd |= IGC_EECD_CS;\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t} else if (nvm->type == igc_nvm_eeprom_spi) {\n+\t\tu16 timeout = NVM_MAX_RETRY_SPI;\n+\n+\t\t/* Clear SK and CS */\n+\t\teecd &= ~(IGC_EECD_CS | IGC_EECD_SK);\n+\t\tIGC_WRITE_REG(hw, IGC_EECD, eecd);\n+\t\tIGC_WRITE_FLUSH(hw);\n+\t\tusec_delay(1);\n+\n+\t\t/* Read \"Status Register\" repeatedly until the LSB is cleared.\n+\t\t * The EEPROM will signal that the command has been completed\n+\t\t * by clearing bit 0 of the internal status register.  If it's\n+\t\t * not cleared within 'timeout', then error out.\n+\t\t */\n+\t\twhile (timeout) {\n+\t\t\tigc_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,\n+\t\t\t\t\t\t hw->nvm.opcode_bits);\n+\t\t\tspi_stat_reg = (u8)igc_shift_in_eec_bits(hw, 8);\n+\t\t\tif (!(spi_stat_reg & NVM_STATUS_RDY_SPI))\n+\t\t\t\tbreak;\n+\n+\t\t\tusec_delay(5);\n+\t\t\tigc_standby_nvm(hw);\n+\t\t\ttimeout--;\n+\t\t}\n+\n+\t\tif (!timeout) {\n+\t\t\tDEBUGOUT(\"SPI NVM Status error\\n\");\n+\t\t\treturn -IGC_ERR_NVM;\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_nvm_spi - Read EEPROM's using SPI\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset of word in the EEPROM to read\n+ *  @words: number of words to read\n+ *  @data: word read from the EEPROM\n+ *\n+ *  Reads a 16 bit word from the EEPROM.\n+ **/\n+s32 igc_read_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 i = 0;\n+\ts32 ret_val;\n+\tu16 word_in;\n+\tu8 read_opcode = NVM_READ_OPCODE_SPI;\n+\n+\tDEBUGFUNC(\"igc_read_nvm_spi\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\tret_val = nvm->ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_ready_nvm_eeprom(hw);\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\tigc_standby_nvm(hw);\n+\n+\tif (nvm->address_bits == 8 && offset >= 128)\n+\t\tread_opcode |= NVM_A8_OPCODE_SPI;\n+\n+\t/* Send the READ command (opcode + addr) */\n+\tigc_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);\n+\tigc_shift_out_eec_bits(hw, (u16)(offset * 2), nvm->address_bits);\n+\n+\t/* Read the data.  SPI NVMs increment the address with each byte\n+\t * read and will roll over if reading beyond the end.  This allows\n+\t * us to read the whole NVM from any offset\n+\t */\n+\tfor (i = 0; i < words; i++) {\n+\t\tword_in = igc_shift_in_eec_bits(hw, 16);\n+\t\tdata[i] = (word_in >> 8) | (word_in << 8);\n+\t}\n+\n+release:\n+\tnvm->ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_nvm_microwire - Reads EEPROM's using microwire\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset of word in the EEPROM to read\n+ *  @words: number of words to read\n+ *  @data: word read from the EEPROM\n+ *\n+ *  Reads a 16 bit word from the EEPROM.\n+ **/\n+s32 igc_read_nvm_microwire(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t     u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 i = 0;\n+\ts32 ret_val;\n+\tu8 read_opcode = NVM_READ_OPCODE_MICROWIRE;\n+\n+\tDEBUGFUNC(\"igc_read_nvm_microwire\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\tret_val = nvm->ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_ready_nvm_eeprom(hw);\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\tfor (i = 0; i < words; i++) {\n+\t\t/* Send the READ command (opcode + addr) */\n+\t\tigc_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);\n+\t\tigc_shift_out_eec_bits(hw, (u16)(offset + i),\n+\t\t\t\t\tnvm->address_bits);\n+\n+\t\t/* Read the data.  For microwire, each word requires the\n+\t\t * overhead of setup and tear-down.\n+\t\t */\n+\t\tdata[i] = igc_shift_in_eec_bits(hw, 16);\n+\t\tigc_standby_nvm(hw);\n+\t}\n+\n+release:\n+\tnvm->ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_nvm_eerd - Reads EEPROM using EERD register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset of word in the EEPROM to read\n+ *  @words: number of words to read\n+ *  @data: word read from the EEPROM\n+ *\n+ *  Reads a 16 bit word from the EEPROM using the EERD register.\n+ **/\n+s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words, u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\tu32 i, eerd = 0;\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_read_nvm_eerd\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * too many words for the offset, and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\tfor (i = 0; i < words; i++) {\n+\t\teerd = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) +\n+\t\t       IGC_NVM_RW_REG_START;\n+\n+\t\tIGC_WRITE_REG(hw, IGC_EERD, eerd);\n+\t\tret_val = igc_poll_eerd_eewr_done(hw, IGC_NVM_POLL_READ);\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\n+\t\tdata[i] = (IGC_READ_REG(hw, IGC_EERD) >>\n+\t\t\t   IGC_NVM_RW_REG_DATA);\n+\t}\n+\n+\tif (ret_val)\n+\t\tDEBUGOUT1(\"NVM read error: %d\\n\", ret_val);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_nvm_spi - Write to EEPROM using SPI\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset within the EEPROM to be written to\n+ *  @words: number of words to write\n+ *  @data: 16 bit word(s) to be written to the EEPROM\n+ *\n+ *  Writes data to EEPROM at offset using SPI interface.\n+ *\n+ *  If igc_update_nvm_checksum is not called after this function , the\n+ *  EEPROM will most likely contain an invalid checksum.\n+ **/\n+s32 igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\ts32 ret_val = -IGC_ERR_NVM;\n+\tu16 widx = 0;\n+\n+\tDEBUGFUNC(\"igc_write_nvm_spi\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\twhile (widx < words) {\n+\t\tu8 write_opcode = NVM_WRITE_OPCODE_SPI;\n+\n+\t\tret_val = nvm->ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = igc_ready_nvm_eeprom(hw);\n+\t\tif (ret_val) {\n+\t\t\tnvm->ops.release(hw);\n+\t\t\treturn ret_val;\n+\t\t}\n+\n+\t\tigc_standby_nvm(hw);\n+\n+\t\t/* Send the WRITE ENABLE command (8 bit opcode) */\n+\t\tigc_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,\n+\t\t\t\t\t nvm->opcode_bits);\n+\n+\t\tigc_standby_nvm(hw);\n+\n+\t\t/* Some SPI eeproms use the 8th address bit embedded in the\n+\t\t * opcode\n+\t\t */\n+\t\tif (nvm->address_bits == 8 && offset >= 128)\n+\t\t\twrite_opcode |= NVM_A8_OPCODE_SPI;\n+\n+\t\t/* Send the Write command (8-bit opcode + addr) */\n+\t\tigc_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);\n+\t\tigc_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),\n+\t\t\t\t\t nvm->address_bits);\n+\n+\t\t/* Loop to allow for up to whole page write of eeprom */\n+\t\twhile (widx < words) {\n+\t\t\tu16 word_out = data[widx];\n+\t\t\tword_out = (word_out >> 8) | (word_out << 8);\n+\t\t\tigc_shift_out_eec_bits(hw, word_out, 16);\n+\t\t\twidx++;\n+\n+\t\t\tif ((((offset + widx) * 2) % nvm->page_size) == 0) {\n+\t\t\t\tigc_standby_nvm(hw);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tmsec_delay(10);\n+\t\tnvm->ops.release(hw);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_nvm_microwire - Writes EEPROM using microwire\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset within the EEPROM to be written to\n+ *  @words: number of words to write\n+ *  @data: 16 bit word(s) to be written to the EEPROM\n+ *\n+ *  Writes data to EEPROM at offset using microwire interface.\n+ *\n+ *  If igc_update_nvm_checksum is not called after this function , the\n+ *  EEPROM will most likely contain an invalid checksum.\n+ **/\n+s32 igc_write_nvm_microwire(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t      u16 *data)\n+{\n+\tstruct igc_nvm_info *nvm = &hw->nvm;\n+\ts32  ret_val;\n+\tu32 eecd;\n+\tu16 words_written = 0;\n+\tu16 widx = 0;\n+\n+\tDEBUGFUNC(\"igc_write_nvm_microwire\");\n+\n+\t/* A check for invalid values:  offset too large, too many words,\n+\t * and not enough words.\n+\t */\n+\tif (offset >= nvm->word_size || words > (nvm->word_size - offset) ||\n+\t\t\twords == 0) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\tret_val = nvm->ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_ready_nvm_eeprom(hw);\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\tigc_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,\n+\t\t\t\t (u16)(nvm->opcode_bits + 2));\n+\n+\tigc_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));\n+\n+\tigc_standby_nvm(hw);\n+\n+\twhile (words_written < words) {\n+\t\tigc_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,\n+\t\t\t\t\t nvm->opcode_bits);\n+\n+\t\tigc_shift_out_eec_bits(hw, (u16)(offset + words_written),\n+\t\t\t\t\t nvm->address_bits);\n+\n+\t\tigc_shift_out_eec_bits(hw, data[words_written], 16);\n+\n+\t\tigc_standby_nvm(hw);\n+\n+\t\tfor (widx = 0; widx < 200; widx++) {\n+\t\t\teecd = IGC_READ_REG(hw, IGC_EECD);\n+\t\t\tif (eecd & IGC_EECD_DO)\n+\t\t\t\tbreak;\n+\t\t\tusec_delay(50);\n+\t\t}\n+\n+\t\tif (widx == 200) {\n+\t\t\tDEBUGOUT(\"NVM Write did not complete\\n\");\n+\t\t\tret_val = -IGC_ERR_NVM;\n+\t\t\tgoto release;\n+\t\t}\n+\n+\t\tigc_standby_nvm(hw);\n+\n+\t\twords_written++;\n+\t}\n+\n+\tigc_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,\n+\t\t\t\t (u16)(nvm->opcode_bits + 2));\n+\n+\tigc_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));\n+\n+release:\n+\tnvm->ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_pba_string_generic - Read device part number\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num: pointer to device part number\n+ *  @pba_num_size: size of part number buffer\n+ *\n+ *  Reads the product board assembly (PBA) number from the EEPROM and stores\n+ *  the value in pba_num.\n+ **/\n+s32 igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,\n+\t\t\t\t  u32 pba_num_size)\n+{\n+\ts32 ret_val;\n+\tu16 nvm_data;\n+\tu16 pba_ptr;\n+\tu16 offset;\n+\tu16 length;\n+\n+\tDEBUGFUNC(\"igc_read_pba_string_generic\");\n+\n+\tif (pba_num == NULL) {\n+\t\tDEBUGOUT(\"PBA string buffer was null\\n\");\n+\t\treturn -IGC_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* if nvm_data is not ptr guard the PBA must be in legacy format which\n+\t * means pba_ptr is actually our second data word for the PBA number\n+\t * and we can decode it into an ascii string\n+\t */\n+\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n+\t\tDEBUGOUT(\"NVM PBA number is not stored as string\\n\");\n+\n+\t\t/* make sure callers buffer is big enough to store the PBA */\n+\t\tif (pba_num_size < IGC_PBANUM_LENGTH) {\n+\t\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n+\t\t\treturn IGC_ERR_NO_SPACE;\n+\t\t}\n+\n+\t\t/* extract hex string from data and pba_ptr */\n+\t\tpba_num[0] = (nvm_data >> 12) & 0xF;\n+\t\tpba_num[1] = (nvm_data >> 8) & 0xF;\n+\t\tpba_num[2] = (nvm_data >> 4) & 0xF;\n+\t\tpba_num[3] = nvm_data & 0xF;\n+\t\tpba_num[4] = (pba_ptr >> 12) & 0xF;\n+\t\tpba_num[5] = (pba_ptr >> 8) & 0xF;\n+\t\tpba_num[6] = '-';\n+\t\tpba_num[7] = 0;\n+\t\tpba_num[8] = (pba_ptr >> 4) & 0xF;\n+\t\tpba_num[9] = pba_ptr & 0xF;\n+\n+\t\t/* put a null character on the end of our string */\n+\t\tpba_num[10] = '\\0';\n+\n+\t\t/* switch all the data but the '-' to hex char */\n+\t\tfor (offset = 0; offset < 10; offset++) {\n+\t\t\tif (pba_num[offset] < 0xA)\n+\t\t\t\tpba_num[offset] += '0';\n+\t\t\telse if (pba_num[offset] < 0x10)\n+\t\t\t\tpba_num[offset] += 'A' - 0xA;\n+\t\t}\n+\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (length == 0xFFFF || length == 0) {\n+\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n+\t\treturn -IGC_ERR_NVM_PBA_SECTION;\n+\t}\n+\t/* check if pba_num buffer is big enough */\n+\tif (pba_num_size < (((u32)length * 2) - 1)) {\n+\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n+\t\treturn -IGC_ERR_NO_SPACE;\n+\t}\n+\n+\t/* trim pba length from start of string */\n+\tpba_ptr++;\n+\tlength--;\n+\n+\tfor (offset = 0; offset < length; offset++) {\n+\t\tret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t\tpba_num[offset * 2] = (u8)(nvm_data >> 8);\n+\t\tpba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);\n+\t}\n+\tpba_num[offset * 2] = '\\0';\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_pba_length_generic - Read device part number length\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num_size: size of part number buffer\n+ *\n+ *  Reads the product board assembly (PBA) number length from the EEPROM and\n+ *  stores the value in pba_num_size.\n+ **/\n+s32 igc_read_pba_length_generic(struct igc_hw *hw, u32 *pba_num_size)\n+{\n+\ts32 ret_val;\n+\tu16 nvm_data;\n+\tu16 pba_ptr;\n+\tu16 length;\n+\n+\tDEBUGFUNC(\"igc_read_pba_length_generic\");\n+\n+\tif (pba_num_size == NULL) {\n+\t\tDEBUGOUT(\"PBA buffer size was null\\n\");\n+\t\treturn -IGC_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t /* if data is not ptr guard the PBA must be in legacy format */\n+\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n+\t\t*pba_num_size = IGC_PBANUM_LENGTH;\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (length == 0xFFFF || length == 0) {\n+\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n+\t\treturn -IGC_ERR_NVM_PBA_SECTION;\n+\t}\n+\n+\t/* Convert from length in u16 values to u8 chars, add 1 for NULL,\n+\t * and subtract 2 because length field is included in length.\n+\t */\n+\t*pba_num_size = ((u32)length * 2) - 1;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_pba_num_generic - Read device part number\n+ *  @hw: pointer to the HW structure\n+ *  @pba_num: pointer to device part number\n+ *\n+ *  Reads the product board assembly (PBA) number from the EEPROM and stores\n+ *  the value in pba_num.\n+ **/\n+s32 igc_read_pba_num_generic(struct igc_hw *hw, u32 *pba_num)\n+{\n+\ts32 ret_val;\n+\tu16 nvm_data;\n+\n+\tDEBUGFUNC(\"igc_read_pba_num_generic\");\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t} else if (nvm_data == NVM_PBA_PTR_GUARD) {\n+\t\tDEBUGOUT(\"NVM Not Supported\\n\");\n+\t\treturn -IGC_NOT_IMPLEMENTED;\n+\t}\n+\t*pba_num = (u32)(nvm_data << 16);\n+\n+\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\treturn ret_val;\n+\t}\n+\t*pba_num |= nvm_data;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+\n+/**\n+ *  igc_read_pba_raw\n+ *  @hw: pointer to the HW structure\n+ *  @eeprom_buf: optional pointer to EEPROM image\n+ *  @eeprom_buf_size: size of EEPROM image in words\n+ *  @max_pba_block_size: PBA block size limit\n+ *  @pba: pointer to output PBA structure\n+ *\n+ *  Reads PBA from EEPROM image when eeprom_buf is not NULL.\n+ *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.\n+ *\n+ **/\n+s32 igc_read_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t       u32 eeprom_buf_size, u16 max_pba_block_size,\n+\t\t       struct igc_pba *pba)\n+{\n+\ts32 ret_val;\n+\tu16 pba_block_size;\n+\n+\tif (pba == NULL)\n+\t\treturn -IGC_ERR_PARAM;\n+\n+\tif (eeprom_buf == NULL) {\n+\t\tret_val = igc_read_nvm(hw, NVM_PBA_OFFSET_0, 2,\n+\t\t\t\t\t &pba->word[0]);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t} else {\n+\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n+\t\t\tpba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];\n+\t\t\tpba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];\n+\t\t} else {\n+\t\t\treturn -IGC_ERR_PARAM;\n+\t\t}\n+\t}\n+\n+\tif (pba->word[0] == NVM_PBA_PTR_GUARD) {\n+\t\tif (pba->pba_block == NULL)\n+\t\t\treturn -IGC_ERR_PARAM;\n+\n+\t\tret_val = igc_get_pba_block_size(hw, eeprom_buf,\n+\t\t\t\t\t\t   eeprom_buf_size,\n+\t\t\t\t\t\t   &pba_block_size);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (pba_block_size > max_pba_block_size)\n+\t\t\treturn -IGC_ERR_PARAM;\n+\n+\t\tif (eeprom_buf == NULL) {\n+\t\t\tret_val = igc_read_nvm(hw, pba->word[1],\n+\t\t\t\t\t\t pba_block_size,\n+\t\t\t\t\t\t pba->pba_block);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t} else {\n+\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n+\t\t\t\t\t      pba_block_size)) {\n+\t\t\t\tmemcpy(pba->pba_block,\n+\t\t\t\t       &eeprom_buf[pba->word[1]],\n+\t\t\t\t       pba_block_size * sizeof(u16));\n+\t\t\t} else {\n+\t\t\t\treturn -IGC_ERR_PARAM;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_pba_raw\n+ *  @hw: pointer to the HW structure\n+ *  @eeprom_buf: optional pointer to EEPROM image\n+ *  @eeprom_buf_size: size of EEPROM image in words\n+ *  @pba: pointer to PBA structure\n+ *\n+ *  Writes PBA to EEPROM image when eeprom_buf is not NULL.\n+ *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.\n+ *\n+ **/\n+s32 igc_write_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t\tu32 eeprom_buf_size, struct igc_pba *pba)\n+{\n+\ts32 ret_val;\n+\n+\tif (pba == NULL)\n+\t\treturn -IGC_ERR_PARAM;\n+\n+\tif (eeprom_buf == NULL) {\n+\t\tret_val = igc_write_nvm(hw, NVM_PBA_OFFSET_0, 2,\n+\t\t\t\t\t  &pba->word[0]);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t} else {\n+\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n+\t\t\teeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];\n+\t\t\teeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];\n+\t\t} else {\n+\t\t\treturn -IGC_ERR_PARAM;\n+\t\t}\n+\t}\n+\n+\tif (pba->word[0] == NVM_PBA_PTR_GUARD) {\n+\t\tif (pba->pba_block == NULL)\n+\t\t\treturn -IGC_ERR_PARAM;\n+\n+\t\tif (eeprom_buf == NULL) {\n+\t\t\tret_val = igc_write_nvm(hw, pba->word[1],\n+\t\t\t\t\t\t  pba->pba_block[0],\n+\t\t\t\t\t\t  pba->pba_block);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t} else {\n+\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n+\t\t\t\t\t      pba->pba_block[0])) {\n+\t\t\t\tmemcpy(&eeprom_buf[pba->word[1]],\n+\t\t\t\t       pba->pba_block,\n+\t\t\t\t       pba->pba_block[0] * sizeof(u16));\n+\t\t\t} else {\n+\t\t\t\treturn -IGC_ERR_PARAM;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_pba_block_size\n+ *  @hw: pointer to the HW structure\n+ *  @eeprom_buf: optional pointer to EEPROM image\n+ *  @eeprom_buf_size: size of EEPROM image in words\n+ *  @pba_data_size: pointer to output variable\n+ *\n+ *  Returns the size of the PBA block in words. Function operates on EEPROM\n+ *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical\n+ *  EEPROM device.\n+ *\n+ **/\n+s32 igc_get_pba_block_size(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t\t     u32 eeprom_buf_size, u16 *pba_block_size)\n+{\n+\ts32 ret_val;\n+\tu16 pba_word[2];\n+\tu16 length;\n+\n+\tDEBUGFUNC(\"igc_get_pba_block_size\");\n+\n+\tif (eeprom_buf == NULL) {\n+\t\tret_val = igc_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t} else {\n+\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n+\t\t\tpba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];\n+\t\t\tpba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];\n+\t\t} else {\n+\t\t\treturn -IGC_ERR_PARAM;\n+\t\t}\n+\t}\n+\n+\tif (pba_word[0] == NVM_PBA_PTR_GUARD) {\n+\t\tif (eeprom_buf == NULL) {\n+\t\t\tret_val = igc_read_nvm(hw, pba_word[1] + 0, 1,\n+\t\t\t\t\t\t &length);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t} else {\n+\t\t\tif (eeprom_buf_size > pba_word[1])\n+\t\t\t\tlength = eeprom_buf[pba_word[1] + 0];\n+\t\t\telse\n+\t\t\t\treturn -IGC_ERR_PARAM;\n+\t\t}\n+\n+\t\tif (length == 0xFFFF || length == 0)\n+\t\t\treturn -IGC_ERR_NVM_PBA_SECTION;\n+\t} else {\n+\t\t/* PBA number in legacy format, there is no PBA Block. */\n+\t\tlength = 0;\n+\t}\n+\n+\tif (pba_block_size != NULL)\n+\t\t*pba_block_size = length;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_mac_addr_generic - Read device MAC address\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the device MAC address from the EEPROM and stores the value.\n+ *  Since devices with two ports use the same EEPROM, we increment the\n+ *  last bit in the MAC address for the second port.\n+ **/\n+s32 igc_read_mac_addr_generic(struct igc_hw *hw)\n+{\n+\tu32 rar_high;\n+\tu32 rar_low;\n+\tu16 i;\n+\n+\trar_high = IGC_READ_REG(hw, IGC_RAH(0));\n+\trar_low = IGC_READ_REG(hw, IGC_RAL(0));\n+\n+\tfor (i = 0; i < IGC_RAL_MAC_ADDR_LEN; i++)\n+\t\thw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));\n+\n+\tfor (i = 0; i < IGC_RAH_MAC_ADDR_LEN; i++)\n+\t\thw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));\n+\n+\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n+\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_validate_nvm_checksum_generic - Validate EEPROM checksum\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.\n+ **/\n+s32 igc_validate_nvm_checksum_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 checksum = 0;\n+\tu16 i, nvm_data;\n+\n+\tDEBUGFUNC(\"igc_validate_nvm_checksum_generic\");\n+\n+\tfor (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {\n+\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t\tchecksum += nvm_data;\n+\t}\n+\n+\tif (checksum != (u16)NVM_SUM) {\n+\t\tDEBUGOUT(\"NVM Checksum Invalid\\n\");\n+\t\treturn -IGC_ERR_NVM;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_update_nvm_checksum_generic - Update EEPROM checksum\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM\n+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the\n+ *  value to the EEPROM.\n+ **/\n+s32 igc_update_nvm_checksum_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 checksum = 0;\n+\tu16 i, nvm_data;\n+\n+\tDEBUGFUNC(\"igc_update_nvm_checksum\");\n+\n+\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n+\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t\tchecksum += nvm_data;\n+\t}\n+\tchecksum = (u16)NVM_SUM - checksum;\n+\tret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);\n+\tif (ret_val)\n+\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_reload_nvm_generic - Reloads EEPROM\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n+ *  extended control register.\n+ **/\n+static void igc_reload_nvm_generic(struct igc_hw *hw)\n+{\n+\tu32 ctrl_ext;\n+\n+\tDEBUGFUNC(\"igc_reload_nvm_generic\");\n+\n+\tusec_delay(10);\n+\tctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);\n+\tctrl_ext |= IGC_CTRL_EXT_EE_RST;\n+\tIGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);\n+\tIGC_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ *  igc_get_fw_version - Get firmware version information\n+ *  @hw: pointer to the HW structure\n+ *  @fw_vers: pointer to output version structure\n+ *\n+ *  unsupported/not present features return 0 in version structure\n+ **/\n+void igc_get_fw_version(struct igc_hw *hw, struct igc_fw_version *fw_vers)\n+{\n+\tu16 eeprom_verh, eeprom_verl, etrack_test, fw_version;\n+\tu8 q, hval, rem, result;\n+\tu16 comb_verh, comb_verl, comb_offset;\n+\n+\tmemset(fw_vers, 0, sizeof(struct igc_fw_version));\n+\n+\t/*\n+\t * basic eeprom version numbers, bits used vary by part and by tool\n+\t * used to create the nvm images. Check which data format we have.\n+\t */\n+\tswitch (hw->mac.type) {\n+\tcase igc_i225:\n+\t\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n+\t\t/* find combo image version */\n+\t\thw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);\n+\t\tif (comb_offset && comb_offset != NVM_VER_INVALID) {\n+\t\t\thw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset + 1,\n+\t\t\t\t\t1, &comb_verh);\n+\t\t\thw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset,\n+\t\t\t\t\t1, &comb_verl);\n+\n+\t\t\t/* get Option Rom version if it exists and is valid */\n+\t\t\tif (comb_verh && comb_verl &&\n+\t\t\t\t\tcomb_verh != NVM_VER_INVALID &&\n+\t\t\t\t\tcomb_verl != NVM_VER_INVALID) {\n+\t\t\t\tfw_vers->or_valid = true;\n+\t\t\t\tfw_vers->or_major = comb_verl >>\n+\t\t\t\t\t\tNVM_COMB_VER_SHFT;\n+\t\t\t\tfw_vers->or_build = (comb_verl <<\n+\t\t\t\t\t\tNVM_COMB_VER_SHFT) |\n+\t\t\t\t\t\t(comb_verh >>\n+\t\t\t\t\t\tNVM_COMB_VER_SHFT);\n+\t\t\t\tfw_vers->or_patch = comb_verh &\n+\t\t\t\t\t\tNVM_COMB_VER_MASK;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n+\t\treturn;\n+\t}\n+\thw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);\n+\tfw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)\n+\t\t\t      >> NVM_MAJOR_SHIFT;\n+\n+\t/* check for old style version format in newer images*/\n+\tif ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {\n+\t\teeprom_verl = (fw_version & NVM_COMB_VER_MASK);\n+\t} else {\n+\t\teeprom_verl = (fw_version & NVM_MINOR_MASK)\n+\t\t\t\t>> NVM_MINOR_SHIFT;\n+\t}\n+\t/* Convert minor value to hex before assigning to output struct\n+\t * Val to be converted will not be higher than 99, per tool output\n+\t */\n+\tq = eeprom_verl / NVM_HEX_CONV;\n+\thval = q * NVM_HEX_TENS;\n+\trem = eeprom_verl % NVM_HEX_CONV;\n+\tresult = hval + rem;\n+\tfw_vers->eep_minor = result;\n+\n+\tif ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {\n+\t\thw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);\n+\t\thw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);\n+\t\tfw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)\n+\t\t\t| eeprom_verl;\n+\t} else if ((etrack_test & NVM_ETRACK_VALID) == 0) {\n+\t\thw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);\n+\t\thw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);\n+\t\tfw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |\n+\t\t\t\t     eeprom_verl;\n+\t}\n+}\ndiff --git a/drivers/net/igc/base/e1000_nvm.h b/drivers/net/igc/base/e1000_nvm.h\nnew file mode 100644\nindex 0000000..5e66547\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_nvm.h\n@@ -0,0 +1,69 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_NVM_H_\n+#define _IGC_NVM_H_\n+\n+struct igc_pba {\n+\tu16 word[2];\n+\tu16 *pba_block;\n+};\n+\n+struct igc_fw_version {\n+\tu32 etrack_id;\n+\tu16 eep_major;\n+\tu16 eep_minor;\n+\tu16 eep_build;\n+\n+\tu8 invm_major;\n+\tu8 invm_minor;\n+\tu8 invm_img_type;\n+\n+\tbool or_valid;\n+\tu16 or_major;\n+\tu16 or_build;\n+\tu16 or_patch;\n+};\n+\n+\n+void igc_init_nvm_ops_generic(struct igc_hw *hw);\n+s32  igc_null_read_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);\n+void igc_null_nvm_generic(struct igc_hw *hw);\n+s32  igc_null_led_default(struct igc_hw *hw, u16 *data);\n+s32  igc_null_write_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);\n+s32  igc_acquire_nvm_generic(struct igc_hw *hw);\n+\n+s32  igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg);\n+s32  igc_read_mac_addr_generic(struct igc_hw *hw);\n+s32  igc_read_pba_num_generic(struct igc_hw *hw, u32 *pba_num);\n+s32  igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,\n+\t\t\t\t   u32 pba_num_size);\n+s32  igc_read_pba_length_generic(struct igc_hw *hw, u32 *pba_num_size);\n+s32 igc_read_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t       u32 eeprom_buf_size, u16 max_pba_block_size,\n+\t\t       struct igc_pba *pba);\n+s32 igc_write_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t\tu32 eeprom_buf_size, struct igc_pba *pba);\n+s32 igc_get_pba_block_size(struct igc_hw *hw, u16 *eeprom_buf,\n+\t\t\t     u32 eeprom_buf_size, u16 *pba_block_size);\n+s32  igc_read_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data);\n+s32  igc_read_nvm_microwire(struct igc_hw *hw, u16 offset,\n+\t\t\t      u16 words, u16 *data);\n+s32  igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t u16 *data);\n+s32  igc_valid_led_default_generic(struct igc_hw *hw, u16 *data);\n+s32  igc_validate_nvm_checksum_generic(struct igc_hw *hw);\n+s32  igc_write_nvm_microwire(struct igc_hw *hw, u16 offset,\n+\t\t\t       u16 words, u16 *data);\n+s32  igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words,\n+\t\t\t u16 *data);\n+s32  igc_update_nvm_checksum_generic(struct igc_hw *hw);\n+void igc_stop_nvm(struct igc_hw *hw);\n+void igc_release_nvm_generic(struct igc_hw *hw);\n+void igc_get_fw_version(struct igc_hw *hw,\n+\t\t\t  struct igc_fw_version *fw_vers);\n+\n+#define IGC_STM_OPCODE\t0xDB00\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_osdep.c b/drivers/net/igc/base/e1000_osdep.c\nnew file mode 100644\nindex 0000000..56703cb\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_osdep.c\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2020\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+/*\n+ * NOTE: the following routines using the igc\n+ * naming style are provided to the shared\n+ * code but are OS specific\n+ */\n+\n+void\n+igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\t(void)hw;\n+\t(void)reg;\n+\t(void)value;\n+}\n+\n+void\n+igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\t(void)hw;\n+\t(void)reg;\n+\t*value = 0;\n+}\n+\n+void\n+igc_pci_set_mwi(struct igc_hw *hw)\n+{\n+\t(void)hw;\n+}\n+\n+void\n+igc_pci_clear_mwi(struct igc_hw *hw)\n+{\n+\t(void)hw;\n+}\n+\n+/*\n+ * Read the PCI Express capabilities\n+ */\n+int32_t\n+igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\t(void)hw;\n+\t(void)reg;\n+\t(void)value;\n+\treturn IGC_NOT_IMPLEMENTED;\n+}\n+\n+/*\n+ * Write the PCI Express capabilities\n+ */\n+int32_t\n+igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)\n+{\n+\t(void)hw;\n+\t(void)reg;\n+\t(void)value;\n+\n+\treturn IGC_NOT_IMPLEMENTED;\n+}\ndiff --git a/drivers/net/igc/base/e1000_osdep.h b/drivers/net/igc/base/e1000_osdep.h\nnew file mode 100644\nindex 0000000..f4d2135\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_osdep.h\n@@ -0,0 +1,163 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2020\n+ */\n+\n+\n+#ifndef _IGC_OSDEP_H_\n+#define _IGC_OSDEP_H_\n+\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <string.h>\n+#include <stdbool.h>\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_log.h>\n+#include <rte_debug.h>\n+#include <rte_byteorder.h>\n+#include <rte_io.h>\n+\n+#include \"../igc_logs.h\"\n+\n+#define DELAY(x) rte_delay_us(x)\n+#define usec_delay(x) DELAY(x)\n+#define usec_delay_irq(x) DELAY(x)\n+#define msec_delay(x) DELAY(1000 * (x))\n+#define msec_delay_irq(x) DELAY(1000 * (x))\n+\n+#define DEBUGFUNC(F)            DEBUGOUT(F \"\\n\")\n+#define DEBUGOUT(S, args...)    PMD_DRV_LOG_RAW(DEBUG, S, ##args)\n+#define DEBUGOUT1(S, args...)   DEBUGOUT(S, ##args)\n+#define DEBUGOUT2(S, args...)   DEBUGOUT(S, ##args)\n+#define DEBUGOUT3(S, args...)   DEBUGOUT(S, ##args)\n+#define DEBUGOUT6(S, args...)   DEBUGOUT(S, ##args)\n+#define DEBUGOUT7(S, args...)   DEBUGOUT(S, ##args)\n+\n+#define UNREFERENCED_PARAMETER(_p)\t(void)(_p)\n+#define UNREFERENCED_1PARAMETER(_p)\t(void)(_p)\n+#define UNREFERENCED_2PARAMETER(_p, _q)\t\\\n+\tdo {\t\t\t\t\\\n+\t\t(void)(_p);\t\t\\\n+\t\t(void)(_q);\t\t\\\n+\t} while (0)\n+#define UNREFERENCED_3PARAMETER(_p, _q, _r)\t\\\n+\tdo {\t\t\t\t\t\\\n+\t\t(void)(_p);\t\t\t\\\n+\t\t(void)(_q);\t\t\t\\\n+\t\t(void)(_r);\t\t\t\\\n+\t} while (0)\n+#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)\t\\\n+\tdo {\t\t\t\t\t\\\n+\t\t(void)(_p);\t\t\t\\\n+\t\t(void)(_q);\t\t\t\\\n+\t\t(void)(_r);\t\t\t\\\n+\t\t(void)(_s);\t\t\t\\\n+\t} while (0)\n+\n+#define\tCMD_MEM_WRT_INVALIDATE\t0x0010  /* BIT_4 */\n+\n+/* Mutex used in the shared code */\n+#define IGC_MUTEX                     uintptr_t\n+#define IGC_MUTEX_INIT(mutex)         (*(mutex) = 0)\n+#define IGC_MUTEX_LOCK(mutex)         (*(mutex) = 1)\n+#define IGC_MUTEX_UNLOCK(mutex)       (*(mutex) = 0)\n+\n+typedef uint64_t\tu64;\n+typedef uint32_t\tu32;\n+typedef uint16_t\tu16;\n+typedef uint8_t\t\tu8;\n+typedef int64_t\t\ts64;\n+typedef int32_t\t\ts32;\n+typedef int16_t\t\ts16;\n+typedef int8_t\t\ts8;\n+\n+#define __le16\t\tu16\n+#define __le32\t\tu32\n+#define __le64\t\tu64\n+\n+#define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS)\n+\n+#define IGC_PCI_REG(reg)\trte_read32(reg)\n+\n+#define IGC_PCI_REG16(reg)\trte_read16(reg)\n+\n+#define IGC_PCI_REG_WRITE(reg, value)\t\t\t\\\n+\trte_write32((rte_cpu_to_le_32(value)), reg)\n+\n+#define IGC_PCI_REG_WRITE_RELAXED(reg, value)\t\t\\\n+\trte_write32_relaxed((rte_cpu_to_le_32(value)), reg)\n+\n+#define IGC_PCI_REG_WRITE16(reg, value)\t\t\\\n+\trte_write16((rte_cpu_to_le_16(value)), reg)\n+\n+#define IGC_PCI_REG_ADDR(hw, reg) \\\n+\t((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))\n+\n+#define IGC_PCI_REG_ARRAY_ADDR(hw, reg, index) \\\n+\tIGC_PCI_REG_ADDR((hw), (reg) + ((index) << 2))\n+\n+#define IGC_PCI_REG_FLASH_ADDR(hw, reg) \\\n+\t((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))\n+\n+static inline uint32_t igc_read_addr(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_32(IGC_PCI_REG(addr));\n+}\n+\n+static inline uint16_t igc_read_addr16(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_16(IGC_PCI_REG16(addr));\n+}\n+\n+/* Register READ/WRITE macros */\n+\n+#define IGC_READ_REG(hw, reg) \\\n+\tigc_read_addr(IGC_PCI_REG_ADDR((hw), (reg)))\n+\n+#define IGC_READ_REG_LE_VALUE(hw, reg) \\\n+\trte_read32(IGC_PCI_REG_ADDR((hw), (reg)))\n+\n+#define IGC_WRITE_REG(hw, reg, value) \\\n+\tIGC_PCI_REG_WRITE(IGC_PCI_REG_ADDR((hw), (reg)), (value))\n+\n+#define IGC_WRITE_REG_LE_VALUE(hw, reg, value) \\\n+\trte_write32(value, IGC_PCI_REG_ADDR((hw), (reg)))\n+\n+#define IGC_READ_REG_ARRAY(hw, reg, index) \\\n+\tIGC_PCI_REG(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))\n+\n+#define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \\\n+\tIGC_PCI_REG_WRITE(IGC_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), \\\n+\t\t\t(value))\n+\n+#define IGC_READ_REG_ARRAY_DWORD IGC_READ_REG_ARRAY\n+#define IGC_WRITE_REG_ARRAY_DWORD IGC_WRITE_REG_ARRAY\n+\n+/*\n+ * To be able to do IO write, we need to map IO BAR\n+ * (bar 2/4 depending on device).\n+ * Right now mapping multiple BARs is not supported by DPDK.\n+ * Fortunatelly we need it only for legacy hw support.\n+ */\n+\n+#define IGC_WRITE_REG_IO(hw, reg, value) \\\n+\tIGC_WRITE_REG(hw, reg, value)\n+\n+/*\n+ * Tested on I217/I218 chipset.\n+ */\n+\n+#define IGC_READ_FLASH_REG(hw, reg) \\\n+\tigc_read_addr(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))\n+\n+#define IGC_READ_FLASH_REG16(hw, reg)  \\\n+\tigc_read_addr16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)))\n+\n+#define IGC_WRITE_FLASH_REG(hw, reg, value)  \\\n+\tIGC_PCI_REG_WRITE(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))\n+\n+#define IGC_WRITE_FLASH_REG16(hw, reg, value) \\\n+\tIGC_PCI_REG_WRITE16(IGC_PCI_REG_FLASH_ADDR((hw), (reg)), (value))\n+\n+#endif /* _IGC_OSDEP_H_ */\ndiff --git a/drivers/net/igc/base/e1000_phy.c b/drivers/net/igc/base/e1000_phy.c\nnew file mode 100644\nindex 0000000..3130e25\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_phy.c\n@@ -0,0 +1,4422 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#include \"e1000_api.h\"\n+\n+static s32 igc_wait_autoneg(struct igc_hw *hw);\n+static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,\n+\t\t\t\t\t  u16 *data, bool read, bool page_set);\n+static u32 igc_get_phy_addr_for_hv_page(u32 page);\n+static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,\n+\t\t\t\t\t  u16 *data, bool read);\n+\n+/* Cable length tables */\n+static const u16 igc_m88_cable_length_table[] = {\n+\t0, 50, 80, 110, 140, 140, IGC_CABLE_LENGTH_UNDEFINED };\n+#define M88IGC_CABLE_LENGTH_TABLE_SIZE \\\n+\t\t(sizeof(igc_m88_cable_length_table) / \\\n+\t\t sizeof(igc_m88_cable_length_table[0]))\n+\n+static const u16 igc_igp_2_cable_length_table[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,\n+\t6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,\n+\t26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,\n+\t44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,\n+\t66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,\n+\t87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,\n+\t100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,\n+\t124};\n+#define IGP02IGC_CABLE_LENGTH_TABLE_SIZE \\\n+\t\t(sizeof(igc_igp_2_cable_length_table) / \\\n+\t\t sizeof(igc_igp_2_cable_length_table[0]))\n+\n+/**\n+ *  igc_init_phy_ops_generic - Initialize PHY function pointers\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Setups up the function pointers to no-op functions\n+ **/\n+void igc_init_phy_ops_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\tDEBUGFUNC(\"igc_init_phy_ops_generic\");\n+\n+\t/* Initialize function pointers */\n+\tphy->ops.init_params = igc_null_ops_generic;\n+\tphy->ops.acquire = igc_null_ops_generic;\n+\tphy->ops.check_polarity = igc_null_ops_generic;\n+\tphy->ops.check_reset_block = igc_null_ops_generic;\n+\tphy->ops.commit = igc_null_ops_generic;\n+\tphy->ops.force_speed_duplex = igc_null_ops_generic;\n+\tphy->ops.get_cfg_done = igc_null_ops_generic;\n+\tphy->ops.get_cable_length = igc_null_ops_generic;\n+\tphy->ops.get_info = igc_null_ops_generic;\n+\tphy->ops.set_page = igc_null_set_page;\n+\tphy->ops.read_reg = igc_null_read_reg;\n+\tphy->ops.read_reg_locked = igc_null_read_reg;\n+\tphy->ops.read_reg_page = igc_null_read_reg;\n+\tphy->ops.release = igc_null_phy_generic;\n+\tphy->ops.reset = igc_null_ops_generic;\n+\tphy->ops.set_d0_lplu_state = igc_null_lplu_state;\n+\tphy->ops.set_d3_lplu_state = igc_null_lplu_state;\n+\tphy->ops.write_reg = igc_null_write_reg;\n+\tphy->ops.write_reg_locked = igc_null_write_reg;\n+\tphy->ops.write_reg_page = igc_null_write_reg;\n+\tphy->ops.power_up = igc_null_phy_generic;\n+\tphy->ops.power_down = igc_null_phy_generic;\n+\tphy->ops.read_i2c_byte = igc_read_i2c_byte_null;\n+\tphy->ops.write_i2c_byte = igc_write_i2c_byte_null;\n+\tphy->ops.cfg_on_link_up = igc_null_ops_generic;\n+}\n+\n+/**\n+ *  igc_null_set_page - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @data: dummy variable\n+ **/\n+s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\tu16 IGC_UNUSEDARG data)\n+{\n+\tDEBUGFUNC(\"igc_null_set_page\");\n+\tUNREFERENCED_2PARAMETER(hw, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_read_reg - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @offset: dummy variable\n+ *  @data: dummy variable\n+ **/\n+s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\tu32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG * data)\n+{\n+\tDEBUGFUNC(\"igc_null_read_reg\");\n+\tUNREFERENCED_3PARAMETER(hw, offset, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_phy_generic - No-op function, return void\n+ *  @hw: pointer to the HW structure\n+ **/\n+void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_null_phy_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+}\n+\n+/**\n+ *  igc_null_lplu_state - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @active: dummy variable\n+ **/\n+s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t  bool IGC_UNUSEDARG active)\n+{\n+\tDEBUGFUNC(\"igc_null_lplu_state\");\n+\tUNREFERENCED_2PARAMETER(hw, active);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_null_write_reg - No-op function, return 0\n+ *  @hw: pointer to the HW structure\n+ *  @offset: dummy variable\n+ *  @data: dummy variable\n+ **/\n+s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)\n+{\n+\tDEBUGFUNC(\"igc_null_write_reg\");\n+\tUNREFERENCED_3PARAMETER(hw, offset, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_i2c_byte_null - No-op function, return 0\n+ *  @hw: pointer to hardware structure\n+ *  @byte_offset: byte offset to write\n+ *  @dev_addr: device address\n+ *  @data: data value read\n+ *\n+ **/\n+s32 igc_read_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t     u8 IGC_UNUSEDARG byte_offset,\n+\t\t\t     u8 IGC_UNUSEDARG dev_addr,\n+\t\t\t     u8 IGC_UNUSEDARG * data)\n+{\n+\tDEBUGFUNC(\"igc_read_i2c_byte_null\");\n+\tUNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_i2c_byte_null - No-op function, return 0\n+ *  @hw: pointer to hardware structure\n+ *  @byte_offset: byte offset to write\n+ *  @dev_addr: device address\n+ *  @data: data value to write\n+ *\n+ **/\n+s32 igc_write_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,\n+\t\t\t      u8 IGC_UNUSEDARG byte_offset,\n+\t\t\t      u8 IGC_UNUSEDARG dev_addr,\n+\t\t\t      u8 IGC_UNUSEDARG data)\n+{\n+\tDEBUGFUNC(\"igc_write_i2c_byte_null\");\n+\tUNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_check_reset_block_generic - Check if PHY reset is blocked\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Read the PHY management control register and check whether a PHY reset\n+ *  is blocked.  If a reset is not blocked return IGC_SUCCESS, otherwise\n+ *  return IGC_BLK_PHY_RESET (12).\n+ **/\n+s32 igc_check_reset_block_generic(struct igc_hw *hw)\n+{\n+\tu32 manc;\n+\n+\tDEBUGFUNC(\"igc_check_reset_block\");\n+\n+\tmanc = IGC_READ_REG(hw, IGC_MANC);\n+\n+\treturn (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?\n+\t       IGC_BLK_PHY_RESET : IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_phy_id - Retrieve the PHY ID and revision\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the PHY registers and stores the PHY ID and possibly the PHY\n+ *  revision in the hardware structure.\n+ **/\n+s32 igc_get_phy_id(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu16 phy_id;\n+\tu16 retry_count = 0;\n+\n+\tDEBUGFUNC(\"igc_get_phy_id\");\n+\n+\tif (!phy->ops.read_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\twhile (retry_count < 2) {\n+\t\tret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy->id = (u32)(phy_id << 16);\n+\t\tusec_delay(20);\n+\t\tret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy->id |= (u32)(phy_id & PHY_REVISION_MASK);\n+\t\tphy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);\n+\n+\t\tif (phy->id != 0 && phy->id != PHY_REVISION_MASK)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tretry_count++;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_reset_dsp_generic - Reset PHY DSP\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reset the digital signal processor.\n+ **/\n+s32 igc_phy_reset_dsp_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_phy_reset_dsp_generic\");\n+\n+\tif (!hw->phy.ops.write_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0xC1);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treturn hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0);\n+}\n+\n+/**\n+ *  igc_read_phy_reg_mdic - Read MDI control register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the MDI control register in the PHY at offset and stores the\n+ *  information read to data.\n+ **/\n+s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\tu32 i, mdic = 0;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_mdic\");\n+\n+\tif (offset > MAX_PHY_REG_ADDRESS) {\n+\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n+\t\treturn -IGC_ERR_PARAM;\n+\t}\n+\n+\t/* Set up Op-code, Phy Address, and register offset in the MDI\n+\t * Control register.  The MAC will take care of interfacing with the\n+\t * PHY to retrieve the desired data.\n+\t */\n+\tmdic = ((offset << IGC_MDIC_REG_SHIFT) |\n+\t\t(phy->addr << IGC_MDIC_PHY_SHIFT) |\n+\t\t(IGC_MDIC_OP_READ));\n+\n+\tIGC_WRITE_REG(hw, IGC_MDIC, mdic);\n+\n+\t/* Poll the ready bit to see if the MDI read completed\n+\t * Increasing the time out as testing showed failures with\n+\t * the lower time out\n+\t */\n+\tfor (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {\n+\t\tusec_delay_irq(50);\n+\t\tmdic = IGC_READ_REG(hw, IGC_MDIC);\n+\t\tif (mdic & IGC_MDIC_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(mdic & IGC_MDIC_READY)) {\n+\t\tDEBUGOUT(\"MDI Read did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (mdic & IGC_MDIC_ERROR) {\n+\t\tDEBUGOUT(\"MDI Error\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {\n+\t\tDEBUGOUT2(\"MDI Read offset error - requested %d, returned %d\\n\",\n+\t\t\t  offset,\n+\t\t\t  (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\t*data = (u16)mdic;\n+\n+\t/* Allow some time after each MDIC transaction to avoid\n+\t * reading duplicate data in the next MDIC transaction.\n+\t */\n+\tif (hw->mac.type == igc_pch2lan)\n+\t\tusec_delay_irq(100);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_mdic - Write MDI control register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write to register at offset\n+ *\n+ *  Writes data to MDI control register in the PHY at offset.\n+ **/\n+s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\tu32 i, mdic = 0;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_mdic\");\n+\n+\tif (offset > MAX_PHY_REG_ADDRESS) {\n+\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n+\t\treturn -IGC_ERR_PARAM;\n+\t}\n+\n+\t/* Set up Op-code, Phy Address, and register offset in the MDI\n+\t * Control register.  The MAC will take care of interfacing with the\n+\t * PHY to retrieve the desired data.\n+\t */\n+\tmdic = (((u32)data) |\n+\t\t(offset << IGC_MDIC_REG_SHIFT) |\n+\t\t(phy->addr << IGC_MDIC_PHY_SHIFT) |\n+\t\t(IGC_MDIC_OP_WRITE));\n+\n+\tIGC_WRITE_REG(hw, IGC_MDIC, mdic);\n+\n+\t/* Poll the ready bit to see if the MDI read completed\n+\t * Increasing the time out as testing showed failures with\n+\t * the lower time out\n+\t */\n+\tfor (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {\n+\t\tusec_delay_irq(50);\n+\t\tmdic = IGC_READ_REG(hw, IGC_MDIC);\n+\t\tif (mdic & IGC_MDIC_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(mdic & IGC_MDIC_READY)) {\n+\t\tDEBUGOUT(\"MDI Write did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (mdic & IGC_MDIC_ERROR) {\n+\t\tDEBUGOUT(\"MDI Error\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {\n+\t\tDEBUGOUT2(\"MDI Write offset error - requested %d, returned %d\\n\",\n+\t\t\t  offset,\n+\t\t\t  (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\t/* Allow some time after each MDIC transaction to avoid\n+\t * reading duplicate data in the next MDIC transaction.\n+\t */\n+\tif (hw->mac.type == igc_pch2lan)\n+\t\tusec_delay_irq(100);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_i2c - Read PHY register using i2c\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the PHY register at offset using the i2c interface and stores the\n+ *  retrieved information in data.\n+ **/\n+s32 igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\tu32 i, i2ccmd = 0;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_i2c\");\n+\n+\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n+\t * register.  The MAC will take care of interfacing with the\n+\t * PHY to retrieve the desired data.\n+\t */\n+\ti2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |\n+\t\t  (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |\n+\t\t  (IGC_I2CCMD_OPCODE_READ));\n+\n+\tIGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);\n+\n+\t/* Poll the ready bit to see if the I2C read completed */\n+\tfor (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {\n+\t\tusec_delay(50);\n+\t\ti2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);\n+\t\tif (i2ccmd & IGC_I2CCMD_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(i2ccmd & IGC_I2CCMD_READY)) {\n+\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (i2ccmd & IGC_I2CCMD_ERROR) {\n+\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\t/* Need to byte-swap the 16-bit value. */\n+\t*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_i2c - Write PHY register using i2c\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Writes the data to PHY register at the offset using the i2c interface.\n+ **/\n+s32 igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\tu32 i, i2ccmd = 0;\n+\tu16 phy_data_swapped;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_i2c\");\n+\n+\t/* Prevent overwriting SFP I2C EEPROM which is at A0 address. */\n+\tif (hw->phy.addr == 0 || hw->phy.addr > 7) {\n+\t\tDEBUGOUT1(\"PHY I2C Address %d is out of range.\\n\",\n+\t\t\thw->phy.addr);\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\t/* Swap the data bytes for the I2C interface */\n+\tphy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);\n+\n+\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n+\t * register.  The MAC will take care of interfacing with the\n+\t * PHY to retrieve the desired data.\n+\t */\n+\ti2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |\n+\t\t  (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |\n+\t\t  IGC_I2CCMD_OPCODE_WRITE |\n+\t\t  phy_data_swapped);\n+\n+\tIGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);\n+\n+\t/* Poll the ready bit to see if the I2C read completed */\n+\tfor (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {\n+\t\tusec_delay(50);\n+\t\ti2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);\n+\t\tif (i2ccmd & IGC_I2CCMD_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(i2ccmd & IGC_I2CCMD_READY)) {\n+\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (i2ccmd & IGC_I2CCMD_ERROR) {\n+\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_sfp_data_byte - Reads SFP module data.\n+ *  @hw: pointer to the HW structure\n+ *  @offset: byte location offset to be read\n+ *  @data: read data buffer pointer\n+ *\n+ *  Reads one byte from SFP module data stored\n+ *  in SFP resided EEPROM memory or SFP diagnostic area.\n+ *  Function should be called with\n+ *  IGC_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access\n+ *  IGC_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters\n+ *  access\n+ **/\n+s32 igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data)\n+{\n+\tu32 i = 0;\n+\tu32 i2ccmd = 0;\n+\tu32 data_local = 0;\n+\n+\tDEBUGFUNC(\"igc_read_sfp_data_byte\");\n+\n+\tif (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {\n+\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n+\t * register. The MAC will take care of interfacing with the\n+\t * EEPROM to retrieve the desired data.\n+\t */\n+\ti2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |\n+\t\t  IGC_I2CCMD_OPCODE_READ);\n+\n+\tIGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);\n+\n+\t/* Poll the ready bit to see if the I2C read completed */\n+\tfor (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {\n+\t\tusec_delay(50);\n+\t\tdata_local = IGC_READ_REG(hw, IGC_I2CCMD);\n+\t\tif (data_local & IGC_I2CCMD_READY)\n+\t\t\tbreak;\n+\t}\n+\tif (!(data_local & IGC_I2CCMD_READY)) {\n+\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (data_local & IGC_I2CCMD_ERROR) {\n+\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\t*data = (u8)data_local & 0xFF;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_sfp_data_byte - Writes SFP module data.\n+ *  @hw: pointer to the HW structure\n+ *  @offset: byte location offset to write to\n+ *  @data: data to write\n+ *\n+ *  Writes one byte to SFP module data stored\n+ *  in SFP resided EEPROM memory or SFP diagnostic area.\n+ *  Function should be called with\n+ *  IGC_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access\n+ *  IGC_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters\n+ *  access\n+ **/\n+s32 igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data)\n+{\n+\tu32 i = 0;\n+\tu32 i2ccmd = 0;\n+\tu32 data_local = 0;\n+\n+\tDEBUGFUNC(\"igc_write_sfp_data_byte\");\n+\n+\tif (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {\n+\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\t/* The programming interface is 16 bits wide\n+\t * so we need to read the whole word first\n+\t * then update appropriate byte lane and write\n+\t * the updated word back.\n+\t */\n+\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n+\t * register. The MAC will take care of interfacing\n+\t * with an EEPROM to write the data given.\n+\t */\n+\ti2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |\n+\t\t  IGC_I2CCMD_OPCODE_READ);\n+\t/* Set a command to read single word */\n+\tIGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);\n+\tfor (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {\n+\t\tusec_delay(50);\n+\t\t/* Poll the ready bit to see if lastly\n+\t\t * launched I2C operation completed\n+\t\t */\n+\t\ti2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);\n+\t\tif (i2ccmd & IGC_I2CCMD_READY) {\n+\t\t\t/* Check if this is READ or WRITE phase */\n+\t\t\tif ((i2ccmd & IGC_I2CCMD_OPCODE_READ) ==\n+\t\t\t    IGC_I2CCMD_OPCODE_READ) {\n+\t\t\t\t/* Write the selected byte\n+\t\t\t\t * lane and update whole word\n+\t\t\t\t */\n+\t\t\t\tdata_local = i2ccmd & 0xFF00;\n+\t\t\t\tdata_local |= (u32)data;\n+\t\t\t\ti2ccmd = ((offset <<\n+\t\t\t\t\tIGC_I2CCMD_REG_ADDR_SHIFT) |\n+\t\t\t\t\tIGC_I2CCMD_OPCODE_WRITE | data_local);\n+\t\t\t\tIGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);\n+\t\t\t} else {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (!(i2ccmd & IGC_I2CCMD_READY)) {\n+\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\tif (i2ccmd & IGC_I2CCMD_ERROR) {\n+\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_m88 - Read m88 PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore, if necessary, then reads the PHY register at offset\n+ *  and storing the retrieved information in data.  Release any acquired\n+ *  semaphores before exiting.\n+ **/\n+s32 igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_m88\");\n+\n+\tif (!hw->phy.ops.acquire)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t  data);\n+\n+\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_m88 - Write m88 PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_m88\");\n+\n+\tif (!hw->phy.ops.acquire)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t   data);\n+\n+\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_set_page_igp - Set page as on IGP-like PHY(s)\n+ *  @hw: pointer to the HW structure\n+ *  @page: page to set (shifted left when necessary)\n+ *\n+ *  Sets PHY page required for PHY register access.  Assumes semaphore is\n+ *  already acquired.  Note, this function sets phy.addr to 1 so the caller\n+ *  must set it appropriately (if necessary) after this function returns.\n+ **/\n+s32 igc_set_page_igp(struct igc_hw *hw, u16 page)\n+{\n+\tDEBUGFUNC(\"igc_set_page_igp\");\n+\n+\tDEBUGOUT1(\"Setting page 0x%x\\n\", page);\n+\n+\thw->phy.addr = 1;\n+\n+\treturn igc_write_phy_reg_mdic(hw, IGP01IGC_PHY_PAGE_SELECT, page);\n+}\n+\n+/**\n+ *  __igc_read_phy_reg_igp - Read igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *  @locked: semaphore has already been acquired or not\n+ *\n+ *  Acquires semaphore, if necessary, then reads the PHY register at offset\n+ *  and stores the retrieved information in data.  Release any acquired\n+ *  semaphores before exiting.\n+ **/\n+static s32 __igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data,\n+\t\t\t\t    bool locked)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"__igc_read_phy_reg_igp\");\n+\n+\tif (!locked) {\n+\t\tif (!hw->phy.ops.acquire)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n+\t\tret_val = igc_write_phy_reg_mdic(hw,\n+\t\t\t\t\t\t   IGP01IGC_PHY_PAGE_SELECT,\n+\t\t\t\t\t\t   (u16)offset);\n+\tif (!ret_val)\n+\t\tret_val = igc_read_phy_reg_mdic(hw,\n+\t\t\t\t\t\t  MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t\t  data);\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_igp - Read igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore then reads the PHY register at offset and stores the\n+ *  retrieved information in data.\n+ *  Release the acquired semaphore before exiting.\n+ **/\n+s32 igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_phy_reg_igp(hw, offset, data, false);\n+}\n+\n+/**\n+ *  igc_read_phy_reg_igp_locked - Read igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the PHY register at offset and stores the retrieved information\n+ *  in data.  Assumes semaphore already acquired.\n+ **/\n+s32 igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_phy_reg_igp(hw, offset, data, true);\n+}\n+\n+/**\n+ *  igc_write_phy_reg_igp - Write igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *  @locked: semaphore has already been acquired or not\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+static s32 __igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data,\n+\t\t\t\t     bool locked)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_igp\");\n+\n+\tif (!locked) {\n+\t\tif (!hw->phy.ops.acquire)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n+\t\tret_val = igc_write_phy_reg_mdic(hw,\n+\t\t\t\t\t\t   IGP01IGC_PHY_PAGE_SELECT,\n+\t\t\t\t\t\t   (u16)offset);\n+\tif (!ret_val)\n+\t\tret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &\n+\t\t\t\t\t\t       offset,\n+\t\t\t\t\t\t   data);\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_igp - Write igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_phy_reg_igp(hw, offset, data, false);\n+}\n+\n+/**\n+ *  igc_write_phy_reg_igp_locked - Write igp PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Writes the data to PHY register at the offset.\n+ *  Assumes semaphore already acquired.\n+ **/\n+s32 igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_phy_reg_igp(hw, offset, data, true);\n+}\n+\n+/**\n+ *  __igc_read_kmrn_reg - Read kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *  @locked: semaphore has already been acquired or not\n+ *\n+ *  Acquires semaphore, if necessary.  Then reads the PHY register at offset\n+ *  using the kumeran interface.  The information retrieved is stored in data.\n+ *  Release any acquired semaphores before exiting.\n+ **/\n+static s32 __igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data,\n+\t\t\t\t bool locked)\n+{\n+\tu32 kmrnctrlsta;\n+\n+\tDEBUGFUNC(\"__igc_read_kmrn_reg\");\n+\n+\tif (!locked) {\n+\t\ts32 ret_val = IGC_SUCCESS;\n+\n+\t\tif (!hw->phy.ops.acquire)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tkmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &\n+\t\t       IGC_KMRNCTRLSTA_OFFSET) | IGC_KMRNCTRLSTA_REN;\n+\tIGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tusec_delay(2);\n+\n+\tkmrnctrlsta = IGC_READ_REG(hw, IGC_KMRNCTRLSTA);\n+\t*data = (u16)kmrnctrlsta;\n+\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_read_kmrn_reg_generic -  Read kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore then reads the PHY register at offset using the\n+ *  kumeran interface.  The information retrieved is stored in data.\n+ *  Release the acquired semaphore before exiting.\n+ **/\n+s32 igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_kmrn_reg(hw, offset, data, false);\n+}\n+\n+/**\n+ *  igc_read_kmrn_reg_locked -  Read kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the PHY register at offset using the kumeran interface.  The\n+ *  information retrieved is stored in data.\n+ *  Assumes semaphore already acquired.\n+ **/\n+s32 igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_kmrn_reg(hw, offset, data, true);\n+}\n+\n+/**\n+ *  __igc_write_kmrn_reg - Write kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *  @locked: semaphore has already been acquired or not\n+ *\n+ *  Acquires semaphore, if necessary.  Then write the data to PHY register\n+ *  at the offset using the kumeran interface.  Release any acquired semaphores\n+ *  before exiting.\n+ **/\n+static s32 __igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data,\n+\t\t\t\t  bool locked)\n+{\n+\tu32 kmrnctrlsta;\n+\n+\tDEBUGFUNC(\"igc_write_kmrn_reg_generic\");\n+\n+\tif (!locked) {\n+\t\ts32 ret_val = IGC_SUCCESS;\n+\n+\t\tif (!hw->phy.ops.acquire)\n+\t\t\treturn IGC_SUCCESS;\n+\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tkmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &\n+\t\t       IGC_KMRNCTRLSTA_OFFSET) | data;\n+\tIGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tusec_delay(2);\n+\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_kmrn_reg_generic -  Write kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore then writes the data to the PHY register at the offset\n+ *  using the kumeran interface.  Release the acquired semaphore before exiting.\n+ **/\n+s32 igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_kmrn_reg(hw, offset, data, false);\n+}\n+\n+/**\n+ *  igc_write_kmrn_reg_locked -  Write kumeran register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Write the data to PHY register at the offset using the kumeran interface.\n+ *  Assumes semaphore already acquired.\n+ **/\n+s32 igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_kmrn_reg(hw, offset, data, true);\n+}\n+\n+/**\n+ *  igc_set_master_slave_mode - Setup PHY for Master/slave mode\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets up Master/slave mode\n+ **/\n+static s32 igc_set_master_slave_mode(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\n+\t/* Resolve Master/Slave mode */\n+\tret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* load defaults for future use */\n+\thw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?\n+\t\t\t\t   ((phy_data & CR_1000T_MS_VALUE) ?\n+\t\t\t\t    igc_ms_force_master :\n+\t\t\t\t    igc_ms_force_slave) : igc_ms_auto;\n+\n+\tswitch (hw->phy.ms_type) {\n+\tcase igc_ms_force_master:\n+\t\tphy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);\n+\t\tbreak;\n+\tcase igc_ms_force_slave:\n+\t\tphy_data |= CR_1000T_MS_ENABLE;\n+\t\tphy_data &= ~(CR_1000T_MS_VALUE);\n+\t\tbreak;\n+\tcase igc_ms_auto:\n+\t\tphy_data &= ~CR_1000T_MS_ENABLE;\n+\t\t/* fall-through */\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);\n+}\n+\n+/**\n+ *  igc_copper_link_setup_82577 - Setup 82577 PHY for copper link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets up Carrier-sense on Transmit and downshift values.\n+ **/\n+s32 igc_copper_link_setup_82577(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\n+\tDEBUGFUNC(\"igc_copper_link_setup_82577\");\n+\n+\tif (hw->phy.type == igc_phy_82580) {\n+\t\tret_val = hw->phy.ops.reset(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n+\tret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy_data |= I82577_CFG_ASSERT_CRS_ON_TX;\n+\n+\t/* Enable downshift */\n+\tphy_data |= I82577_CFG_ENABLE_DOWNSHIFT;\n+\n+\tret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Set MDI/MDIX mode */\n+\tret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\tphy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;\n+\t/* Options:\n+\t *   0 - Auto (default)\n+\t *   1 - MDI mode\n+\t *   2 - MDI-X mode\n+\t */\n+\tswitch (hw->phy.mdix) {\n+\tcase 1:\n+\t\tbreak;\n+\tcase 2:\n+\t\tphy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;\n+\t\tbreak;\n+\tcase 0:\n+\tdefault:\n+\t\tphy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;\n+\t\tbreak;\n+\t}\n+\tret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treturn igc_set_master_slave_mode(hw);\n+}\n+\n+/**\n+ *  igc_copper_link_setup_m88 - Setup m88 PHY's for copper link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock\n+ *  and downshift values are set also.\n+ **/\n+s32 igc_copper_link_setup_m88(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\n+\tDEBUGFUNC(\"igc_copper_link_setup_m88\");\n+\n+\n+\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* For BM PHY this bit is downshift enable */\n+\tif (phy->type != igc_phy_bm)\n+\t\tphy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;\n+\n+\t/* Options:\n+\t *   MDI/MDI-X = 0 (default)\n+\t *   0 - Auto for all speeds\n+\t *   1 - MDI mode\n+\t *   2 - MDI-X mode\n+\t *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n+\t */\n+\tphy_data &= ~M88IGC_PSCR_AUTO_X_MODE;\n+\n+\tswitch (phy->mdix) {\n+\tcase 1:\n+\t\tphy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;\n+\t\tbreak;\n+\tcase 2:\n+\t\tphy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;\n+\t\tbreak;\n+\tcase 3:\n+\t\tphy_data |= M88IGC_PSCR_AUTO_X_1000T;\n+\t\tbreak;\n+\tcase 0:\n+\tdefault:\n+\t\tphy_data |= M88IGC_PSCR_AUTO_X_MODE;\n+\t\tbreak;\n+\t}\n+\n+\t/* Options:\n+\t *   disable_polarity_correction = 0 (default)\n+\t *       Automatic Correction for Reversed Cable Polarity\n+\t *   0 - Disabled\n+\t *   1 - Enabled\n+\t */\n+\tphy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;\n+\tif (phy->disable_polarity_correction)\n+\t\tphy_data |= M88IGC_PSCR_POLARITY_REVERSAL;\n+\n+\t/* Enable downshift on BM (disabled by default) */\n+\tif (phy->type == igc_phy_bm) {\n+\t\t/* For 82574/82583, first disable then enable downshift */\n+\t\tif (phy->id == BMIGC_E_PHY_ID_R2) {\n+\t\t\tphy_data &= ~BMIGC_PSCR_ENABLE_DOWNSHIFT;\n+\t\t\tret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,\n+\t\t\t\t\t\t     phy_data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t\t/* Commit the changes. */\n+\t\t\tret_val = phy->ops.commit(hw);\n+\t\t\tif (ret_val) {\n+\t\t\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n+\t\t\t\treturn ret_val;\n+\t\t\t}\n+\t\t}\n+\n+\t\tphy_data |= BMIGC_PSCR_ENABLE_DOWNSHIFT;\n+\t}\n+\n+\tret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (phy->type == igc_phy_m88 && phy->revision < IGC_REVISION_4 &&\n+\t\t\tphy->id != BMIGC_E_PHY_ID_R2) {\n+\t\t/* Force TX_CLK in the Extended PHY Specific Control Register\n+\t\t * to 25MHz clock.\n+\t\t */\n+\t\tret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy_data |= M88IGC_EPSCR_TX_CLK_25;\n+\n+\t\tif (phy->revision == IGC_REVISION_2 &&\n+\t\t\t\tphy->id == M88E1111_I_PHY_ID) {\n+\t\t\t/* 82573L PHY - set the downshift counter to 5x. */\n+\t\t\tphy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;\n+\t\t\tphy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;\n+\t\t} else {\n+\t\t\t/* Configure Master and Slave downshift values */\n+\t\t\tphy_data &= ~(M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK |\n+\t\t\t\t     M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK);\n+\t\t\tphy_data |= (M88IGC_EPSCR_MASTER_DOWNSHIFT_1X |\n+\t\t\t\t     M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X);\n+\t\t}\n+\t\tret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,\n+\t\t\t\t\t     phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tif (phy->type == igc_phy_bm && phy->id == BMIGC_E_PHY_ID_R2) {\n+\t\t/* Set PHY page 0, register 29 to 0x0003 */\n+\t\tret_val = phy->ops.write_reg(hw, 29, 0x0003);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Set PHY page 0, register 30 to 0x0000 */\n+\t\tret_val = phy->ops.write_reg(hw, 30, 0x0000);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\t/* Commit the changes. */\n+\tret_val = phy->ops.commit(hw);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (phy->type == igc_phy_82578) {\n+\t\tret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* 82578 PHY - set the downshift count to 1x. */\n+\t\tphy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;\n+\t\tphy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;\n+\t\tret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,\n+\t\t\t\t\t     phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.\n+ *  Also enables and sets the downshift parameters.\n+ **/\n+s32 igc_copper_link_setup_m88_gen2(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\n+\tDEBUGFUNC(\"igc_copper_link_setup_m88_gen2\");\n+\n+\n+\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Options:\n+\t *   MDI/MDI-X = 0 (default)\n+\t *   0 - Auto for all speeds\n+\t *   1 - MDI mode\n+\t *   2 - MDI-X mode\n+\t *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n+\t */\n+\tphy_data &= ~M88IGC_PSCR_AUTO_X_MODE;\n+\n+\tswitch (phy->mdix) {\n+\tcase 1:\n+\t\tphy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;\n+\t\tbreak;\n+\tcase 2:\n+\t\tphy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;\n+\t\tbreak;\n+\tcase 3:\n+\t\t/* M88E1112 does not support this mode) */\n+\t\tif (phy->id != M88E1112_E_PHY_ID) {\n+\t\t\tphy_data |= M88IGC_PSCR_AUTO_X_1000T;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Fall through */\n+\tcase 0:\n+\tdefault:\n+\t\tphy_data |= M88IGC_PSCR_AUTO_X_MODE;\n+\t\tbreak;\n+\t}\n+\n+\t/* Options:\n+\t *   disable_polarity_correction = 0 (default)\n+\t *       Automatic Correction for Reversed Cable Polarity\n+\t *   0 - Disabled\n+\t *   1 - Enabled\n+\t */\n+\tphy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;\n+\tif (phy->disable_polarity_correction)\n+\t\tphy_data |= M88IGC_PSCR_POLARITY_REVERSAL;\n+\n+\t/* Enable downshift and setting it to X6 */\n+\tif (phy->id == M88E1543_E_PHY_ID) {\n+\t\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;\n+\t\tret_val =\n+\t\t    phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.commit(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;\n+\tphy_data |= I347AT4_PSCR_DOWNSHIFT_6X;\n+\tphy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;\n+\n+\tret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Commit the changes. */\n+\tret_val = phy->ops.commit(hw);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tret_val = igc_set_master_slave_mode(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_copper_link_setup_igp - Setup igp PHY's for copper link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for\n+ *  igp PHY's.\n+ **/\n+s32 igc_copper_link_setup_igp(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_copper_link_setup_igp\");\n+\n+\n+\tret_val = hw->phy.ops.reset(hw);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid\n+\t * timeout issues when LFS is enabled.\n+\t */\n+\tmsec_delay(100);\n+\n+\t/* The NVM settings will configure LPLU in D3 for\n+\t * non-IGP1 PHYs.\n+\t */\n+\tif (phy->type == igc_phy_igp) {\n+\t\t/* disable lplu d3 during driver init */\n+\t\tret_val = hw->phy.ops.set_d3_lplu_state(hw, false);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error Disabling LPLU D3\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\t/* disable lplu d0 during driver init */\n+\tif (hw->phy.ops.set_d0_lplu_state) {\n+\t\tret_val = hw->phy.ops.set_d0_lplu_state(hw, false);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error Disabling LPLU D0\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\t/* Configure mdi-mdix settings */\n+\tret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tdata &= ~IGP01IGC_PSCR_AUTO_MDIX;\n+\n+\tswitch (phy->mdix) {\n+\tcase 1:\n+\t\tdata &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;\n+\t\tbreak;\n+\tcase 2:\n+\t\tdata |= IGP01IGC_PSCR_FORCE_MDI_MDIX;\n+\t\tbreak;\n+\tcase 0:\n+\tdefault:\n+\t\tdata |= IGP01IGC_PSCR_AUTO_MDIX;\n+\t\tbreak;\n+\t}\n+\tret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* set auto-master slave resolution settings */\n+\tif (hw->mac.autoneg) {\n+\t\t/* when autonegotiation advertisement is only 1000Mbps then we\n+\t\t * should disable SmartSpeed and enable Auto MasterSlave\n+\t\t * resolution as hardware default.\n+\t\t */\n+\t\tif (phy->autoneg_advertised == ADVERTISE_1000_FULL) {\n+\t\t\t/* Disable SmartSpeed */\n+\t\t\tret_val = phy->ops.read_reg(hw,\n+\t\t\t\t\t\t    IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t    &data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\n+\t\t\tdata &= ~IGP01IGC_PSCFR_SMART_SPEED;\n+\t\t\tret_val = phy->ops.write_reg(hw,\n+\t\t\t\t\t\t     IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t     data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\n+\t\t\t/* Set auto Master/Slave resolution process */\n+\t\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\n+\t\t\tdata &= ~CR_1000T_MS_ENABLE;\n+\t\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t}\n+\n+\t\tret_val = igc_set_master_slave_mode(hw);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_setup_autoneg - Configure PHY for auto-negotiation\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the MII auto-neg advertisement register and/or the 1000T control\n+ *  register and if the PHY is already setup for auto-negotiation, then\n+ *  return successful.  Otherwise, setup advertisement and flow control to\n+ *  the appropriate values for the wanted auto-negotiation.\n+ **/\n+s32 igc_phy_setup_autoneg(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 mii_autoneg_adv_reg;\n+\tu16 mii_1000t_ctrl_reg = 0;\n+\tu16 aneg_multigbt_an_ctrl = 0;\n+\n+\tDEBUGFUNC(\"igc_phy_setup_autoneg\");\n+\n+\tphy->autoneg_advertised &= phy->autoneg_mask;\n+\n+\t/* Read the MII Auto-Neg Advertisement Register (Address 4). */\n+\tret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (phy->autoneg_mask & ADVERTISE_1000_FULL) {\n+\t\t/* Read the MII 1000Base-T Control Register (Address 9). */\n+\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,\n+\t\t\t\t\t    &mii_1000t_ctrl_reg);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tif ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&\n+\t    hw->phy.id == I225_I_PHY_ID) {\n+\t/* Read the MULTI GBT AN Control Register - reg 7.32 */\n+\t\tret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<\n+\t\t\t\t\t    MMD_DEVADDR_SHIFT) |\n+\t\t\t\t\t    ANEG_MULTIGBT_AN_CTRL,\n+\t\t\t\t\t    &aneg_multigbt_an_ctrl);\n+\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\t/* Need to parse both autoneg_advertised and fc and set up\n+\t * the appropriate PHY registers.  First we will parse for\n+\t * autoneg_advertised software override.  Since we can advertise\n+\t * a plethora of combinations, we need to check each bit\n+\t * individually.\n+\t */\n+\n+\t/* First we clear all the 10/100 mb speed bits in the Auto-Neg\n+\t * Advertisement Register (Address 4) and the 1000 mb speed bits in\n+\t * the  1000Base-T Control Register (Address 9).\n+\t */\n+\tmii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |\n+\t\t\t\t NWAY_AR_100TX_HD_CAPS |\n+\t\t\t\t NWAY_AR_10T_FD_CAPS   |\n+\t\t\t\t NWAY_AR_10T_HD_CAPS);\n+\tmii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);\n+\n+\tDEBUGOUT1(\"autoneg_advertised %x\\n\", phy->autoneg_advertised);\n+\n+\t/* Do we want to advertise 10 Mb Half Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_10_HALF) {\n+\t\tDEBUGOUT(\"Advertise 10mb Half duplex\\n\");\n+\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;\n+\t}\n+\n+\t/* Do we want to advertise 10 Mb Full Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_10_FULL) {\n+\t\tDEBUGOUT(\"Advertise 10mb Full duplex\\n\");\n+\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;\n+\t}\n+\n+\t/* Do we want to advertise 100 Mb Half Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_100_HALF) {\n+\t\tDEBUGOUT(\"Advertise 100mb Half duplex\\n\");\n+\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;\n+\t}\n+\n+\t/* Do we want to advertise 100 Mb Full Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_100_FULL) {\n+\t\tDEBUGOUT(\"Advertise 100mb Full duplex\\n\");\n+\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;\n+\t}\n+\n+\t/* We do not allow the Phy to advertise 1000 Mb Half Duplex */\n+\tif (phy->autoneg_advertised & ADVERTISE_1000_HALF)\n+\t\tDEBUGOUT(\"Advertise 1000mb Half duplex request denied!\\n\");\n+\n+\t/* Do we want to advertise 1000 Mb Full Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_1000_FULL) {\n+\t\tDEBUGOUT(\"Advertise 1000mb Full duplex\\n\");\n+\t\tmii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;\n+\t}\n+\n+\t/* We do not allow the Phy to advertise 2500 Mb Half Duplex */\n+\tif (phy->autoneg_advertised & ADVERTISE_2500_HALF)\n+\t\tDEBUGOUT(\"Advertise 2500mb Half duplex request denied!\\n\");\n+\n+\t/* Do we want to advertise 2500 Mb Full Duplex? */\n+\tif (phy->autoneg_advertised & ADVERTISE_2500_FULL) {\n+\t\tDEBUGOUT(\"Advertise 2500mb Full duplex\\n\");\n+\t\taneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;\n+\t} else {\n+\t\taneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;\n+\t}\n+\n+\t/* Check for a software override of the flow control settings, and\n+\t * setup the PHY advertisement registers accordingly.  If\n+\t * auto-negotiation is enabled, then software will have to set the\n+\t * \"PAUSE\" bits to the correct value in the Auto-Negotiation\n+\t * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-\n+\t * negotiation.\n+\t *\n+\t * The possible values of the \"fc\" parameter are:\n+\t *      0:  Flow control is completely disabled\n+\t *      1:  Rx flow control is enabled (we can receive pause frames\n+\t *          but not send pause frames).\n+\t *      2:  Tx flow control is enabled (we can send pause frames\n+\t *          but we do not support receiving pause frames).\n+\t *      3:  Both Rx and Tx flow control (symmetric) are enabled.\n+\t *  other:  No software override.  The flow control configuration\n+\t *          in the EEPROM is used.\n+\t */\n+\tswitch (hw->fc.current_mode) {\n+\tcase igc_fc_none:\n+\t\t/* Flow control (Rx & Tx) is completely disabled by a\n+\t\t * software over-ride.\n+\t\t */\n+\t\tmii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n+\t\tbreak;\n+\tcase igc_fc_rx_pause:\n+\t\t/* Rx Flow control is enabled, and Tx Flow control is\n+\t\t * disabled, by a software over-ride.\n+\t\t *\n+\t\t * Since there really isn't a way to advertise that we are\n+\t\t * capable of Rx Pause ONLY, we will advertise that we\n+\t\t * support both symmetric and asymmetric Rx PAUSE.  Later\n+\t\t * (in igc_config_fc_after_link_up) we will disable the\n+\t\t * hw's ability to send PAUSE frames.\n+\t\t */\n+\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n+\t\tbreak;\n+\tcase igc_fc_tx_pause:\n+\t\t/* Tx Flow control is enabled, and Rx Flow control is\n+\t\t * disabled, by a software over-ride.\n+\t\t */\n+\t\tmii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;\n+\t\tmii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;\n+\t\tbreak;\n+\tcase igc_fc_full:\n+\t\t/* Flow control (both Rx and Tx) is enabled by a software\n+\t\t * over-ride.\n+\t\t */\n+\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n+\t\tbreak;\n+\tdefault:\n+\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tDEBUGOUT1(\"Auto-Neg Advertising %x\\n\", mii_autoneg_adv_reg);\n+\n+\tif (phy->autoneg_mask & ADVERTISE_1000_FULL)\n+\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,\n+\t\t\t\t\t     mii_1000t_ctrl_reg);\n+\n+\tif ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&\n+\t    hw->phy.id == I225_I_PHY_ID)\n+\t\tret_val = phy->ops.write_reg(hw,\n+\t\t\t\t\t     (STANDARD_AN_REG_MASK <<\n+\t\t\t\t\t     MMD_DEVADDR_SHIFT) |\n+\t\t\t\t\t     ANEG_MULTIGBT_AN_CTRL,\n+\t\t\t\t\t     aneg_multigbt_an_ctrl);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_copper_link_autoneg - Setup/Enable autoneg for copper link\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Performs initial bounds checking on autoneg advertisement parameter, then\n+ *  configure to advertise the full capability.  Setup the PHY to autoneg\n+ *  and restart the negotiation process between the link partner.  If\n+ *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.\n+ **/\n+s32 igc_copper_link_autoneg(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_ctrl;\n+\n+\tDEBUGFUNC(\"igc_copper_link_autoneg\");\n+\n+\t/* Perform some bounds checking on the autoneg advertisement\n+\t * parameter.\n+\t */\n+\tphy->autoneg_advertised &= phy->autoneg_mask;\n+\n+\t/* If autoneg_advertised is zero, we assume it was not defaulted\n+\t * by the calling code so we set to advertise full capability.\n+\t */\n+\tif (!phy->autoneg_advertised)\n+\t\tphy->autoneg_advertised = phy->autoneg_mask;\n+\n+\tDEBUGOUT(\"Reconfiguring auto-neg advertisement params\\n\");\n+\tret_val = igc_phy_setup_autoneg(hw);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Error Setting up Auto-Negotiation\\n\");\n+\t\treturn ret_val;\n+\t}\n+\tDEBUGOUT(\"Restarting Auto-Neg\\n\");\n+\n+\t/* Restart auto-negotiation by setting the Auto Neg Enable bit and\n+\t * the Auto Neg Restart bit in the PHY control register.\n+\t */\n+\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);\n+\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Does the user want to wait for Auto-Neg to complete here, or\n+\t * check at a later time (for example, callback routine).\n+\t */\n+\tif (phy->autoneg_wait_to_complete) {\n+\t\tret_val = igc_wait_autoneg(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error while waiting for autoneg to complete\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\thw->mac.get_link_status = true;\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_setup_copper_link_generic - Configure copper link settings\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Calls the appropriate function to configure the link for auto-neg or forced\n+ *  speed and duplex.  Then we check for link, once link is established calls\n+ *  to configure collision distance and flow control are called.  If link is\n+ *  not established, we return -IGC_ERR_PHY (-2).\n+ **/\n+s32 igc_setup_copper_link_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tbool link = false;\n+\n+\tDEBUGFUNC(\"igc_setup_copper_link_generic\");\n+\n+\tif (hw->mac.autoneg) {\n+\t\t/* Setup autoneg and flow control advertisement and perform\n+\t\t * autonegotiation.\n+\t\t */\n+\t\tret_val = igc_copper_link_autoneg(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t} else {\n+\t\t/* PHY will be set to 10H, 10F, 100H or 100F\n+\t\t * depending on user settings.\n+\t\t */\n+\t\tDEBUGOUT(\"Forcing Speed and Duplex\\n\");\n+\t\tret_val = hw->phy.ops.force_speed_duplex(hw);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Error Forcing Speed and Duplex\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\t/* Check link status. Wait up to 100 microseconds for link to become\n+\t * valid.\n+\t */\n+\tret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,\n+\t\t\t\t\t     &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (link) {\n+\t\tDEBUGOUT(\"Valid link established!!!\\n\");\n+\t\thw->mac.ops.config_collision_dist(hw);\n+\t\tret_val = igc_config_fc_after_link_up_generic(hw);\n+\t} else {\n+\t\tDEBUGOUT(\"Unable to establish link!!!\\n\");\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Calls the PHY setup function to force speed and duplex.  Clears the\n+ *  auto-crossover to force MDI manually.  Waits for link and returns\n+ *  successful if link up is successful, else -IGC_ERR_PHY (-2).\n+ **/\n+s32 igc_phy_force_speed_duplex_igp(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_phy_force_speed_duplex_igp\");\n+\n+\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tigc_phy_force_speed_duplex_setup(hw, &phy_data);\n+\n+\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Clear Auto-Crossover to force MDI manually.  IGP requires MDI\n+\t * forced whenever speed and duplex are forced.\n+\t */\n+\tret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy_data &= ~IGP01IGC_PSCR_AUTO_MDIX;\n+\tphy_data &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;\n+\n+\tret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tDEBUGOUT1(\"IGP PSCR: %X\\n\", phy_data);\n+\n+\tusec_delay(1);\n+\n+\tif (phy->autoneg_wait_to_complete) {\n+\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IGP phy.\\n\");\n+\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (!link)\n+\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n+\n+\t\t/* Try once more */\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Calls the PHY setup function to force speed and duplex.  Clears the\n+ *  auto-crossover to force MDI manually.  Resets the PHY to commit the\n+ *  changes.  If time expires while waiting for link up, we reset the DSP.\n+ *  After reset, TX_CLK and CRS on Tx must be set.  Return successful upon\n+ *  successful completion, else return corresponding error code.\n+ **/\n+s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_phy_force_speed_duplex_m88\");\n+\n+\t/* I210 and I211 devices support Auto-Crossover in forced operation. */\n+\tif (phy->type != igc_phy_i210) {\n+\t\t/* Clear Auto-Crossover to force MDI manually.  M88E1000\n+\t\t * requires MDI forced whenever speed and duplex are forced.\n+\t\t */\n+\t\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL,\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy_data &= ~M88IGC_PSCR_AUTO_X_MODE;\n+\t\tret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,\n+\t\t\t\t\t     phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tDEBUGOUT1(\"M88E1000 PSCR: %X\\n\", phy_data);\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tigc_phy_force_speed_duplex_setup(hw, &phy_data);\n+\n+\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Reset the phy to commit changes. */\n+\tret_val = hw->phy.ops.commit(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (phy->autoneg_wait_to_complete) {\n+\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on M88 phy.\\n\");\n+\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (!link) {\n+\t\t\tbool reset_dsp = true;\n+\n+\t\t\tswitch (hw->phy.id) {\n+\t\t\tcase I347AT4_E_PHY_ID:\n+\t\t\tcase M88E1340M_E_PHY_ID:\n+\t\t\tcase M88E1112_E_PHY_ID:\n+\t\t\tcase M88E1543_E_PHY_ID:\n+\t\t\tcase M88E1512_E_PHY_ID:\n+\t\t\tcase I210_I_PHY_ID:\n+\t\t\t/* fall-through */\n+\t\t\tcase I225_I_PHY_ID:\n+\t\t\t/* fall-through */\n+\t\t\t\treset_dsp = false;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tif (hw->phy.type != igc_phy_m88)\n+\t\t\t\t\treset_dsp = false;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (!reset_dsp) {\n+\t\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n+\t\t\t} else {\n+\t\t\t\t/* We didn't get link.\n+\t\t\t\t * Reset the DSP and cross our fingers.\n+\t\t\t\t */\n+\t\t\t\tret_val = phy->ops.write_reg(hw,\n+\t\t\t\t\t\tM88IGC_PHY_PAGE_SELECT,\n+\t\t\t\t\t\t0x001d);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\t\t\t\tret_val = igc_phy_reset_dsp_generic(hw);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Try once more */\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\tif (hw->phy.type != igc_phy_m88)\n+\t\treturn IGC_SUCCESS;\n+\n+\tif (hw->phy.id == I347AT4_E_PHY_ID ||\n+\t\thw->phy.id == M88E1340M_E_PHY_ID ||\n+\t\thw->phy.id == M88E1112_E_PHY_ID)\n+\t\treturn IGC_SUCCESS;\n+\tif (hw->phy.id == I210_I_PHY_ID)\n+\t\treturn IGC_SUCCESS;\n+\tif (hw->phy.id == I225_I_PHY_ID)\n+\t\treturn IGC_SUCCESS;\n+\tif (hw->phy.id == M88E1543_E_PHY_ID || hw->phy.id == M88E1512_E_PHY_ID)\n+\t\treturn IGC_SUCCESS;\n+\tret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Resetting the phy means we need to re-force TX_CLK in the\n+\t * Extended PHY Specific Control Register to 25MHz clock from\n+\t * the reset value of 2.5MHz.\n+\t */\n+\tphy_data |= M88IGC_EPSCR_TX_CLK_25;\n+\tret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* In addition, we must re-enable CRS on Tx for both half and full\n+\t * duplex.\n+\t */\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;\n+\tret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_force_speed_duplex_ife - Force PHY speed & duplex\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Forces the speed and duplex settings of the PHY.\n+ *  This is a function pointer entry point only called by\n+ *  PHY setup routines.\n+ **/\n+s32 igc_phy_force_speed_duplex_ife(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_phy_force_speed_duplex_ife\");\n+\n+\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tigc_phy_force_speed_duplex_setup(hw, &data);\n+\n+\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Disable MDI-X support for 10/100 */\n+\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tdata &= ~IFE_PMC_AUTO_MDIX;\n+\tdata &= ~IFE_PMC_FORCE_MDIX;\n+\n+\tret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tDEBUGOUT1(\"IFE PMC: %X\\n\", data);\n+\n+\tusec_delay(1);\n+\n+\tif (phy->autoneg_wait_to_complete) {\n+\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IFE phy.\\n\");\n+\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (!link)\n+\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n+\n+\t\t/* Try once more */\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex\n+ *  @hw: pointer to the HW structure\n+ *  @phy_ctrl: pointer to current value of PHY_CONTROL\n+ *\n+ *  Forces speed and duplex on the PHY by doing the following: disable flow\n+ *  control, force speed/duplex on the MAC, disable auto speed detection,\n+ *  disable auto-negotiation, configure duplex, configure speed, configure\n+ *  the collision distance, write configuration to CTRL register.  The\n+ *  caller must write to the PHY_CONTROL register for these settings to\n+ *  take affect.\n+ **/\n+void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)\n+{\n+\tstruct igc_mac_info *mac = &hw->mac;\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_phy_force_speed_duplex_setup\");\n+\n+\t/* Turn off flow control when forcing speed/duplex */\n+\thw->fc.current_mode = igc_fc_none;\n+\n+\t/* Force speed/duplex on the mac */\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);\n+\tctrl &= ~IGC_CTRL_SPD_SEL;\n+\n+\t/* Disable Auto Speed Detection */\n+\tctrl &= ~IGC_CTRL_ASDE;\n+\n+\t/* Disable autoneg on the phy */\n+\t*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;\n+\n+\t/* Forcing Full or Half Duplex? */\n+\tif (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {\n+\t\tctrl &= ~IGC_CTRL_FD;\n+\t\t*phy_ctrl &= ~MII_CR_FULL_DUPLEX;\n+\t\tDEBUGOUT(\"Half Duplex\\n\");\n+\t} else {\n+\t\tctrl |= IGC_CTRL_FD;\n+\t\t*phy_ctrl |= MII_CR_FULL_DUPLEX;\n+\t\tDEBUGOUT(\"Full Duplex\\n\");\n+\t}\n+\n+\t/* Forcing 10mb or 100mb? */\n+\tif (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {\n+\t\tctrl |= IGC_CTRL_SPD_100;\n+\t\t*phy_ctrl |= MII_CR_SPEED_100;\n+\t\t*phy_ctrl &= ~MII_CR_SPEED_1000;\n+\t\tDEBUGOUT(\"Forcing 100mb\\n\");\n+\t} else {\n+\t\tctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);\n+\t\t*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);\n+\t\tDEBUGOUT(\"Forcing 10mb\\n\");\n+\t}\n+\n+\thw->mac.ops.config_collision_dist(hw);\n+\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+}\n+\n+/**\n+ *  igc_set_d3_lplu_state_generic - Sets low power link up state for D3\n+ *  @hw: pointer to the HW structure\n+ *  @active: boolean used to enable/disable lplu\n+ *\n+ *  Success returns 0, Failure returns 1\n+ *\n+ *  The low power link up (lplu) state is set to the power management level D3\n+ *  and SmartSpeed is disabled when active is true, else clear lplu for D3\n+ *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU\n+ *  is used during Dx states where the power conservation is most important.\n+ *  During driver activity, SmartSpeed should be enabled so performance is\n+ *  maintained.\n+ **/\n+s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_set_d3_lplu_state_generic\");\n+\n+\tif (!hw->phy.ops.read_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!active) {\n+\t\tdata &= ~IGP02IGC_PM_D3_LPLU;\n+\t\tret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,\n+\t\t\t\t\t     data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\t/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used\n+\t\t * during Dx states where the power conservation is most\n+\t\t * important.  During driver activity we should enable\n+\t\t * SmartSpeed, so performance is maintained.\n+\t\t */\n+\t\tif (phy->smart_speed == igc_smart_speed_on) {\n+\t\t\tret_val = phy->ops.read_reg(hw,\n+\t\t\t\t\t\t    IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t    &data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\n+\t\t\tdata |= IGP01IGC_PSCFR_SMART_SPEED;\n+\t\t\tret_val = phy->ops.write_reg(hw,\n+\t\t\t\t\t\t     IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t     data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t} else if (phy->smart_speed == igc_smart_speed_off) {\n+\t\t\tret_val = phy->ops.read_reg(hw,\n+\t\t\t\t\t\t    IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t    &data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\n+\t\t\tdata &= ~IGP01IGC_PSCFR_SMART_SPEED;\n+\t\t\tret_val = phy->ops.write_reg(hw,\n+\t\t\t\t\t\t     IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t\t     data);\n+\t\t\tif (ret_val)\n+\t\t\t\treturn ret_val;\n+\t\t}\n+\t} else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||\n+\t\t   (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||\n+\t\t   (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {\n+\t\tdata |= IGP02IGC_PM_D3_LPLU;\n+\t\tret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,\n+\t\t\t\t\t     data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n+\t\tret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t    &data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tdata &= ~IGP01IGC_PSCFR_SMART_SPEED;\n+\t\tret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,\n+\t\t\t\t\t     data);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_check_downshift_generic - Checks whether a downshift in speed occurred\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Success returns 0, Failure returns 1\n+ *\n+ *  A downshift is detected by querying the PHY link health.\n+ **/\n+s32 igc_check_downshift_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data, offset, mask;\n+\n+\tDEBUGFUNC(\"igc_check_downshift_generic\");\n+\n+\tswitch (phy->type) {\n+\tcase igc_phy_i210:\n+\tcase igc_phy_m88:\n+\tcase igc_phy_gg82563:\n+\tcase igc_phy_bm:\n+\tcase igc_phy_82578:\n+\t\toffset = M88IGC_PHY_SPEC_STATUS;\n+\t\tmask = M88IGC_PSSR_DOWNSHIFT;\n+\t\tbreak;\n+\tcase igc_phy_igp:\n+\tcase igc_phy_igp_2:\n+\tcase igc_phy_igp_3:\n+\t\toffset = IGP01IGC_PHY_LINK_HEALTH;\n+\t\tmask = IGP01IGC_PLHR_SS_DOWNGRADE;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* speed downshift not supported */\n+\t\tphy->speed_downgraded = false;\n+\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n+\n+\tif (!ret_val)\n+\t\tphy->speed_downgraded = !!(phy_data & mask);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_check_polarity_m88 - Checks the polarity.\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Success returns 0, Failure returns -IGC_ERR_PHY (-2)\n+ *\n+ *  Polarity is determined based on the PHY specific status register.\n+ **/\n+s32 igc_check_polarity_m88(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_check_polarity_m88\");\n+\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &data);\n+\n+\tif (!ret_val)\n+\t\tphy->cable_polarity = ((data & M88IGC_PSSR_REV_POLARITY)\n+\t\t\t\t       ? igc_rev_polarity_reversed\n+\t\t\t\t       : igc_rev_polarity_normal);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_check_polarity_igp - Checks the polarity.\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Success returns 0, Failure returns -IGC_ERR_PHY (-2)\n+ *\n+ *  Polarity is determined based on the PHY port status register, and the\n+ *  current speed (since there is no polarity at 100Mbps).\n+ **/\n+s32 igc_check_polarity_igp(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data, offset, mask;\n+\n+\tDEBUGFUNC(\"igc_check_polarity_igp\");\n+\n+\t/* Polarity is determined based on the speed of\n+\t * our connection.\n+\t */\n+\tret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif ((data & IGP01IGC_PSSR_SPEED_MASK) ==\n+\t    IGP01IGC_PSSR_SPEED_1000MBPS) {\n+\t\toffset = IGP01IGC_PHY_PCS_INIT_REG;\n+\t\tmask = IGP01IGC_PHY_POLARITY_MASK;\n+\t} else {\n+\t\t/* This really only applies to 10Mbps since\n+\t\t * there is no polarity for 100Mbps (always 0).\n+\t\t */\n+\t\toffset = IGP01IGC_PHY_PORT_STATUS;\n+\t\tmask = IGP01IGC_PSSR_POLARITY_REVERSED;\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, offset, &data);\n+\n+\tif (!ret_val)\n+\t\tphy->cable_polarity = ((data & mask)\n+\t\t\t\t       ? igc_rev_polarity_reversed\n+\t\t\t\t       : igc_rev_polarity_normal);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_check_polarity_ife - Check cable polarity for IFE PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Polarity is determined on the polarity reversal feature being enabled.\n+ **/\n+s32 igc_check_polarity_ife(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data, offset, mask;\n+\n+\tDEBUGFUNC(\"igc_check_polarity_ife\");\n+\n+\t/* Polarity is determined based on the reversal feature being enabled.\n+\t */\n+\tif (phy->polarity_correction) {\n+\t\toffset = IFE_PHY_EXTENDED_STATUS_CONTROL;\n+\t\tmask = IFE_PESC_POLARITY_REVERSED;\n+\t} else {\n+\t\toffset = IFE_PHY_SPECIAL_CONTROL;\n+\t\tmask = IFE_PSC_FORCE_POLARITY;\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n+\n+\tif (!ret_val)\n+\t\tphy->cable_polarity = ((phy_data & mask)\n+\t\t\t\t       ? igc_rev_polarity_reversed\n+\t\t\t\t       : igc_rev_polarity_normal);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_wait_autoneg - Wait for auto-neg completion\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Waits for auto-negotiation to complete or for the auto-negotiation time\n+ *  limit to expire, which ever happens first.\n+ **/\n+static s32 igc_wait_autoneg(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu16 i, phy_status;\n+\n+\tDEBUGFUNC(\"igc_wait_autoneg\");\n+\n+\tif (!hw->phy.ops.read_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */\n+\tfor (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\t\tif (phy_status & MII_SR_AUTONEG_COMPLETE)\n+\t\t\tbreak;\n+\t\tmsec_delay(100);\n+\t}\n+\n+\t/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation\n+\t * has completed.\n+\t */\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_has_link_generic - Polls PHY for link\n+ *  @hw: pointer to the HW structure\n+ *  @iterations: number of times to poll for link\n+ *  @usec_interval: delay between polling attempts\n+ *  @success: pointer to whether polling was successful or not\n+ *\n+ *  Polls the PHY status register for link, 'iterations' number of times.\n+ **/\n+s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,\n+\t\t\t       u32 usec_interval, bool *success)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu16 i, phy_status;\n+\n+\tDEBUGFUNC(\"igc_phy_has_link_generic\");\n+\n+\tif (!hw->phy.ops.read_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\tfor (i = 0; i < iterations; i++) {\n+\t\t/* Some PHYs require the PHY_STATUS register to be read\n+\t\t * twice due to the link bit being sticky.  No harm doing\n+\t\t * it across the board.\n+\t\t */\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n+\t\tif (ret_val) {\n+\t\t\t/* If the first read fails, another entity may have\n+\t\t\t * ownership of the resources, wait and try again to\n+\t\t\t * see if they have relinquished the resources yet.\n+\t\t\t */\n+\t\t\tif (usec_interval >= 1000)\n+\t\t\t\tmsec_delay(usec_interval / 1000);\n+\t\t\telse\n+\t\t\t\tusec_delay(usec_interval);\n+\t\t}\n+\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\t\tif (phy_status & MII_SR_LINK_STATUS)\n+\t\t\tbreak;\n+\t\tif (usec_interval >= 1000)\n+\t\t\tmsec_delay(usec_interval / 1000);\n+\t\telse\n+\t\t\tusec_delay(usec_interval);\n+\t}\n+\n+\t*success = (i < iterations);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_cable_length_m88 - Determine cable length for m88 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Reads the PHY specific status register to retrieve the cable length\n+ *  information.  The cable length is determined by averaging the minimum and\n+ *  maximum values to get the \"average\" cable length.  The m88 PHY has four\n+ *  possible cable length values, which are:\n+ *\tRegister Value\t\tCable Length\n+ *\t0\t\t\t< 50 meters\n+ *\t1\t\t\t50 - 80 meters\n+ *\t2\t\t\t80 - 110 meters\n+ *\t3\t\t\t110 - 140 meters\n+ *\t4\t\t\t> 140 meters\n+ **/\n+s32 igc_get_cable_length_m88(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data, index;\n+\n+\tDEBUGFUNC(\"igc_get_cable_length_m88\");\n+\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tindex = ((phy_data & M88IGC_PSSR_CABLE_LENGTH) >>\n+\t\t M88IGC_PSSR_CABLE_LENGTH_SHIFT);\n+\n+\tif (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\tphy->min_cable_length = igc_m88_cable_length_table[index];\n+\tphy->max_cable_length = igc_m88_cable_length_table[index + 1];\n+\n+\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+s32 igc_get_cable_length_m88_gen2(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val  = 0;\n+\tu16 phy_data, phy_data2, is_cm;\n+\tu16 index, default_page;\n+\n+\tDEBUGFUNC(\"igc_get_cable_length_m88_gen2\");\n+\n+\tswitch (hw->phy.id) {\n+\tcase I210_I_PHY_ID:\n+\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n+\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n+\t\t\t\t\t    (I347AT4_PCDL + phy->addr),\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Check if the unit of cable length is meters or cm */\n+\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n+\t\t\t\t\t    I347AT4_PCDC, &phy_data2);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n+\n+\t\t/* Populate the phy structure with cable length in meters */\n+\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n+\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n+\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n+\t\tbreak;\n+\tcase I225_I_PHY_ID:\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\t/* TODO - complete with Foxville data */\n+\t\tbreak;\n+\tcase M88E1543_E_PHY_ID:\n+\tcase M88E1512_E_PHY_ID:\n+\tcase M88E1340M_E_PHY_ID:\n+\tcase I347AT4_E_PHY_ID:\n+\t\t/* Remember the original page select and set it to 7 */\n+\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n+\t\t\t\t\t    &default_page);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n+\t\tret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Check if the unit of cable length is meters or cm */\n+\t\tret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n+\n+\t\t/* Populate the phy structure with cable length in meters */\n+\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n+\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n+\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n+\n+\t\t/* Reset the page select to its original value */\n+\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n+\t\t\t\t\t     default_page);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tbreak;\n+\n+\tcase M88E1112_E_PHY_ID:\n+\t\t/* Remember the original page select and set it to 5 */\n+\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n+\t\t\t\t\t    &default_page);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,\n+\t\t\t\t\t    &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tindex = (phy_data & M88IGC_PSSR_CABLE_LENGTH) >>\n+\t\t\tM88IGC_PSSR_CABLE_LENGTH_SHIFT;\n+\n+\t\tif (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)\n+\t\t\treturn -IGC_ERR_PHY;\n+\n+\t\tphy->min_cable_length = igc_m88_cable_length_table[index];\n+\t\tphy->max_cable_length = igc_m88_cable_length_table[index + 1];\n+\n+\t\tphy->cable_length = (phy->min_cable_length +\n+\t\t\t\t     phy->max_cable_length) / 2;\n+\n+\t\t/* Reset the page select to its original value */\n+\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n+\t\t\t\t\t     default_page);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -IGC_ERR_PHY;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_cable_length_igp_2 - Determine cable length for igp2 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  The automatic gain control (agc) normalizes the amplitude of the\n+ *  received signal, adjusting for the attenuation produced by the\n+ *  cable.  By reading the AGC registers, which represent the\n+ *  combination of coarse and fine gain value, the value can be put\n+ *  into a lookup table to obtain the approximate cable length\n+ *  for each channel.\n+ **/\n+s32 igc_get_cable_length_igp_2(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data, i, agc_value = 0;\n+\tu16 cur_agc_index, max_agc_index = 0;\n+\tu16 min_agc_index = IGP02IGC_CABLE_LENGTH_TABLE_SIZE - 1;\n+\tstatic const u16 agc_reg_array[IGP02IGC_PHY_CHANNEL_NUM] = {\n+\t\tIGP02IGC_PHY_AGC_A,\n+\t\tIGP02IGC_PHY_AGC_B,\n+\t\tIGP02IGC_PHY_AGC_C,\n+\t\tIGP02IGC_PHY_AGC_D\n+\t};\n+\n+\tDEBUGFUNC(\"igc_get_cable_length_igp_2\");\n+\n+\t/* Read the AGC registers for all channels */\n+\tfor (i = 0; i < IGP02IGC_PHY_CHANNEL_NUM; i++) {\n+\t\tret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Getting bits 15:9, which represent the combination of\n+\t\t * coarse and fine gain values.  The result is a number\n+\t\t * that can be put into the lookup table to obtain the\n+\t\t * approximate cable length.\n+\t\t */\n+\t\tcur_agc_index = ((phy_data >> IGP02IGC_AGC_LENGTH_SHIFT) &\n+\t\t\t\t IGP02IGC_AGC_LENGTH_MASK);\n+\n+\t\t/* Array index bound check. */\n+\t\tif (cur_agc_index >= IGP02IGC_CABLE_LENGTH_TABLE_SIZE ||\n+\t\t\t\tcur_agc_index == 0)\n+\t\t\treturn -IGC_ERR_PHY;\n+\n+\t\t/* Remove min & max AGC values from calculation. */\n+\t\tif (igc_igp_2_cable_length_table[min_agc_index] >\n+\t\t    igc_igp_2_cable_length_table[cur_agc_index])\n+\t\t\tmin_agc_index = cur_agc_index;\n+\t\tif (igc_igp_2_cable_length_table[max_agc_index] <\n+\t\t    igc_igp_2_cable_length_table[cur_agc_index])\n+\t\t\tmax_agc_index = cur_agc_index;\n+\n+\t\tagc_value += igc_igp_2_cable_length_table[cur_agc_index];\n+\t}\n+\n+\tagc_value -= (igc_igp_2_cable_length_table[min_agc_index] +\n+\t\t      igc_igp_2_cable_length_table[max_agc_index]);\n+\tagc_value /= (IGP02IGC_PHY_CHANNEL_NUM - 2);\n+\n+\t/* Calculate cable length with the error range of +/- 10 meters. */\n+\tphy->min_cable_length = (((agc_value - IGP02IGC_AGC_RANGE) > 0) ?\n+\t\t\t\t (agc_value - IGP02IGC_AGC_RANGE) : 0);\n+\tphy->max_cable_length = agc_value + IGP02IGC_AGC_RANGE;\n+\n+\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_phy_info_m88 - Retrieve PHY information\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Valid for only copper links.  Read the PHY status register (sticky read)\n+ *  to verify that link is up.  Read the PHY special control register to\n+ *  determine the polarity and 10base-T extended distance.  Read the PHY\n+ *  special status register to determine MDI/MDIx and current speed.  If\n+ *  speed is 1000, then determine cable length, local and remote receiver.\n+ **/\n+s32 igc_get_phy_info_m88(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32  ret_val;\n+\tu16 phy_data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_get_phy_info_m88\");\n+\n+\tif (phy->media_type != igc_media_type_copper) {\n+\t\tDEBUGOUT(\"Phy info is only valid for copper media\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!link) {\n+\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy->polarity_correction = !!(phy_data &\n+\t\t\t\t      M88IGC_PSCR_POLARITY_REVERSAL);\n+\n+\tret_val = igc_check_polarity_m88(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy->is_mdix = !!(phy_data & M88IGC_PSSR_MDIX);\n+\n+\tif ((phy_data & M88IGC_PSSR_SPEED) == M88IGC_PSSR_1000MBS) {\n+\t\tret_val = hw->phy.ops.get_cable_length(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)\n+\t\t\t\t? igc_1000t_rx_status_ok\n+\t\t\t\t: igc_1000t_rx_status_not_ok;\n+\n+\t\tphy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)\n+\t\t\t\t ? igc_1000t_rx_status_ok\n+\t\t\t\t : igc_1000t_rx_status_not_ok;\n+\t} else {\n+\t\t/* Set values to \"undefined\" */\n+\t\tphy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;\n+\t\tphy->local_rx = igc_1000t_rx_status_undefined;\n+\t\tphy->remote_rx = igc_1000t_rx_status_undefined;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_phy_info_igp - Retrieve igp PHY information\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Read PHY status to determine if link is up.  If link is up, then\n+ *  set/determine 10base-T extended distance and polarity correction.  Read\n+ *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,\n+ *  determine on the cable length, local and remote receiver.\n+ **/\n+s32 igc_get_phy_info_igp(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_get_phy_info_igp\");\n+\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!link) {\n+\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tphy->polarity_correction = true;\n+\n+\tret_val = igc_check_polarity_igp(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy->is_mdix = !!(data & IGP01IGC_PSSR_MDIX);\n+\n+\tif ((data & IGP01IGC_PSSR_SPEED_MASK) ==\n+\t    IGP01IGC_PSSR_SPEED_1000MBPS) {\n+\t\tret_val = phy->ops.get_cable_length(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n+\t\t\t\t? igc_1000t_rx_status_ok\n+\t\t\t\t: igc_1000t_rx_status_not_ok;\n+\n+\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n+\t\t\t\t ? igc_1000t_rx_status_ok\n+\t\t\t\t : igc_1000t_rx_status_not_ok;\n+\t} else {\n+\t\tphy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;\n+\t\tphy->local_rx = igc_1000t_rx_status_undefined;\n+\t\tphy->remote_rx = igc_1000t_rx_status_undefined;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_phy_info_ife - Retrieves various IFE PHY states\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Populates \"phy\" structure with various feature states.\n+ **/\n+s32 igc_get_phy_info_ife(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_get_phy_info_ife\");\n+\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!link) {\n+\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\tphy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);\n+\n+\tif (phy->polarity_correction) {\n+\t\tret_val = igc_check_polarity_ife(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t} else {\n+\t\t/* Polarity is forced */\n+\t\tphy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)\n+\t\t\t\t       ? igc_rev_polarity_reversed\n+\t\t\t\t       : igc_rev_polarity_normal);\n+\t}\n+\n+\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);\n+\n+\t/* The following parameters are undefined for 10/100 operation. */\n+\tphy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;\n+\tphy->local_rx = igc_1000t_rx_status_undefined;\n+\tphy->remote_rx = igc_1000t_rx_status_undefined;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_sw_reset_generic - PHY software reset\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Does a software reset of the PHY by reading the PHY control register and\n+ *  setting/write the control register reset bit to the PHY.\n+ **/\n+s32 igc_phy_sw_reset_generic(struct igc_hw *hw)\n+{\n+\ts32 ret_val;\n+\tu16 phy_ctrl;\n+\n+\tDEBUGFUNC(\"igc_phy_sw_reset_generic\");\n+\n+\tif (!hw->phy.ops.read_reg)\n+\t\treturn IGC_SUCCESS;\n+\n+\tret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy_ctrl |= MII_CR_RESET;\n+\tret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tusec_delay(1);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_hw_reset_generic - PHY hardware reset\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Verify the reset block is not blocking us from resetting.  Acquire\n+ *  semaphore (if necessary) and read/set/write the device control reset\n+ *  bit in the PHY.  Wait the appropriate delay time for the device to\n+ *  reset and release the semaphore (if necessary).\n+ **/\n+s32 igc_phy_hw_reset_generic(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu32 ctrl;\n+\n+\tDEBUGFUNC(\"igc_phy_hw_reset_generic\");\n+\n+\tif (phy->ops.check_reset_block) {\n+\t\tret_val = phy->ops.check_reset_block(hw);\n+\t\tif (ret_val)\n+\t\t\treturn IGC_SUCCESS;\n+\t}\n+\n+\tret_val = phy->ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tctrl = IGC_READ_REG(hw, IGC_CTRL);\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tusec_delay(phy->reset_delay_us);\n+\n+\tIGC_WRITE_REG(hw, IGC_CTRL, ctrl);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\tusec_delay(150);\n+\n+\tphy->ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_cfg_done_generic - Generic configuration done\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Generic function to wait 10 milli-seconds for configuration to complete\n+ *  and return success.\n+ **/\n+s32 igc_get_cfg_done_generic(struct igc_hw IGC_UNUSEDARG * hw)\n+{\n+\tDEBUGFUNC(\"igc_get_cfg_done_generic\");\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tmsec_delay_irq(10);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_phy_init_script_igp3 - Inits the IGP3 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.\n+ **/\n+s32 igc_phy_init_script_igp3(struct igc_hw *hw)\n+{\n+\tDEBUGOUT(\"Running IGP 3 PHY init script\\n\");\n+\n+\t/* PHY init IGP 3 */\n+\t/* Enable rise/fall, 10-mode work in class-A */\n+\thw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);\n+\t/* Remove all caps from Replica path filter */\n+\thw->phy.ops.write_reg(hw, 0x2F52, 0x0000);\n+\t/* Bias trimming for ADC, AFE and Driver (Default) */\n+\thw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);\n+\t/* Increase Hybrid poly bias */\n+\thw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);\n+\t/* Add 4% to Tx amplitude in Gig mode */\n+\thw->phy.ops.write_reg(hw, 0x2010, 0x10B0);\n+\t/* Disable trimming (TTT) */\n+\thw->phy.ops.write_reg(hw, 0x2011, 0x0000);\n+\t/* Poly DC correction to 94.6% + 2% for all channels */\n+\thw->phy.ops.write_reg(hw, 0x20DD, 0x249A);\n+\t/* ABS DC correction to 95.9% */\n+\thw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);\n+\t/* BG temp curve trim */\n+\thw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);\n+\t/* Increasing ADC OPAMP stage 1 currents to max */\n+\thw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);\n+\t/* Force 1000 ( required for enabling PHY regs configuration) */\n+\thw->phy.ops.write_reg(hw, 0x0000, 0x0140);\n+\t/* Set upd_freq to 6 */\n+\thw->phy.ops.write_reg(hw, 0x1F30, 0x1606);\n+\t/* Disable NPDFE */\n+\thw->phy.ops.write_reg(hw, 0x1F31, 0xB814);\n+\t/* Disable adaptive fixed FFE (Default) */\n+\thw->phy.ops.write_reg(hw, 0x1F35, 0x002A);\n+\t/* Enable FFE hysteresis */\n+\thw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);\n+\t/* Fixed FFE for short cable lengths */\n+\thw->phy.ops.write_reg(hw, 0x1F54, 0x0065);\n+\t/* Fixed FFE for medium cable lengths */\n+\thw->phy.ops.write_reg(hw, 0x1F55, 0x002A);\n+\t/* Fixed FFE for long cable lengths */\n+\thw->phy.ops.write_reg(hw, 0x1F56, 0x002A);\n+\t/* Enable Adaptive Clip Threshold */\n+\thw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);\n+\t/* AHT reset limit to 1 */\n+\thw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);\n+\t/* Set AHT master delay to 127 msec */\n+\thw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);\n+\t/* Set scan bits for AHT */\n+\thw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);\n+\t/* Set AHT Preset bits */\n+\thw->phy.ops.write_reg(hw, 0x1F79, 0x0210);\n+\t/* Change integ_factor of channel A to 3 */\n+\thw->phy.ops.write_reg(hw, 0x1895, 0x0003);\n+\t/* Change prop_factor of channels BCD to 8 */\n+\thw->phy.ops.write_reg(hw, 0x1796, 0x0008);\n+\t/* Change cg_icount + enable integbp for channels BCD */\n+\thw->phy.ops.write_reg(hw, 0x1798, 0xD008);\n+\t/* Change cg_icount + enable integbp + change prop_factor_master\n+\t * to 8 for channel A\n+\t */\n+\thw->phy.ops.write_reg(hw, 0x1898, 0xD918);\n+\t/* Disable AHT in Slave mode on channel A */\n+\thw->phy.ops.write_reg(hw, 0x187A, 0x0800);\n+\t/* Enable LPLU and disable AN to 1000 in non-D0a states,\n+\t * Enable SPD+B2B\n+\t */\n+\thw->phy.ops.write_reg(hw, 0x0019, 0x008D);\n+\t/* Enable restart AN on an1000_dis change */\n+\thw->phy.ops.write_reg(hw, 0x001B, 0x2080);\n+\t/* Enable wh_fifo read clock in 10/100 modes */\n+\thw->phy.ops.write_reg(hw, 0x0014, 0x0045);\n+\t/* Restart AN, Speed selection is 1000 */\n+\thw->phy.ops.write_reg(hw, 0x0000, 0x1340);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_phy_type_from_id - Get PHY type from id\n+ *  @phy_id: phy_id read from the phy\n+ *\n+ *  Returns the phy type from the id.\n+ **/\n+enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id)\n+{\n+\tenum igc_phy_type phy_type = igc_phy_unknown;\n+\n+\tswitch (phy_id) {\n+\tcase M88IGC_I_PHY_ID:\n+\tcase M88IGC_E_PHY_ID:\n+\tcase M88E1111_I_PHY_ID:\n+\tcase M88E1011_I_PHY_ID:\n+\tcase M88E1543_E_PHY_ID:\n+\tcase M88E1512_E_PHY_ID:\n+\tcase I347AT4_E_PHY_ID:\n+\tcase M88E1112_E_PHY_ID:\n+\tcase M88E1340M_E_PHY_ID:\n+\t\tphy_type = igc_phy_m88;\n+\t\tbreak;\n+\tcase IGP01IGC_I_PHY_ID: /* IGP 1 & 2 share this */\n+\t\tphy_type = igc_phy_igp_2;\n+\t\tbreak;\n+\tcase GG82563_E_PHY_ID:\n+\t\tphy_type = igc_phy_gg82563;\n+\t\tbreak;\n+\tcase IGP03IGC_E_PHY_ID:\n+\t\tphy_type = igc_phy_igp_3;\n+\t\tbreak;\n+\tcase IFE_E_PHY_ID:\n+\tcase IFE_PLUS_E_PHY_ID:\n+\tcase IFE_C_E_PHY_ID:\n+\t\tphy_type = igc_phy_ife;\n+\t\tbreak;\n+\tcase BMIGC_E_PHY_ID:\n+\tcase BMIGC_E_PHY_ID_R2:\n+\t\tphy_type = igc_phy_bm;\n+\t\tbreak;\n+\tcase I82578_E_PHY_ID:\n+\t\tphy_type = igc_phy_82578;\n+\t\tbreak;\n+\tcase I82577_E_PHY_ID:\n+\t\tphy_type = igc_phy_82577;\n+\t\tbreak;\n+\tcase I82579_E_PHY_ID:\n+\t\tphy_type = igc_phy_82579;\n+\t\tbreak;\n+\tcase I217_E_PHY_ID:\n+\t\tphy_type = igc_phy_i217;\n+\t\tbreak;\n+\tcase I82580_I_PHY_ID:\n+\t\tphy_type = igc_phy_82580;\n+\t\tbreak;\n+\tcase I210_I_PHY_ID:\n+\t\tphy_type = igc_phy_i210;\n+\t\tbreak;\n+\tcase I225_I_PHY_ID:\n+\t\tphy_type = igc_phy_i225;\n+\t\tbreak;\n+\tdefault:\n+\t\tphy_type = igc_phy_unknown;\n+\t\tbreak;\n+\t}\n+\treturn phy_type;\n+}\n+\n+/**\n+ *  igc_determine_phy_address - Determines PHY address.\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This uses a trial and error method to loop through possible PHY\n+ *  addresses. It tests each by reading the PHY ID registers and\n+ *  checking for a match.\n+ **/\n+s32 igc_determine_phy_address(struct igc_hw *hw)\n+{\n+\tu32 phy_addr = 0;\n+\tu32 i;\n+\tenum igc_phy_type phy_type = igc_phy_unknown;\n+\n+\thw->phy.id = phy_type;\n+\n+\tfor (phy_addr = 0; phy_addr < IGC_MAX_PHY_ADDR; phy_addr++) {\n+\t\thw->phy.addr = phy_addr;\n+\t\ti = 0;\n+\n+\t\tdo {\n+\t\t\tigc_get_phy_id(hw);\n+\t\t\tphy_type = igc_get_phy_type_from_id(hw->phy.id);\n+\n+\t\t\t/* If phy_type is valid, break - we found our\n+\t\t\t * PHY address\n+\t\t\t */\n+\t\t\tif (phy_type != igc_phy_unknown)\n+\t\t\t\treturn IGC_SUCCESS;\n+\n+\t\t\tmsec_delay(1);\n+\t\t\ti++;\n+\t\t} while (i < 10);\n+\t}\n+\n+\treturn -IGC_ERR_PHY_TYPE;\n+}\n+\n+/**\n+ *  igc_get_phy_addr_for_bm_page - Retrieve PHY page address\n+ *  @page: page to access\n+ *  @reg: register to access\n+ *\n+ *  Returns the phy address for the page requested.\n+ **/\n+static u32 igc_get_phy_addr_for_bm_page(u32 page, u32 reg)\n+{\n+\tu32 phy_addr = 2;\n+\n+\tif (page >= 768 || (page == 0 && reg == 25) || reg == 31)\n+\t\tphy_addr = 1;\n+\n+\treturn phy_addr;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_bm - Write BM PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\ts32 ret_val;\n+\tu32 page = offset >> IGP_PAGE_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_bm\");\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,\n+\t\t\t\t\t\t\t false, false);\n+\t\tgoto release;\n+\t}\n+\n+\thw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n+\t\tu32 page_shift, page_select;\n+\n+\t\t/* Page select is register 31 for phy address 1 and 22 for\n+\t\t * phy address 2 and 3. Page select is shifted only for\n+\t\t * phy address 1.\n+\t\t */\n+\t\tif (hw->phy.addr == 1) {\n+\t\t\tpage_shift = IGP_PAGE_SHIFT;\n+\t\t\tpage_select = IGP01IGC_PHY_PAGE_SELECT;\n+\t\t} else {\n+\t\t\tpage_shift = 0;\n+\t\t\tpage_select = BM_PHY_PAGE_SELECT;\n+\t\t}\n+\n+\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\tret_val = igc_write_phy_reg_mdic(hw, page_select,\n+\t\t\t\t\t\t   (page << page_shift));\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t}\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t   data);\n+\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_bm - Read BM PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore, if necessary, then reads the PHY register at offset\n+ *  and storing the retrieved information in data.  Release any acquired\n+ *  semaphores before exiting.\n+ **/\n+s32 igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\ts32 ret_val;\n+\tu32 page = offset >> IGP_PAGE_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_bm\");\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,\n+\t\t\t\t\t\t\t true, false);\n+\t\tgoto release;\n+\t}\n+\n+\thw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n+\t\tu32 page_shift, page_select;\n+\n+\t\t/* Page select is register 31 for phy address 1 and 22 for\n+\t\t * phy address 2 and 3. Page select is shifted only for\n+\t\t * phy address 1.\n+\t\t */\n+\t\tif (hw->phy.addr == 1) {\n+\t\t\tpage_shift = IGP_PAGE_SHIFT;\n+\t\t\tpage_select = IGP01IGC_PHY_PAGE_SELECT;\n+\t\t} else {\n+\t\t\tpage_shift = 0;\n+\t\t\tpage_select = BM_PHY_PAGE_SELECT;\n+\t\t}\n+\n+\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\tret_val = igc_write_phy_reg_mdic(hw, page_select,\n+\t\t\t\t\t\t   (page << page_shift));\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t}\n+\n+\tret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t  data);\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_bm2 - Read BM PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore, if necessary, then reads the PHY register at offset\n+ *  and storing the retrieved information in data.  Release any acquired\n+ *  semaphores before exiting.\n+ **/\n+s32 igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\ts32 ret_val;\n+\tu16 page = (u16)(offset >> IGP_PAGE_SHIFT);\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_bm2\");\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,\n+\t\t\t\t\t\t\t true, false);\n+\t\tgoto release;\n+\t}\n+\n+\thw->phy.addr = 1;\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n+\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\tret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,\n+\t\t\t\t\t\t   page);\n+\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t}\n+\n+\tret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t  data);\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_bm2 - Write BM PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\ts32 ret_val;\n+\tu16 page = (u16)(offset >> IGP_PAGE_SHIFT);\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_bm2\");\n+\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,\n+\t\t\t\t\t\t\t false, false);\n+\t\tgoto release;\n+\t}\n+\n+\thw->phy.addr = 1;\n+\n+\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n+\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\tret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,\n+\t\t\t\t\t\t   page);\n+\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t}\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n+\t\t\t\t\t   data);\n+\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers\n+ *  @hw: pointer to the HW structure\n+ *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG\n+ *\n+ *  Assumes semaphore already acquired and phy_reg points to a valid memory\n+ *  address to store contents of the BM_WUC_ENABLE_REG register.\n+ **/\n+s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)\n+{\n+\ts32 ret_val;\n+\tu16 temp;\n+\n+\tDEBUGFUNC(\"igc_enable_phy_wakeup_reg_access_bm\");\n+\n+\tif (!phy_reg)\n+\t\treturn -IGC_ERR_PARAM;\n+\n+\t/* All page select, port ctrl and wakeup registers use phy address 1 */\n+\thw->phy.addr = 1;\n+\n+\t/* Select Port Control Registers page */\n+\tret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Could not set Port Control page\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\tret_val = igc_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);\n+\tif (ret_val) {\n+\t\tDEBUGOUT2(\"Could not read PHY register %d.%d\\n\",\n+\t\t\t  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Enable both PHY wakeup mode and Wakeup register page writes.\n+\t * Prevent a power state change by disabling ME and Host PHY wakeup.\n+\t */\n+\ttemp = *phy_reg;\n+\ttemp |= BM_WUC_ENABLE_BIT;\n+\ttemp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);\n+\tif (ret_val) {\n+\t\tDEBUGOUT2(\"Could not write PHY register %d.%d\\n\",\n+\t\t\t  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Select Host Wakeup Registers page - caller now able to write\n+\t * registers on the Wakeup registers page\n+\t */\n+\treturn igc_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));\n+}\n+\n+/**\n+ *  igc_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs\n+ *  @hw: pointer to the HW structure\n+ *  @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG\n+ *\n+ *  Restore BM_WUC_ENABLE_REG to its original value.\n+ *\n+ *  Assumes semaphore already acquired and *phy_reg is the contents of the\n+ *  BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by\n+ *  caller.\n+ **/\n+s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"igc_disable_phy_wakeup_reg_access_bm\");\n+\n+\tif (!phy_reg)\n+\t\treturn -IGC_ERR_PARAM;\n+\n+\t/* Select Port Control Registers page */\n+\tret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Could not set Port Control page\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Restore 769.17 to its original value */\n+\tret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);\n+\tif (ret_val)\n+\t\tDEBUGOUT2(\"Could not restore PHY register %d.%d\\n\",\n+\t\t\t  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read or written\n+ *  @data: pointer to the data to read or write\n+ *  @read: determines if operation is read or write\n+ *  @page_set: BM_WUC_PAGE already set and access enabled\n+ *\n+ *  Read the PHY register at offset and store the retrieved information in\n+ *  data, or write data to PHY register at offset.  Note the procedure to\n+ *  access the PHY wakeup registers is different than reading the other PHY\n+ *  registers. It works as such:\n+ *  1) Set 769.17.2 (page 769, register 17, bit 2) = 1\n+ *  2) Set page to 800 for host (801 if we were manageability)\n+ *  3) Write the address using the address opcode (0x11)\n+ *  4) Read or write the data using the data opcode (0x12)\n+ *  5) Restore 769.17.2 to its original value\n+ *\n+ *  Steps 1 and 2 are done by igc_enable_phy_wakeup_reg_access_bm() and\n+ *  step 5 is done by igc_disable_phy_wakeup_reg_access_bm().\n+ *\n+ *  Assumes semaphore is already acquired.  When page_set==true, assumes\n+ *  the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack\n+ *  is responsible for calls to igc_[enable|disable]_phy_wakeup_reg_bm()).\n+ **/\n+static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,\n+\t\t\t\t\t  u16 *data, bool read, bool page_set)\n+{\n+\ts32 ret_val;\n+\tu16 reg = BM_PHY_REG_NUM(offset);\n+\tu16 page = BM_PHY_REG_PAGE(offset);\n+\tu16 phy_reg = 0;\n+\n+\tDEBUGFUNC(\"igc_access_phy_wakeup_reg_bm\");\n+\n+\t/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */\n+\tif (hw->mac.type == igc_pchlan &&\n+\t\t!(IGC_READ_REG(hw, IGC_PHY_CTRL) & IGC_PHY_CTRL_GBE_DISABLE))\n+\t\tDEBUGOUT1(\"Attempting to access page %d while gig enabled.\\n\",\n+\t\t\t  page);\n+\n+\tif (!page_set) {\n+\t\t/* Enable access to PHY wakeup registers */\n+\t\tret_val = igc_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n+\t\tif (ret_val) {\n+\t\t\tDEBUGOUT(\"Could not enable PHY wakeup reg access\\n\");\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\n+\tDEBUGOUT2(\"Accessing PHY page %d reg 0x%x\\n\", page, reg);\n+\n+\t/* Write the Wakeup register page offset value using opcode 0x11 */\n+\tret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);\n+\tif (ret_val) {\n+\t\tDEBUGOUT1(\"Could not write address opcode to page %d\\n\", page);\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (read) {\n+\t\t/* Read the Wakeup register page value using opcode 0x12 */\n+\t\tret_val = igc_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,\n+\t\t\t\t\t\t  data);\n+\t} else {\n+\t\t/* Write the Wakeup register page value using opcode 0x12 */\n+\t\tret_val = igc_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,\n+\t\t\t\t\t\t   *data);\n+\t}\n+\n+\tif (ret_val) {\n+\t\tDEBUGOUT2(\"Could not access PHY reg %d.%d\\n\", page, reg);\n+\t\treturn ret_val;\n+\t}\n+\n+\tif (!page_set)\n+\t\tret_val = igc_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * igc_power_up_phy_copper - Restore copper link in case of PHY power down\n+ * @hw: pointer to the HW structure\n+ *\n+ * In the case of a PHY power down to save power, or to turn off link during a\n+ * driver unload, or wake on lan is not enabled, restore the link to previous\n+ * settings.\n+ **/\n+void igc_power_up_phy_copper(struct igc_hw *hw)\n+{\n+\tu16 mii_reg = 0;\n+\n+\t/* The PHY will retain its settings across a power down/up cycle */\n+\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n+\tmii_reg &= ~MII_CR_POWER_DOWN;\n+\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n+}\n+\n+/**\n+ * igc_power_down_phy_copper - Restore copper link in case of PHY power down\n+ * @hw: pointer to the HW structure\n+ *\n+ * In the case of a PHY power down to save power, or to turn off link during a\n+ * driver unload, or wake on lan is not enabled, restore the link to previous\n+ * settings.\n+ **/\n+void igc_power_down_phy_copper(struct igc_hw *hw)\n+{\n+\tu16 mii_reg = 0;\n+\n+\t/* The PHY will retain its settings across a power down/up cycle */\n+\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n+\tmii_reg |= MII_CR_POWER_DOWN;\n+\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n+\tmsec_delay(1);\n+}\n+\n+/**\n+ *  __igc_read_phy_reg_hv -  Read HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *  @locked: semaphore has already been acquired or not\n+ *  @page_set: BM_WUC_PAGE already set and access enabled\n+ *\n+ *  Acquires semaphore, if necessary, then reads the PHY register at offset\n+ *  and stores the retrieved information in data.  Release any acquired\n+ *  semaphore before exiting.\n+ **/\n+static s32 __igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data,\n+\t\t\t\t   bool locked, bool page_set)\n+{\n+\ts32 ret_val;\n+\tu16 page = BM_PHY_REG_PAGE(offset);\n+\tu16 reg = BM_PHY_REG_NUM(offset);\n+\tu32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);\n+\n+\tDEBUGFUNC(\"__igc_read_phy_reg_hv\");\n+\n+\tif (!locked) {\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,\n+\t\t\t\t\t\t\t true, page_set);\n+\t\tgoto out;\n+\t}\n+\n+\tif (page > 0 && page < HV_INTC_FC_PAGE_START) {\n+\t\tret_val = igc_access_phy_debug_regs_hv(hw, offset,\n+\t\t\t\t\t\t\t data, true);\n+\t\tgoto out;\n+\t}\n+\n+\tif (!page_set) {\n+\t\tif (page == HV_INTC_FC_PAGE_START)\n+\t\t\tpage = 0;\n+\n+\t\tif (reg > MAX_PHY_MULTI_PAGE_REG) {\n+\t\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\t\tret_val = igc_set_page_igp(hw,\n+\t\t\t\t\t\t     (page << IGP_PAGE_SHIFT));\n+\n+\t\t\thw->phy.addr = phy_addr;\n+\n+\t\t\tif (ret_val)\n+\t\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\tDEBUGOUT3(\"reading PHY page %d (or 0x%x shifted) reg 0x%x\\n\", page,\n+\t\t  page << IGP_PAGE_SHIFT, reg);\n+\n+\tret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,\n+\t\t\t\t\t  data);\n+out:\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_hv -  Read HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Acquires semaphore then reads the PHY register at offset and stores\n+ *  the retrieved information in data.  Release the acquired semaphore\n+ *  before exiting.\n+ **/\n+s32 igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_phy_reg_hv(hw, offset, data, false, false);\n+}\n+\n+/**\n+ *  igc_read_phy_reg_hv_locked -  Read HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the PHY register at offset and stores the retrieved information\n+ *  in data.  Assumes semaphore already acquired.\n+ **/\n+s32 igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_phy_reg_hv(hw, offset, data, true, false);\n+}\n+\n+/**\n+ *  igc_read_phy_reg_page_hv - Read HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Reads the PHY register at offset and stores the retrieved information\n+ *  in data.  Assumes semaphore already acquired and page already set.\n+ **/\n+s32 igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn __igc_read_phy_reg_hv(hw, offset, data, true, true);\n+}\n+\n+/**\n+ *  __igc_write_phy_reg_hv - Write HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *  @locked: semaphore has already been acquired or not\n+ *  @page_set: BM_WUC_PAGE already set and access enabled\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+static s32 __igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data,\n+\t\t\t\t    bool locked, bool page_set)\n+{\n+\ts32 ret_val;\n+\tu16 page = BM_PHY_REG_PAGE(offset);\n+\tu16 reg = BM_PHY_REG_NUM(offset);\n+\tu32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);\n+\n+\tDEBUGFUNC(\"__igc_write_phy_reg_hv\");\n+\n+\tif (!locked) {\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t}\n+\t/* Page 800 works differently than the rest so it has its own func */\n+\tif (page == BM_WUC_PAGE) {\n+\t\tret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,\n+\t\t\t\t\t\t\t false, page_set);\n+\t\tgoto out;\n+\t}\n+\n+\tif (page > 0 && page < HV_INTC_FC_PAGE_START) {\n+\t\tret_val = igc_access_phy_debug_regs_hv(hw, offset,\n+\t\t\t\t\t\t\t &data, false);\n+\t\tgoto out;\n+\t}\n+\n+\tif (!page_set) {\n+\t\tif (page == HV_INTC_FC_PAGE_START)\n+\t\t\tpage = 0;\n+\n+\t\t/*\n+\t\t * Workaround MDIO accesses being disabled after entering IEEE\n+\t\t * Power Down (when bit 11 of the PHY Control register is set)\n+\t\t */\n+\t\tif (hw->phy.type == igc_phy_82578 &&\n+\t\t\t\thw->phy.revision >= 1 &&\n+\t\t\t\thw->phy.addr == 2 &&\n+\t\t\t\t!(MAX_PHY_REG_ADDRESS & reg) &&\n+\t\t\t\t(data & (1 << 11))) {\n+\t\t\tu16 data2 = 0x7EFF;\n+\t\t\tret_val = igc_access_phy_debug_regs_hv(hw,\n+\t\t\t\t\t\t\t\t(1 << 6) | 0x3,\n+\t\t\t\t\t\t\t\t&data2, false);\n+\t\t\tif (ret_val)\n+\t\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (reg > MAX_PHY_MULTI_PAGE_REG) {\n+\t\t\t/* Page is shifted left, PHY expects (page x 32) */\n+\t\t\tret_val = igc_set_page_igp(hw,\n+\t\t\t\t\t\t     (page << IGP_PAGE_SHIFT));\n+\n+\t\t\thw->phy.addr = phy_addr;\n+\n+\t\t\tif (ret_val)\n+\t\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\tDEBUGOUT3(\"writing PHY page %d (or 0x%x shifted) reg 0x%x\\n\", page,\n+\t\t  page << IGP_PAGE_SHIFT, reg);\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,\n+\t\t\t\t\t   data);\n+\n+out:\n+\tif (!locked)\n+\t\thw->phy.ops.release(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_hv - Write HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore then writes the data to PHY register at the offset.\n+ *  Release the acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_phy_reg_hv(hw, offset, data, false, false);\n+}\n+\n+/**\n+ *  igc_write_phy_reg_hv_locked - Write HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Writes the data to PHY register at the offset.  Assumes semaphore\n+ *  already acquired.\n+ **/\n+s32 igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_phy_reg_hv(hw, offset, data, true, false);\n+}\n+\n+/**\n+ *  igc_write_phy_reg_page_hv - Write HV PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Writes the data to PHY register at the offset.  Assumes semaphore\n+ *  already acquired and page already set.\n+ **/\n+s32 igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\treturn __igc_write_phy_reg_hv(hw, offset, data, true, true);\n+}\n+\n+/**\n+ *  igc_get_phy_addr_for_hv_page - Get PHY adrress based on page\n+ *  @page: page to be accessed\n+ **/\n+static u32 igc_get_phy_addr_for_hv_page(u32 page)\n+{\n+\tu32 phy_addr = 2;\n+\n+\tif (page >= HV_INTC_FC_PAGE_START)\n+\t\tphy_addr = 1;\n+\n+\treturn phy_addr;\n+}\n+\n+/**\n+ * igc_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers\n+ * @hw: pointer to the HW structure\n+ * @offset: register offset to be read or written\n+ * @data: pointer to the data to be read or written\n+ * @read: determines if operation is read or write\n+ *\n+ * Reads the PHY register at offset and stores the retrieved information\n+ * in data.  Assumes semaphore already acquired.  Note that the procedure\n+ * to access these regs uses the address port and data port to read/write.\n+ * These accesses done with PHY address 2 and without using pages.\n+ **/\n+static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,\n+\t\t\t\t\t  u16 *data, bool read)\n+{\n+\ts32 ret_val;\n+\tu32 addr_reg;\n+\tu32 data_reg;\n+\n+\tDEBUGFUNC(\"igc_access_phy_debug_regs_hv\");\n+\n+\t/* This takes care of the difference with desktop vs mobile phy */\n+\taddr_reg = ((hw->phy.type == igc_phy_82578) ?\n+\t\t    I82578_ADDR_REG : I82577_ADDR_REG);\n+\tdata_reg = addr_reg + 1;\n+\n+\t/* All operations in this function are phy address 2 */\n+\thw->phy.addr = 2;\n+\n+\t/* masking with 0x3F to remove the page from offset */\n+\tret_val = igc_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Could not write the Address Offset port register\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* Read or write the data value next */\n+\tif (read)\n+\t\tret_val = igc_read_phy_reg_mdic(hw, data_reg, data);\n+\telse\n+\t\tret_val = igc_write_phy_reg_mdic(hw, data_reg, *data);\n+\n+\tif (ret_val)\n+\t\tDEBUGOUT(\"Could not access the Data port register\\n\");\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_link_stall_workaround_hv - Si workaround\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  This function works around a Si bug where the link partner can get\n+ *  a link up indication before the PHY does.  If small packets are sent\n+ *  by the link partner they can be placed in the packet buffer without\n+ *  being properly accounted for by the PHY and will stall preventing\n+ *  further packets from being received.  The workaround is to clear the\n+ *  packet buffer after the PHY detects link up.\n+ **/\n+s32 igc_link_stall_workaround_hv(struct igc_hw *hw)\n+{\n+\ts32 ret_val = IGC_SUCCESS;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_link_stall_workaround_hv\");\n+\n+\tif (hw->phy.type != igc_phy_82578)\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* Do not apply workaround if in PHY loopback bit 14 set */\n+\thw->phy.ops.read_reg(hw, PHY_CONTROL, &data);\n+\tif (data & PHY_CONTROL_LB)\n+\t\treturn IGC_SUCCESS;\n+\n+\t/* check if link is up and at 1Gbps */\n+\tret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tdata &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |\n+\t\t BM_CS_STATUS_SPEED_MASK);\n+\n+\tif (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |\n+\t\t     BM_CS_STATUS_SPEED_1000))\n+\t\treturn IGC_SUCCESS;\n+\n+\tmsec_delay(200);\n+\n+\t/* flush the packets in the fifo buffer */\n+\tret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,\n+\t\t\t\t\t(HV_MUX_DATA_CTRL_GEN_TO_MAC |\n+\t\t\t\t\t HV_MUX_DATA_CTRL_FORCE_SPEED));\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treturn hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,\n+\t\t\t\t     HV_MUX_DATA_CTRL_GEN_TO_MAC);\n+}\n+\n+/**\n+ *  igc_check_polarity_82577 - Checks the polarity.\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Success returns 0, Failure returns -IGC_ERR_PHY (-2)\n+ *\n+ *  Polarity is determined based on the PHY specific status register.\n+ **/\n+s32 igc_check_polarity_82577(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\n+\tDEBUGFUNC(\"igc_check_polarity_82577\");\n+\n+\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n+\n+\tif (!ret_val)\n+\t\tphy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)\n+\t\t\t\t       ? igc_rev_polarity_reversed\n+\t\t\t\t       : igc_rev_polarity_normal);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Calls the PHY setup function to force speed and duplex.\n+ **/\n+s32 igc_phy_force_speed_duplex_82577(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data;\n+\tbool link = false;\n+\n+\tDEBUGFUNC(\"igc_phy_force_speed_duplex_82577\");\n+\n+\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tigc_phy_force_speed_duplex_setup(hw, &phy_data);\n+\n+\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tusec_delay(1);\n+\n+\tif (phy->autoneg_wait_to_complete) {\n+\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on 82577 phy\\n\");\n+\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tif (!link)\n+\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n+\n+\t\t/* Try once more */\n+\t\tret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n+\t\t\t\t\t\t     100000, &link);\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_get_phy_info_82577 - Retrieve I82577 PHY information\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Read PHY status to determine if link is up.  If link is up, then\n+ *  set/determine 10base-T extended distance and polarity correction.  Read\n+ *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,\n+ *  determine on the cable length, local and remote receiver.\n+ **/\n+s32 igc_get_phy_info_82577(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 data;\n+\tbool link;\n+\n+\tDEBUGFUNC(\"igc_get_phy_info_82577\");\n+\n+\tret_val = igc_phy_has_link_generic(hw, 1, 0, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (!link) {\n+\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n+\t\treturn -IGC_ERR_CONFIG;\n+\t}\n+\n+\tphy->polarity_correction = true;\n+\n+\tret_val = igc_check_polarity_82577(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tphy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);\n+\n+\tif ((data & I82577_PHY_STATUS2_SPEED_MASK) ==\n+\t    I82577_PHY_STATUS2_SPEED_1000MBPS) {\n+\t\tret_val = hw->phy.ops.get_cable_length(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\n+\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n+\t\t\t\t? igc_1000t_rx_status_ok\n+\t\t\t\t: igc_1000t_rx_status_not_ok;\n+\n+\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n+\t\t\t\t ? igc_1000t_rx_status_ok\n+\t\t\t\t : igc_1000t_rx_status_not_ok;\n+\t} else {\n+\t\tphy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;\n+\t\tphy->local_rx = igc_1000t_rx_status_undefined;\n+\t\tphy->remote_rx = igc_1000t_rx_status_undefined;\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_get_cable_length_82577 - Determine cable length for 82577 PHY\n+ *  @hw: pointer to the HW structure\n+ *\n+ * Reads the diagnostic status register and verifies result is valid before\n+ * placing it in the phy_cable_length field.\n+ **/\n+s32 igc_get_cable_length_82577(struct igc_hw *hw)\n+{\n+\tstruct igc_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu16 phy_data, length;\n+\n+\tDEBUGFUNC(\"igc_get_cable_length_82577\");\n+\n+\tret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tlength = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>\n+\t\t  I82577_DSTATUS_CABLE_LENGTH_SHIFT);\n+\n+\tif (length == IGC_CABLE_LENGTH_UNDEFINED)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\tphy->cable_length = length;\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_gs40g - Write GS40G  PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\ts32 ret_val;\n+\tu16 page = offset >> GS40G_PAGE_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_gs40g\");\n+\n+\toffset = offset & GS40G_OFFSET_MASK;\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n+\tif (ret_val)\n+\t\tgoto release;\n+\tret_val = igc_write_phy_reg_mdic(hw, offset, data);\n+\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_gs40g - Read GS40G  PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: lower half is register offset to read to\n+ *     upper half is page to use.\n+ *  @data: data to read at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then reads the data in the PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\ts32 ret_val;\n+\tu16 page = offset >> GS40G_PAGE_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_gs40g\");\n+\n+\toffset = offset & GS40G_OFFSET_MASK;\n+\tret_val = hw->phy.ops.acquire(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n+\tif (ret_val)\n+\t\tgoto release;\n+\tret_val = igc_read_phy_reg_mdic(hw, offset, data);\n+\n+release:\n+\thw->phy.ops.release(hw);\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_gpy - Write GPY PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: register offset to write to\n+ *  @data: data to write at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then writes the data to PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)\n+{\n+\ts32 ret_val;\n+\tu8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_gpy\");\n+\n+\toffset = offset & GPY_REG_MASK;\n+\n+\tif (!dev_addr) {\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tret_val = igc_write_phy_reg_mdic(hw, offset, data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\thw->phy.ops.release(hw);\n+\t} else {\n+\t\tret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,\n+\t\t\t\t\t\tdata);\n+\t}\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_gpy - Read GPY PHY register\n+ *  @hw: pointer to the HW structure\n+ *  @offset: lower half is register offset to read to\n+ *     upper half is MMD to use.\n+ *  @data: data to read at register offset\n+ *\n+ *  Acquires semaphore, if necessary, then reads the data in the PHY register\n+ *  at the offset.  Release any acquired semaphores before exiting.\n+ **/\n+s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)\n+{\n+\ts32 ret_val;\n+\tu8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_gpy\");\n+\n+\toffset = offset & GPY_REG_MASK;\n+\n+\tif (!dev_addr) {\n+\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tret_val = igc_read_phy_reg_mdic(hw, offset, data);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\thw->phy.ops.release(hw);\n+\t} else {\n+\t\tret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,\n+\t\t\t\t\t       data);\n+\t}\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_phy_reg_mphy - Read mPHY control register\n+ *  @hw: pointer to the HW structure\n+ *  @address: address to be read\n+ *  @data: pointer to the read data\n+ *\n+ *  Reads the mPHY control register in the PHY at offset and stores the\n+ *  information read to data.\n+ **/\n+s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data)\n+{\n+\tu32 mphy_ctrl = 0;\n+\tbool locked = false;\n+\tbool ready;\n+\n+\tDEBUGFUNC(\"igc_read_phy_reg_mphy\");\n+\n+\t/* Check if mPHY is ready to read/write operations */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\t/* Check if mPHY access is disabled and enable it if so */\n+\tmphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);\n+\tif (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {\n+\t\tlocked = true;\n+\t\tready = igc_is_mphy_ready(hw);\n+\t\tif (!ready)\n+\t\t\treturn -IGC_ERR_PHY;\n+\t\tmphy_ctrl |= IGC_MPHY_ENA_ACCESS;\n+\t\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);\n+\t}\n+\n+\t/* Set the address that we want to read */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\t/* We mask address, because we want to use only current lane */\n+\tmphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK &\n+\t\t~IGC_MPHY_ADDRESS_FNC_OVERRIDE) |\n+\t\t(address & IGC_MPHY_ADDRESS_MASK);\n+\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);\n+\n+\t/* Read data from the address */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\t*data = IGC_READ_REG(hw, IGC_MPHY_DATA);\n+\n+\t/* Disable access to mPHY if it was originally disabled */\n+\tif (locked)\n+\t\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,\n+\t\t\tIGC_MPHY_DIS_ACCESS);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_write_phy_reg_mphy - Write mPHY control register\n+ *  @hw: pointer to the HW structure\n+ *  @address: address to write to\n+ *  @data: data to write to register at offset\n+ *  @line_override: used when we want to use different line than default one\n+ *\n+ *  Writes data to mPHY control register.\n+ **/\n+s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,\n+\t\t\t     bool line_override)\n+{\n+\tu32 mphy_ctrl = 0;\n+\tbool locked = false;\n+\tbool ready;\n+\n+\tDEBUGFUNC(\"igc_write_phy_reg_mphy\");\n+\n+\t/* Check if mPHY is ready to read/write operations */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\t/* Check if mPHY access is disabled and enable it if so */\n+\tmphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);\n+\tif (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {\n+\t\tlocked = true;\n+\t\tready = igc_is_mphy_ready(hw);\n+\t\tif (!ready)\n+\t\t\treturn -IGC_ERR_PHY;\n+\t\tmphy_ctrl |= IGC_MPHY_ENA_ACCESS;\n+\t\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);\n+\t}\n+\n+\t/* Set the address that we want to read */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\n+\t/* We mask address, because we want to use only current lane */\n+\tif (line_override)\n+\t\tmphy_ctrl |= IGC_MPHY_ADDRESS_FNC_OVERRIDE;\n+\telse\n+\t\tmphy_ctrl &= ~IGC_MPHY_ADDRESS_FNC_OVERRIDE;\n+\tmphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK) |\n+\t\t(address & IGC_MPHY_ADDRESS_MASK);\n+\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);\n+\n+\t/* Read data from the address */\n+\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\tIGC_WRITE_REG(hw, IGC_MPHY_DATA, data);\n+\n+\t/* Disable access to mPHY if it was originally disabled */\n+\tif (locked)\n+\t\tready = igc_is_mphy_ready(hw);\n+\tif (!ready)\n+\t\treturn -IGC_ERR_PHY;\n+\tIGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,\n+\t\t\tIGC_MPHY_DIS_ACCESS);\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n+/**\n+ *  igc_is_mphy_ready - Check if mPHY control register is not busy\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  Returns mPHY control register status.\n+ **/\n+bool igc_is_mphy_ready(struct igc_hw *hw)\n+{\n+\tu16 retry_count = 0;\n+\tu32 mphy_ctrl = 0;\n+\tbool ready = false;\n+\n+\twhile (retry_count < 2) {\n+\t\tmphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);\n+\t\tif (mphy_ctrl & IGC_MPHY_BUSY) {\n+\t\t\tusec_delay(20);\n+\t\t\tretry_count++;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tready = true;\n+\t\tbreak;\n+\t}\n+\n+\tif (!ready)\n+\t\tDEBUGOUT(\"ERROR READING mPHY control register, phy is busy.\\n\");\n+\n+\treturn ready;\n+}\n+\n+/**\n+ *  __igc_access_xmdio_reg - Read/write XMDIO register\n+ *  @hw: pointer to the HW structure\n+ *  @address: XMDIO address to program\n+ *  @dev_addr: device address to program\n+ *  @data: pointer to value to read/write from/to the XMDIO address\n+ *  @read: boolean flag to indicate read or write\n+ **/\n+static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,\n+\t\t\t\t    u8 dev_addr, u16 *data, bool read)\n+{\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"__igc_access_xmdio_reg\");\n+\n+\tret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |\n+\t\t\t\t\tdev_addr);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\tif (read)\n+\t\tret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);\n+\telse\n+\t\tret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Recalibrate the device back to 0 */\n+\tret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  igc_read_xmdio_reg - Read XMDIO register\n+ *  @hw: pointer to the HW structure\n+ *  @addr: XMDIO address to program\n+ *  @dev_addr: device address to program\n+ *  @data: value to be read from the EMI address\n+ **/\n+s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)\n+{\n+\tDEBUGFUNC(\"igc_read_xmdio_reg\");\n+\n+\treturn __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);\n+}\n+\n+/**\n+ *  igc_write_xmdio_reg - Write XMDIO register\n+ *  @hw: pointer to the HW structure\n+ *  @addr: XMDIO address to program\n+ *  @dev_addr: device address to program\n+ *  @data: value to be written to the XMDIO address\n+ **/\n+s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)\n+{\n+\tDEBUGFUNC(\"igc_write_xmdio_reg\");\n+\n+\treturn __igc_access_xmdio_reg(hw, addr, dev_addr, &data,\n+\t\t\t\tfalse);\n+}\ndiff --git a/drivers/net/igc/base/e1000_phy.h b/drivers/net/igc/base/e1000_phy.h\nnew file mode 100644\nindex 0000000..5fae598\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_phy.h\n@@ -0,0 +1,337 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_PHY_H_\n+#define _IGC_PHY_H_\n+\n+void igc_init_phy_ops_generic(struct igc_hw *hw);\n+s32  igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);\n+void igc_null_phy_generic(struct igc_hw *hw);\n+s32  igc_null_lplu_state(struct igc_hw *hw, bool active);\n+s32  igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_null_set_page(struct igc_hw *hw, u16 data);\n+s32 igc_read_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t     u8 dev_addr, u8 *data);\n+s32 igc_write_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,\n+\t\t\t      u8 dev_addr, u8 data);\n+s32  igc_check_downshift_generic(struct igc_hw *hw);\n+s32  igc_check_polarity_m88(struct igc_hw *hw);\n+s32  igc_check_polarity_igp(struct igc_hw *hw);\n+s32  igc_check_polarity_ife(struct igc_hw *hw);\n+s32  igc_check_reset_block_generic(struct igc_hw *hw);\n+s32  igc_phy_setup_autoneg(struct igc_hw *hw);\n+s32  igc_copper_link_autoneg(struct igc_hw *hw);\n+s32  igc_copper_link_setup_igp(struct igc_hw *hw);\n+s32  igc_copper_link_setup_m88(struct igc_hw *hw);\n+s32  igc_copper_link_setup_m88_gen2(struct igc_hw *hw);\n+s32  igc_phy_force_speed_duplex_igp(struct igc_hw *hw);\n+s32  igc_phy_force_speed_duplex_m88(struct igc_hw *hw);\n+s32  igc_phy_force_speed_duplex_ife(struct igc_hw *hw);\n+s32  igc_get_cable_length_m88(struct igc_hw *hw);\n+s32  igc_get_cable_length_m88_gen2(struct igc_hw *hw);\n+s32  igc_get_cable_length_igp_2(struct igc_hw *hw);\n+s32  igc_get_cfg_done_generic(struct igc_hw *hw);\n+s32  igc_get_phy_id(struct igc_hw *hw);\n+s32  igc_get_phy_info_igp(struct igc_hw *hw);\n+s32  igc_get_phy_info_m88(struct igc_hw *hw);\n+s32  igc_get_phy_info_ife(struct igc_hw *hw);\n+s32  igc_phy_sw_reset_generic(struct igc_hw *hw);\n+void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);\n+s32  igc_phy_hw_reset_generic(struct igc_hw *hw);\n+s32  igc_phy_reset_dsp_generic(struct igc_hw *hw);\n+s32  igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_set_page_igp(struct igc_hw *hw, u16 page);\n+s32  igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);\n+s32  igc_setup_copper_link_generic(struct igc_hw *hw);\n+s32  igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,\n+\t\t\t\tu32 usec_interval, bool *success);\n+s32  igc_phy_init_script_igp3(struct igc_hw *hw);\n+enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);\n+s32  igc_determine_phy_address(struct igc_hw *hw);\n+s32  igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);\n+s32  igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);\n+s32  igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data);\n+void igc_power_up_phy_copper(struct igc_hw *hw);\n+void igc_power_down_phy_copper(struct igc_hw *hw);\n+s32  igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data);\n+s32  igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data);\n+s32  igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_link_stall_workaround_hv(struct igc_hw *hw);\n+s32  igc_copper_link_setup_82577(struct igc_hw *hw);\n+s32  igc_check_polarity_82577(struct igc_hw *hw);\n+s32  igc_get_phy_info_82577(struct igc_hw *hw);\n+s32  igc_phy_force_speed_duplex_82577(struct igc_hw *hw);\n+s32  igc_get_cable_length_82577(struct igc_hw *hw);\n+s32  igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data);\n+s32  igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);\n+s32  igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);\n+s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data);\n+s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,\n+\t\t\t     bool line_override);\n+bool igc_is_mphy_ready(struct igc_hw *hw);\n+\n+s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,\n+\t\t\t u16 *data);\n+s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,\n+\t\t\t  u16 data);\n+\n+#define IGC_MAX_PHY_ADDR\t\t8\n+\n+/* IGP01E1000 Specific Registers */\n+#define IGP01IGC_PHY_PORT_CONFIG\t0x10 /* Port Config */\n+#define IGP01IGC_PHY_PORT_STATUS\t0x11 /* Status */\n+#define IGP01IGC_PHY_PORT_CTRL\t0x12 /* Control */\n+#define IGP01IGC_PHY_LINK_HEALTH\t0x13 /* PHY Link Health */\n+#define IGP01IGC_GMII_FIFO\t\t0x14 /* GMII FIFO */\n+#define IGP02IGC_PHY_POWER_MGMT\t0x19 /* Power Management */\n+#define IGP01IGC_PHY_PAGE_SELECT\t0x1F /* Page Select */\n+#define BM_PHY_PAGE_SELECT\t\t22   /* Page Select for BM */\n+#define IGP_PAGE_SHIFT\t\t\t5\n+#define PHY_REG_MASK\t\t\t0x1F\n+\n+/* GS40G - I210 PHY defines */\n+#define GS40G_PAGE_SELECT\t\t0x16\n+#define GS40G_PAGE_SHIFT\t\t16\n+#define GS40G_OFFSET_MASK\t\t0xFFFF\n+#define GS40G_PAGE_2\t\t\t0x20000\n+#define GS40G_MAC_REG2\t\t\t0x15\n+#define GS40G_MAC_LB\t\t\t0x4140\n+#define GS40G_MAC_SPEED_1G\t\t0X0006\n+#define GS40G_COPPER_SPEC\t\t0x0010\n+\n+#define IGC_I225_PHPM\t\t\t0x0E14 /* I225 PHY Power Management */\n+#define IGC_I225_PHPM_DIS_1000_D3\t0x0008 /* Disable 1G in D3 */\n+#define IGC_I225_PHPM_LINK_ENERGY\t0x0010 /* Link Energy Detect */\n+#define IGC_I225_PHPM_GO_LINKD\t0x0020 /* Go Link Disconnect */\n+#define IGC_I225_PHPM_DIS_1000\t0x0040 /* Disable 1G globally */\n+#define IGC_I225_PHPM_SPD_B2B_EN\t0x0080 /* Smart Power Down Back2Back */\n+#define IGC_I225_PHPM_RST_COMPL\t0x0100 /* PHY Reset Completed */\n+#define IGC_I225_PHPM_DIS_100_D3\t0x0200 /* Disable 100M in D3 */\n+#define IGC_I225_PHPM_ULP\t\t0x0400 /* Ultra Low-Power Mode */\n+#define IGC_I225_PHPM_DIS_2500\t0x0800 /* Disable 2.5G globally */\n+#define IGC_I225_PHPM_DIS_2500_D3\t0x1000 /* Disable 2.5G in D3 */\n+/* GPY211 - I225 defines */\n+#define GPY_MMD_MASK\t\t\t0xFFFF0000\n+#define GPY_MMD_SHIFT\t\t\t16\n+#define GPY_REG_MASK\t\t\t0x0000FFFF\n+/* BM/HV Specific Registers */\n+#define BM_PORT_CTRL_PAGE\t\t769\n+#define BM_WUC_PAGE\t\t\t800\n+#define BM_WUC_ADDRESS_OPCODE\t\t0x11\n+#define BM_WUC_DATA_OPCODE\t\t0x12\n+#define BM_WUC_ENABLE_PAGE\t\tBM_PORT_CTRL_PAGE\n+#define BM_WUC_ENABLE_REG\t\t17\n+#define BM_WUC_ENABLE_BIT\t\t(1 << 2)\n+#define BM_WUC_HOST_WU_BIT\t\t(1 << 4)\n+#define BM_WUC_ME_WU_BIT\t\t(1 << 5)\n+\n+#define PHY_UPPER_SHIFT\t\t\t21\n+\n+#define BM_PHY_REG(page, reg)\t(\t\\\n+\t__extension__ ({\t\t\\\n+\t\ttypeof(page) _page = (page);\t\\\n+\t\ttypeof(reg) _reg = (reg);\t\\\n+\t\t(_reg & MAX_PHY_REG_ADDRESS) |\t\\\n+\t\t((_page & 0xFFFF) << PHY_PAGE_SHIFT) |\t\\\n+\t\t((_reg & ~MAX_PHY_REG_ADDRESS) <<\t\\\n+\t\t(PHY_UPPER_SHIFT - PHY_PAGE_SHIFT));\t\\\n+\t}))\n+\n+#define BM_PHY_REG_PAGE(offset) \\\n+\t((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))\n+\n+#define BM_PHY_REG_NUM(offset)\t(\t\\\n+\t__extension__ ({\t\t\\\n+\t\ttypeof(offset) _offset = (offset);\t\\\n+\t\t(u16)((_offset & MAX_PHY_REG_ADDRESS) |\t\\\n+\t\t((_offset >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\t\\\n+\t\t~MAX_PHY_REG_ADDRESS));\t\t\t\\\n+\t}))\n+\n+#define HV_INTC_FC_PAGE_START\t\t768\n+#define I82578_ADDR_REG\t\t\t29\n+#define I82577_ADDR_REG\t\t\t16\n+#define I82577_CFG_REG\t\t\t22\n+#define I82577_CFG_ASSERT_CRS_ON_TX\t(1 << 15)\n+#define I82577_CFG_ENABLE_DOWNSHIFT\t(3 << 10) /* auto downshift */\n+#define I82577_CTRL_REG\t\t\t23\n+\n+/* 82577 specific PHY registers */\n+#define I82577_PHY_CTRL_2\t\t18\n+#define I82577_PHY_LBK_CTRL\t\t19\n+#define I82577_PHY_STATUS_2\t\t26\n+#define I82577_PHY_DIAG_STATUS\t\t31\n+\n+/* I82577 PHY Status 2 */\n+#define I82577_PHY_STATUS2_REV_POLARITY\t\t0x0400\n+#define I82577_PHY_STATUS2_MDIX\t\t\t0x0800\n+#define I82577_PHY_STATUS2_SPEED_MASK\t\t0x0300\n+#define I82577_PHY_STATUS2_SPEED_1000MBPS\t0x0200\n+\n+/* I82577 PHY Control 2 */\n+#define I82577_PHY_CTRL2_MANUAL_MDIX\t\t0x0200\n+#define I82577_PHY_CTRL2_AUTO_MDI_MDIX\t\t0x0400\n+#define I82577_PHY_CTRL2_MDIX_CFG_MASK\t\t0x0600\n+\n+/* I82577 PHY Diagnostics Status */\n+#define I82577_DSTATUS_CABLE_LENGTH\t\t0x03FC\n+#define I82577_DSTATUS_CABLE_LENGTH_SHIFT\t2\n+\n+/* 82580 PHY Power Management */\n+#define IGC_82580_PHY_POWER_MGMT\t0xE14\n+#define IGC_82580_PM_SPD\t\t0x0001 /* Smart Power Down */\n+#define IGC_82580_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n+#define IGC_82580_PM_D3_LPLU\t\t0x0004 /* For all other states */\n+#define IGC_82580_PM_GO_LINKD\t\t0x0020 /* Go Link Disconnect */\n+\n+#define IGC_MPHY_DIS_ACCESS\t\t0x80000000 /* disable_access bit */\n+#define IGC_MPHY_ENA_ACCESS\t\t0x40000000 /* enable_access bit */\n+#define IGC_MPHY_BUSY\t\t\t0x00010000 /* busy bit */\n+#define IGC_MPHY_ADDRESS_FNC_OVERRIDE\t0x20000000 /* fnc_override bit */\n+#define IGC_MPHY_ADDRESS_MASK\t\t0x0000FFFF /* address mask */\n+\n+/* BM PHY Copper Specific Control 1 */\n+#define BM_CS_CTRL1\t\t\t16\n+\n+/* BM PHY Copper Specific Status */\n+#define BM_CS_STATUS\t\t\t17\n+#define BM_CS_STATUS_LINK_UP\t\t0x0400\n+#define BM_CS_STATUS_RESOLVED\t\t0x0800\n+#define BM_CS_STATUS_SPEED_MASK\t\t0xC000\n+#define BM_CS_STATUS_SPEED_1000\t\t0x8000\n+\n+/* 82577 Mobile Phy Status Register */\n+#define HV_M_STATUS\t\t\t26\n+#define HV_M_STATUS_AUTONEG_COMPLETE\t0x1000\n+#define HV_M_STATUS_SPEED_MASK\t\t0x0300\n+#define HV_M_STATUS_SPEED_1000\t\t0x0200\n+#define HV_M_STATUS_SPEED_100\t\t0x0100\n+#define HV_M_STATUS_LINK_UP\t\t0x0040\n+\n+#define IGP01IGC_PHY_PCS_INIT_REG\t0x00B4\n+#define IGP01IGC_PHY_POLARITY_MASK\t0x0078\n+\n+#define IGP01IGC_PSCR_AUTO_MDIX\t0x1000\n+#define IGP01IGC_PSCR_FORCE_MDI_MDIX\t0x2000 /* 0=MDI, 1=MDIX */\n+\n+#define IGP01IGC_PSCFR_SMART_SPEED\t0x0080\n+\n+/* Enable flexible speed on link-up */\n+#define IGP01IGC_GMII_FLEX_SPD\t0x0010\n+#define IGP01IGC_GMII_SPD\t\t0x0020 /* Enable SPD */\n+\n+#define IGP02IGC_PM_SPD\t\t0x0001 /* Smart Power Down */\n+#define IGP02IGC_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n+#define IGP02IGC_PM_D3_LPLU\t\t0x0004 /* For all other states */\n+\n+#define IGP01IGC_PLHR_SS_DOWNGRADE\t0x8000\n+\n+#define IGP01IGC_PSSR_POLARITY_REVERSED\t0x0002\n+#define IGP01IGC_PSSR_MDIX\t\t0x0800\n+#define IGP01IGC_PSSR_SPEED_MASK\t0xC000\n+#define IGP01IGC_PSSR_SPEED_1000MBPS\t0xC000\n+\n+#define IGP02IGC_PHY_CHANNEL_NUM\t4\n+#define IGP02IGC_PHY_AGC_A\t\t0x11B1\n+#define IGP02IGC_PHY_AGC_B\t\t0x12B1\n+#define IGP02IGC_PHY_AGC_C\t\t0x14B1\n+#define IGP02IGC_PHY_AGC_D\t\t0x18B1\n+\n+#define IGP02IGC_AGC_LENGTH_SHIFT\t9   /* Course=15:13, Fine=12:9 */\n+#define IGP02IGC_AGC_LENGTH_MASK\t0x7F\n+#define IGP02IGC_AGC_RANGE\t\t15\n+\n+#define IGC_CABLE_LENGTH_UNDEFINED\t0xFF\n+\n+#define IGC_KMRNCTRLSTA_OFFSET\t0x001F0000\n+#define IGC_KMRNCTRLSTA_OFFSET_SHIFT\t16\n+#define IGC_KMRNCTRLSTA_REN\t\t0x00200000\n+#define IGC_KMRNCTRLSTA_CTRL_OFFSET\t0x1    /* Kumeran Control */\n+#define IGC_KMRNCTRLSTA_DIAG_OFFSET\t0x3    /* Kumeran Diagnostic */\n+#define IGC_KMRNCTRLSTA_TIMEOUTS\t0x4    /* Kumeran Timeouts */\n+#define IGC_KMRNCTRLSTA_INBAND_PARAM\t0x9    /* Kumeran InBand Parameters */\n+#define IGC_KMRNCTRLSTA_IBIST_DISABLE\t0x0200 /* Kumeran IBIST Disable */\n+#define IGC_KMRNCTRLSTA_DIAG_NELPBK\t0x1000 /* Nearend Loopback mode */\n+#define IGC_KMRNCTRLSTA_K1_CONFIG\t0x7\n+#define IGC_KMRNCTRLSTA_K1_ENABLE\t0x0002 /* enable K1 */\n+#define IGC_KMRNCTRLSTA_HD_CTRL\t0x10   /* Kumeran HD Control */\n+#define IGC_KMRNCTRLSTA_K0S_CTRL\t0x1E\t/* Kumeran K0s Control */\n+#define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT\t0\n+#define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT\t4\n+#define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK\t\\\n+\t(3 << IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)\n+#define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \\\n+\t(7 << IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)\n+#define IGC_KMRNCTRLSTA_OP_MODES\t0x1F   /* Kumeran Modes of Operation */\n+#define IGC_KMRNCTRLSTA_OP_MODES_LSC2CSC\t0x0002 /* change LSC to CSC */\n+\n+#define IFE_PHY_EXTENDED_STATUS_CONTROL\t0x10\n+#define IFE_PHY_SPECIAL_CONTROL\t\t0x11 /* 100BaseTx PHY Special Ctrl */\n+#define IFE_PHY_SPECIAL_CONTROL_LED\t0x1B /* PHY Special and LED Ctrl */\n+#define IFE_PHY_MDIX_CONTROL\t\t0x1C /* MDI/MDI-X Control */\n+\n+/* IFE PHY Extended Status Control */\n+#define IFE_PESC_POLARITY_REVERSED\t0x0100\n+\n+/* IFE PHY Special Control */\n+#define IFE_PSC_AUTO_POLARITY_DISABLE\t0x0010\n+#define IFE_PSC_FORCE_POLARITY\t\t0x0020\n+\n+/* IFE PHY Special Control and LED Control */\n+#define IFE_PSCL_PROBE_MODE\t\t0x0020\n+#define IFE_PSCL_PROBE_LEDS_OFF\t\t0x0006 /* Force LEDs 0 and 2 off */\n+#define IFE_PSCL_PROBE_LEDS_ON\t\t0x0007 /* Force LEDs 0 and 2 on */\n+\n+/* IFE PHY MDIX Control */\n+#define IFE_PMC_MDIX_STATUS\t\t0x0020 /* 1=MDI-X, 0=MDI */\n+#define IFE_PMC_FORCE_MDIX\t\t0x0040 /* 1=force MDI-X, 0=force MDI */\n+#define IFE_PMC_AUTO_MDIX\t\t0x0080 /* 1=enable auto, 0=disable */\n+\n+/* SFP modules ID memory locations */\n+#define IGC_SFF_IDENTIFIER_OFFSET\t0x00\n+#define IGC_SFF_IDENTIFIER_SFF\t0x02\n+#define IGC_SFF_IDENTIFIER_SFP\t0x03\n+\n+#define IGC_SFF_ETH_FLAGS_OFFSET\t0x06\n+/* Flags for SFP modules compatible with ETH up to 1Gb */\n+struct sfp_igc_flags {\n+\tu8 igc_base_sx:1;\n+\tu8 igc_base_lx:1;\n+\tu8 igc_base_cx:1;\n+\tu8 igc_base_t:1;\n+\tu8 e100_base_lx:1;\n+\tu8 e100_base_fx:1;\n+\tu8 e10_base_bx10:1;\n+\tu8 e10_base_px:1;\n+};\n+\n+/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */\n+#define IGC_SFF_VENDOR_OUI_TYCO\t0x00407600\n+#define IGC_SFF_VENDOR_OUI_FTL\t0x00906500\n+#define IGC_SFF_VENDOR_OUI_AVAGO\t0x00176A00\n+#define IGC_SFF_VENDOR_OUI_INTEL\t0x001B2100\n+\n+#endif\ndiff --git a/drivers/net/igc/base/e1000_regs.h b/drivers/net/igc/base/e1000_regs.h\nnew file mode 100644\nindex 0000000..ceffe9b\n--- /dev/null\n+++ b/drivers/net/igc/base/e1000_regs.h\n@@ -0,0 +1,724 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _IGC_REGS_H_\n+#define _IGC_REGS_H_\n+\n+/* General Register Descriptions */\n+#define IGC_CTRL\t0x00000  /* Device Control - RW */\n+#define IGC_CTRL_DUP\t0x00004  /* Device Control Duplicate (Shadow) - RW */\n+#define IGC_STATUS\t0x00008  /* Device Status - RO */\n+#define IGC_EECD\t0x00010  /* EEPROM/Flash Control - RW */\n+/* NVM  Register Descriptions */\n+#define IGC_EERD\t\t0x12014  /* EEprom mode read - RW */\n+#define IGC_EEWR\t\t0x12018  /* EEprom mode write - RW */\n+#define IGC_CTRL_EXT\t0x00018  /* Extended Device Control - RW */\n+#define IGC_MDIC\t0x00020  /* MDI Control - RW */\n+#define IGC_MDICNFG\t0x00E04  /* MDI Config - RW */\n+#define IGC_REGISTER_SET_SIZE\t\t0x20000 /* CSR Size */\n+#define IGC_EEPROM_INIT_CTRL_WORD_2\t0x0F /* EEPROM Init Ctrl Word 2 */\n+#define IGC_EEPROM_PCIE_CTRL_WORD_2\t0x28 /* EEPROM PCIe Ctrl Word 2 */\n+#define IGC_BARCTRL\t\t\t0x5BBC /* BAR ctrl reg */\n+#define IGC_BARCTRL_FLSIZE\t\t0x0700 /* BAR ctrl Flsize */\n+#define IGC_BARCTRL_CSRSIZE\t\t0x2000 /* BAR ctrl CSR size */\n+#define IGC_MPHY_ADDR_CTRL\t0x0024 /* GbE MPHY Address Control */\n+#define IGC_MPHY_DATA\t\t0x0E10 /* GBE MPHY Data */\n+#define IGC_MPHY_STAT\t\t0x0E0C /* GBE MPHY Statistics */\n+#define IGC_PPHY_CTRL\t\t0x5b48 /* PCIe PHY Control */\n+#define IGC_I350_BARCTRL\t\t0x5BFC /* BAR ctrl reg */\n+#define IGC_I350_DTXMXPKTSZ\t\t0x355C /* Maximum sent packet size reg*/\n+#define IGC_SCTL\t0x00024  /* SerDes Control - RW */\n+#define IGC_FCAL\t0x00028  /* Flow Control Address Low - RW */\n+#define IGC_FCAH\t0x0002C  /* Flow Control Address High -RW */\n+#define IGC_FEXT\t0x0002C  /* Future Extended - RW */\n+#define IGC_I225_FLSWCTL\t0x12048 /* FLASH control register */\n+#define IGC_I225_FLSWDATA\t0x1204C /* FLASH data register */\n+#define IGC_I225_FLSWCNT\t0x12050 /* FLASH Access Counter */\n+#define IGC_I225_FLSECU\t0x12114 /* FLASH Security */\n+#define IGC_FEXTNVM\t0x00028  /* Future Extended NVM - RW */\n+#define IGC_FEXTNVM3\t0x0003C  /* Future Extended NVM 3 - RW */\n+#define IGC_FEXTNVM4\t0x00024  /* Future Extended NVM 4 - RW */\n+#define IGC_FEXTNVM5\t0x00014  /* Future Extended NVM 5 - RW */\n+#define IGC_FEXTNVM6\t0x00010  /* Future Extended NVM 6 - RW */\n+#define IGC_FEXTNVM7\t0x000E4  /* Future Extended NVM 7 - RW */\n+#define IGC_FEXTNVM9\t0x5BB4  /* Future Extended NVM 9 - RW */\n+#define IGC_FEXTNVM11\t0x5BBC  /* Future Extended NVM 11 - RW */\n+#define IGC_PCIEANACFG\t0x00F18 /* PCIE Analog Config */\n+#define IGC_FCT\t0x00030  /* Flow Control Type - RW */\n+#define IGC_CONNSW\t0x00034  /* Copper/Fiber switch control - RW */\n+#define IGC_VET\t0x00038  /* VLAN Ether Type - RW */\n+#define IGC_ICR\t\t\t0x01500  /* Intr Cause Read - RC/W1C */\n+#define IGC_ITR\t0x000C4  /* Interrupt Throttling Rate - RW */\n+#define IGC_ICS\t\t\t0x01504  /* Intr Cause Set - WO */\n+#define IGC_IMS\t\t\t0x01508  /* Intr Mask Set/Read - RW */\n+#define IGC_IMC\t\t\t0x0150C  /* Intr Mask Clear - WO */\n+#define IGC_IAM\t\t\t0x01510  /* Intr Ack Auto Mask- RW */\n+#define IGC_IVAR\t0x000E4  /* Interrupt Vector Allocation Register - RW */\n+#define IGC_SVCR\t0x000F0\n+#define IGC_SVT\t0x000F4\n+#define IGC_LPIC\t0x000FC  /* Low Power IDLE control */\n+#define IGC_RCTL\t0x00100  /* Rx Control - RW */\n+#define IGC_FCTTV\t0x00170  /* Flow Control Transmit Timer Value - RW */\n+#define IGC_TXCW\t0x00178  /* Tx Configuration Word - RW */\n+#define IGC_RXCW\t0x00180  /* Rx Configuration Word - RO */\n+#define IGC_PBA_ECC\t0x01100  /* PBA ECC Register */\n+#define IGC_EICR\t0x01580  /* Ext. Interrupt Cause Read - R/clr */\n+#define IGC_EITR(_n)\t(0x01680 + (0x4 * (_n)))\n+#define IGC_EICS\t0x01520  /* Ext. Interrupt Cause Set - W0 */\n+#define IGC_EIMS\t0x01524  /* Ext. Interrupt Mask Set/Read - RW */\n+#define IGC_EIMC\t0x01528  /* Ext. Interrupt Mask Clear - WO */\n+#define IGC_EIAC\t0x0152C  /* Ext. Interrupt Auto Clear - RW */\n+#define IGC_EIAM\t0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */\n+#define IGC_GPIE\t0x01514  /* General Purpose Interrupt Enable - RW */\n+#define IGC_IVAR0\t0x01700  /* Interrupt Vector Allocation (array) - RW */\n+#define IGC_IVAR_MISC\t0x01740 /* IVAR for \"other\" causes - RW */\n+#define IGC_TCTL\t0x00400  /* Tx Control - RW */\n+#define IGC_TCTL_EXT\t0x00404  /* Extended Tx Control - RW */\n+#define IGC_TIPG\t0x00410  /* Tx Inter-packet gap -RW */\n+#define IGC_TBT\t0x00448  /* Tx Burst Timer - RW */\n+#define IGC_AIT\t0x00458  /* Adaptive Interframe Spacing Throttle - RW */\n+#define IGC_LEDCTL\t0x00E00  /* LED Control - RW */\n+#define IGC_LEDMUX\t0x08130  /* LED MUX Control */\n+#define IGC_EXTCNF_CTRL\t0x00F00  /* Extended Configuration Control */\n+#define IGC_EXTCNF_SIZE\t0x00F08  /* Extended Configuration Size */\n+#define IGC_PHY_CTRL\t0x00F10  /* PHY Control Register in CSR */\n+#define IGC_POEMB\tIGC_PHY_CTRL /* PHY OEM Bits */\n+#define IGC_PBA\t0x01000  /* Packet Buffer Allocation - RW */\n+#define IGC_PBS\t0x01008  /* Packet Buffer Size */\n+#define IGC_PBECCSTS\t0x0100C  /* Packet Buffer ECC Status - RW */\n+#define IGC_IOSFPC\t0x00F28  /* TX corrupted data  */\n+#define IGC_EEMNGCTL\t0x01010  /* MNG EEprom Control */\n+#define IGC_EEMNGCTL_I210\t0x01010  /* i210 MNG EEprom Mode Control */\n+#define IGC_EEMNGCTL_I225\t0x01010  /* i225 MNG EEprom Mode Control */\n+#define IGC_EEARBC\t0x01024  /* EEPROM Auto Read Bus Control */\n+#define IGC_EEARBC_I210\t0x12024 /* EEPROM Auto Read Bus Control */\n+#define IGC_EEARBC_I225\t0x12024 /* EEPROM Auto Read Bus Control */\n+#define IGC_FLASHT\t0x01028  /* FLASH Timer Register */\n+#define IGC_FLSWCTL\t0x01030  /* FLASH control register */\n+#define IGC_FLSWDATA\t0x01034  /* FLASH data register */\n+#define IGC_FLSWCNT\t0x01038  /* FLASH Access Counter */\n+#define IGC_FLOP\t0x0103C  /* FLASH Opcode Register */\n+#define IGC_I2CCMD\t0x01028  /* SFPI2C Command Register - RW */\n+#define IGC_I2CPARAMS\t0x0102C /* SFPI2C Parameters Register - RW */\n+#define IGC_I2CBB_EN\t0x00000100  /* I2C - Bit Bang Enable */\n+#define IGC_I2C_CLK_OUT\t0x00000200  /* I2C- Clock */\n+#define IGC_I2C_DATA_OUT\t0x00000400  /* I2C- Data Out */\n+#define IGC_I2C_DATA_OE_N\t0x00000800  /* I2C- Data Output Enable */\n+#define IGC_I2C_DATA_IN\t0x00001000  /* I2C- Data In */\n+#define IGC_I2C_CLK_OE_N\t0x00002000  /* I2C- Clock Output Enable */\n+#define IGC_I2C_CLK_IN\t0x00004000  /* I2C- Clock In */\n+#define IGC_I2C_CLK_STRETCH_DIS\t0x00008000 /* I2C- Dis Clk Stretching */\n+#define IGC_WDSTP\t0x01040  /* Watchdog Setup - RW */\n+#define IGC_SWDSTS\t0x01044  /* SW Device Status - RW */\n+#define IGC_FRTIMER\t0x01048  /* Free Running Timer - RW */\n+#define IGC_TCPTIMER\t0x0104C  /* TCP Timer - RW */\n+#define IGC_VPDDIAG\t0x01060  /* VPD Diagnostic - RO */\n+#define IGC_ICR_V2\t0x01500  /* Intr Cause - new location - RC */\n+#define IGC_ICS_V2\t0x01504  /* Intr Cause Set - new location - WO */\n+#define IGC_IMS_V2\t0x01508  /* Intr Mask Set/Read - new location - RW */\n+#define IGC_IMC_V2\t0x0150C  /* Intr Mask Clear - new location - WO */\n+#define IGC_IAM_V2\t0x01510  /* Intr Ack Auto Mask - new location - RW */\n+#define IGC_ERT\t0x02008  /* Early Rx Threshold - RW */\n+#define IGC_FCRTL\t0x02160  /* Flow Control Receive Threshold Low - RW */\n+#define IGC_FCRTH\t0x02168  /* Flow Control Receive Threshold High - RW */\n+#define IGC_PSRCTL\t0x02170  /* Packet Split Receive Control - RW */\n+#define IGC_RDFH\t0x02410  /* Rx Data FIFO Head - RW */\n+#define IGC_RDFT\t0x02418  /* Rx Data FIFO Tail - RW */\n+#define IGC_RDFHS\t0x02420  /* Rx Data FIFO Head Saved - RW */\n+#define IGC_RDFTS\t0x02428  /* Rx Data FIFO Tail Saved - RW */\n+#define IGC_RDFPC\t0x02430  /* Rx Data FIFO Packet Count - RW */\n+#define IGC_PBRTH\t0x02458  /* PB Rx Arbitration Threshold - RW */\n+#define IGC_FCRTV\t0x02460  /* Flow Control Refresh Timer Value - RW */\n+/* Split and Replication Rx Control - RW */\n+#define IGC_RDPUMB\t0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */\n+#define IGC_RDPUAD\t0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */\n+#define IGC_RDPUWD\t0x025D4  /* DMA Rx Descriptor uC Data Write - RW */\n+#define IGC_RDPURD\t0x025D8  /* DMA Rx Descriptor uC Data Read - RW */\n+#define IGC_RDPUCTL\t0x025DC  /* DMA Rx Descriptor uC Control - RW */\n+#define IGC_PBDIAG\t0x02458  /* Packet Buffer Diagnostic - RW */\n+#define IGC_RXPBS\t0x02404  /* Rx Packet Buffer Size - RW */\n+#define IGC_IRPBS\t0x02404 /* Same as RXPBS, renamed for newer Si - RW */\n+#define IGC_PBRWAC\t0x024E8 /* Rx packet buffer wrap around counter - RO */\n+#define IGC_RDTR\t0x02820  /* Rx Delay Timer - RW */\n+#define IGC_RADV\t0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */\n+#define IGC_EMIADD\t0x10     /* Extended Memory Indirect Address */\n+#define IGC_EMIDATA\t0x11     /* Extended Memory Indirect Data */\n+/* Shadow Ram Write Register - RW */\n+#define IGC_SRWR\t\t0x12018\n+#define IGC_EEC_REG\t\t0x12010\n+\n+#define IGC_I210_FLMNGCTL\t0x12038\n+#define IGC_I210_FLMNGDATA\t0x1203C\n+#define IGC_I210_FLMNGCNT\t0x12040\n+\n+#define IGC_I210_FLSWCTL\t0x12048\n+#define IGC_I210_FLSWDATA\t0x1204C\n+#define IGC_I210_FLSWCNT\t0x12050\n+\n+#define IGC_I210_FLA\t\t0x1201C\n+\n+#define IGC_SHADOWINF\t\t0x12068\n+#define IGC_FLFWUPDATE\t0x12108\n+\n+#define IGC_INVM_DATA_REG(_n)\t(0x12120 + 4 * (_n))\n+#define IGC_INVM_SIZE\t\t64 /* Number of INVM Data Registers */\n+\n+/* QAV Tx mode control register */\n+#define IGC_I210_TQAVCTRL\t0x3570\n+\n+/* QAV Tx mode control register bitfields masks */\n+/* QAV enable */\n+#define IGC_TQAVCTRL_MODE\t\t\t(1 << 0)\n+/* Fetching arbitration type */\n+#define IGC_TQAVCTRL_FETCH_ARB\t\t(1 << 4)\n+/* Fetching timer enable */\n+#define IGC_TQAVCTRL_FETCH_TIMER_ENABLE\t(1 << 5)\n+/* Launch arbitration type */\n+#define IGC_TQAVCTRL_LAUNCH_ARB\t\t(1 << 8)\n+/* Launch timer enable */\n+#define IGC_TQAVCTRL_LAUNCH_TIMER_ENABLE\t(1 << 9)\n+/* SP waits for SR enable */\n+#define IGC_TQAVCTRL_SP_WAIT_SR\t\t(1 << 10)\n+/* Fetching timer correction */\n+#define IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET\t16\n+#define IGC_TQAVCTRL_FETCH_TIMER_DELTA\t\\\n+\t\t\t(0xFFFF << IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)\n+\n+/* High credit registers where _n can be 0 or 1. */\n+#define IGC_I210_TQAVHC(_n)\t\t\t(0x300C + 0x40 * (_n))\n+\n+/* Queues fetch arbitration priority control register */\n+#define IGC_I210_TQAVARBCTRL\t\t\t0x3574\n+/* Queues priority masks where _n and _p can be 0-3. */\n+#define IGC_TQAVARBCTRL_QUEUE_PRI(_n, _p)\t((_p) << (2 * (_n)))\n+/* QAV Tx mode control registers where _n can be 0 or 1. */\n+#define IGC_I210_TQAVCC(_n)\t\t\t(0x3004 + 0x40 * (_n))\n+\n+/* QAV Tx mode control register bitfields masks */\n+#define IGC_TQAVCC_IDLE_SLOPE\t\t0xFFFF /* Idle slope */\n+#define IGC_TQAVCC_KEEP_CREDITS\t(1 << 30) /* Keep credits opt enable */\n+#define IGC_TQAVCC_QUEUE_MODE\t\t(1 << 31) /* SP vs. SR Tx mode */\n+\n+/* Good transmitted packets counter registers */\n+#define IGC_PQGPTC(_n)\t\t(0x010014 + (0x100 * (_n)))\n+\n+/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */\n+#define IGC_I210_TXPBS_SIZE(_n, _s)\t((_s) << (6 * (_n)))\n+\n+#define IGC_MMDAC\t\t\t13 /* MMD Access Control */\n+#define IGC_MMDAAD\t\t\t14 /* MMD Access Address/Data */\n+\n+/* Convenience macros\n+ *\n+ * Note: \"_n\" is the queue number of the register\n+ *\n+ * Example usage:\n+ * IGC_RDBAL_REG(current_rx_queue)\n+ */\n+#define IGC_QUEUE_REG(n, low, high) (\t\\\n+\t__extension__ ({\t\t\t\\\n+\t\ttypeof(n) _n = (n);\t\t\\\n+\t\t_n < 4 ? ((low) + _n * 0x100) : ((high) + _n * 0x40);\t\\\n+\t}))\n+\n+#define IGC_RDBAL(_n)\t\tIGC_QUEUE_REG(_n, 0x02800, 0x0C000)\n+#define IGC_RDBAH(_n)\t\tIGC_QUEUE_REG(_n, 0x02804, 0x0C004)\n+#define IGC_RDLEN(_n)\t\tIGC_QUEUE_REG(_n, 0x02808, 0x0C008)\n+#define IGC_SRRCTL(_n)\t\tIGC_QUEUE_REG(_n, 0x0280C, 0x0C00C)\n+#define IGC_RDH(_n)\t\tIGC_QUEUE_REG(_n, 0x02810, 0x0C010)\n+#define IGC_RXCTL(_n)\t\tIGC_QUEUE_REG(_n, 0x02814, 0x0C014)\n+#define IGC_DCA_RXCTRL(_n)\tIGC_RXCTL(_n)\n+#define IGC_RDT(_n)\t\tIGC_QUEUE_REG(_n, 0x02818, 0x0C018)\n+#define IGC_RXDCTL(_n)\t\tIGC_QUEUE_REG(_n, 0x02828, 0x0C028)\n+#define IGC_RQDPC(_n)\t\tIGC_QUEUE_REG(_n, 0x02830, 0x0C030)\n+#define IGC_TDBAL(_n)\t\tIGC_QUEUE_REG(_n, 0x03800, 0x0E000)\n+#define IGC_TDBAH(_n)\t\tIGC_QUEUE_REG(_n, 0x03804, 0x0E004)\n+#define IGC_TDLEN(_n)\t\tIGC_QUEUE_REG(_n, 0x03808, 0x0E008)\n+#define IGC_TDH(_n)\t\tIGC_QUEUE_REG(_n, 0x03810, 0x0E010)\n+#define IGC_TXCTL(_n)\t\tIGC_QUEUE_REG(_n, 0x03814, 0x0E014)\n+#define IGC_DCA_TXCTRL(_n)\tIGC_TXCTL(_n)\n+#define IGC_TDT(_n)\t\tIGC_QUEUE_REG(_n, 0x03818, 0x0E018)\n+#define IGC_TXDCTL(_n)\t\tIGC_QUEUE_REG(_n, 0x03828, 0x0E028)\n+#define IGC_TDWBAL(_n)\t\tIGC_QUEUE_REG(_n, 0x03838, 0x0E038)\n+#define IGC_TDWBAH(_n)\t\tIGC_QUEUE_REG(_n, 0x0383C, 0x0E03C)\n+#define IGC_TARC(_n)\t\t(0x03840 + (_n) * 0x100)\n+#define IGC_RSRPD\t\t0x02C00  /* Rx Small Packet Detect - RW */\n+#define IGC_RAID\t\t0x02C08  /* Receive Ack Interrupt Delay - RW */\n+#define IGC_TXDMAC\t\t0x03000  /* Tx DMA Control - RW */\n+#define IGC_KABGTXD\t\t0x03004  /* AFE Band Gap Transmit Ref Data */\n+#define IGC_PSRTYPE(_i)\t(0x05480 + ((_i) * 4))\n+\n+#define IGC_RAL(n)\t\t(\t\\\n+\t__extension__ ({\t\t\\\n+\t\ttypeof(n) _n = (n);\t\\\n+\t\t_n < 16 ? (0x05400 + _n * 8) : (0x054E0 + (_n - 16) * 8); \\\n+\t}))\n+\n+#define IGC_RAH(_n)\t\t(IGC_RAL(_n) + 4)\n+\n+#define IGC_VLAPQF\t\t0x055B0  /* VLAN Priority Queue Filter VLAPQF */\n+\n+#define IGC_SHRAL(_i)\t\t(0x05438 + ((_i) * 8))\n+#define IGC_SHRAH(_i)\t\t(0x0543C + ((_i) * 8))\n+#define IGC_IP4AT_REG(_i)\t(0x05840 + ((_i) * 8))\n+#define IGC_IP6AT_REG(_i)\t(0x05880 + ((_i) * 4))\n+#define IGC_WUPM_REG(_i)\t(0x05A00 + ((_i) * 4))\n+#define IGC_FFMT_REG(_i)\t(0x09000 + ((_i) * 8))\n+#define IGC_FFVT_REG(_i)\t(0x09800 + ((_i) * 8))\n+#define IGC_FFLT_REG(_i)\t(0x05F00 + ((_i) * 8))\n+#define IGC_PBSLAC\t\t0x03100  /* Pkt Buffer Slave Access Control */\n+#define IGC_PBSLAD(_n)\t(0x03110 + (0x4 * (_n)))  /* Pkt Buffer DWORD */\n+#define IGC_TXPBS\t\t0x03404  /* Tx Packet Buffer Size - RW */\n+/* Same as TXPBS, renamed for newer Si - RW */\n+#define IGC_ITPBS\t\t0x03404\n+#define IGC_TDFH\t\t0x03410  /* Tx Data FIFO Head - RW */\n+#define IGC_TDFT\t\t0x03418  /* Tx Data FIFO Tail - RW */\n+#define IGC_TDFHS\t\t0x03420  /* Tx Data FIFO Head Saved - RW */\n+#define IGC_TDFTS\t\t0x03428  /* Tx Data FIFO Tail Saved - RW */\n+#define IGC_TDFPC\t\t0x03430  /* Tx Data FIFO Packet Count - RW */\n+#define IGC_TDPUMB\t\t0x0357C  /* DMA Tx Desc uC Mail Box - RW */\n+#define IGC_TDPUAD\t\t0x03580  /* DMA Tx Desc uC Addr Command - RW */\n+#define IGC_TDPUWD\t\t0x03584  /* DMA Tx Desc uC Data Write - RW */\n+#define IGC_TDPURD\t\t0x03588  /* DMA Tx Desc uC Data  Read  - RW */\n+#define IGC_TDPUCTL\t\t0x0358C  /* DMA Tx Desc uC Control - RW */\n+#define IGC_DTXCTL\t\t0x03590  /* DMA Tx Control - RW */\n+#define IGC_DTXTCPFLGL\t0x0359C /* DMA Tx Control flag low - RW */\n+#define IGC_DTXTCPFLGH\t0x035A0 /* DMA Tx Control flag high - RW */\n+/* DMA Tx Max Total Allow Size Reqs - RW */\n+#define IGC_DTXMXSZRQ\t\t0x03540\n+#define IGC_TIDV\t0x03820  /* Tx Interrupt Delay Value - RW */\n+#define IGC_TADV\t0x0382C  /* Tx Interrupt Absolute Delay Val - RW */\n+#define IGC_TSPMT\t0x03830  /* TCP Segmentation PAD & Min Threshold - RW */\n+/* Statistics Register Descriptions */\n+#define IGC_CRCERRS\t0x04000  /* CRC Error Count - R/clr */\n+#define IGC_ALGNERRC\t0x04004  /* Alignment Error Count - R/clr */\n+#define IGC_SYMERRS\t0x04008  /* Symbol Error Count - R/clr */\n+#define IGC_RXERRC\t0x0400C  /* Receive Error Count - R/clr */\n+#define IGC_MPC\t0x04010  /* Missed Packet Count - R/clr */\n+#define IGC_SCC\t0x04014  /* Single Collision Count - R/clr */\n+#define IGC_ECOL\t0x04018  /* Excessive Collision Count - R/clr */\n+#define IGC_MCC\t0x0401C  /* Multiple Collision Count - R/clr */\n+#define IGC_LATECOL\t0x04020  /* Late Collision Count - R/clr */\n+#define IGC_COLC\t0x04028  /* Collision Count - R/clr */\n+#define IGC_DC\t0x04030  /* Defer Count - R/clr */\n+#define IGC_TNCRS\t0x04034  /* Tx-No CRS - R/clr */\n+#define IGC_SEC\t0x04038  /* Sequence Error Count - R/clr */\n+#define IGC_CEXTERR\t0x0403C  /* Carrier Extension Error Count - R/clr */\n+#define IGC_RLEC\t0x04040  /* Receive Length Error Count - R/clr */\n+#define IGC_XONRXC\t0x04048  /* XON Rx Count - R/clr */\n+#define IGC_XONTXC\t0x0404C  /* XON Tx Count - R/clr */\n+#define IGC_XOFFRXC\t0x04050  /* XOFF Rx Count - R/clr */\n+#define IGC_XOFFTXC\t0x04054  /* XOFF Tx Count - R/clr */\n+#define IGC_FCRUC\t0x04058  /* Flow Control Rx Unsupported Count- R/clr */\n+#define IGC_PRC64\t0x0405C  /* Packets Rx (64 bytes) - R/clr */\n+#define IGC_PRC127\t0x04060  /* Packets Rx (65-127 bytes) - R/clr */\n+#define IGC_PRC255\t0x04064  /* Packets Rx (128-255 bytes) - R/clr */\n+#define IGC_PRC511\t0x04068  /* Packets Rx (255-511 bytes) - R/clr */\n+#define IGC_PRC1023\t0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */\n+#define IGC_PRC1522\t0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */\n+#define IGC_GPRC\t0x04074  /* Good Packets Rx Count - R/clr */\n+#define IGC_BPRC\t0x04078  /* Broadcast Packets Rx Count - R/clr */\n+#define IGC_MPRC\t0x0407C  /* Multicast Packets Rx Count - R/clr */\n+#define IGC_GPTC\t0x04080  /* Good Packets Tx Count - R/clr */\n+#define IGC_GORCL\t0x04088  /* Good Octets Rx Count Low - R/clr */\n+#define IGC_GORCH\t0x0408C  /* Good Octets Rx Count High - R/clr */\n+#define IGC_GOTCL\t0x04090  /* Good Octets Tx Count Low - R/clr */\n+#define IGC_GOTCH\t0x04094  /* Good Octets Tx Count High - R/clr */\n+#define IGC_RNBC\t0x040A0  /* Rx No Buffers Count - R/clr */\n+#define IGC_RUC\t0x040A4  /* Rx Undersize Count - R/clr */\n+#define IGC_RFC\t0x040A8  /* Rx Fragment Count - R/clr */\n+#define IGC_ROC\t0x040AC  /* Rx Oversize Count - R/clr */\n+#define IGC_RJC\t0x040B0  /* Rx Jabber Count - R/clr */\n+#define IGC_MGTPRC\t0x040B4  /* Management Packets Rx Count - R/clr */\n+#define IGC_MGTPDC\t0x040B8  /* Management Packets Dropped Count - R/clr */\n+#define IGC_MGTPTC\t0x040BC  /* Management Packets Tx Count - R/clr */\n+#define IGC_TORL\t0x040C0  /* Total Octets Rx Low - R/clr */\n+#define IGC_TORH\t0x040C4  /* Total Octets Rx High - R/clr */\n+#define IGC_TOTL\t0x040C8  /* Total Octets Tx Low - R/clr */\n+#define IGC_TOTH\t0x040CC  /* Total Octets Tx High - R/clr */\n+#define IGC_TPR\t0x040D0  /* Total Packets Rx - R/clr */\n+#define IGC_TPT\t0x040D4  /* Total Packets Tx - R/clr */\n+#define IGC_PTC64\t0x040D8  /* Packets Tx (64 bytes) - R/clr */\n+#define IGC_PTC127\t0x040DC  /* Packets Tx (65-127 bytes) - R/clr */\n+#define IGC_PTC255\t0x040E0  /* Packets Tx (128-255 bytes) - R/clr */\n+#define IGC_PTC511\t0x040E4  /* Packets Tx (256-511 bytes) - R/clr */\n+#define IGC_PTC1023\t0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */\n+#define IGC_PTC1522\t0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */\n+#define IGC_MPTC\t0x040F0  /* Multicast Packets Tx Count - R/clr */\n+#define IGC_BPTC\t0x040F4  /* Broadcast Packets Tx Count - R/clr */\n+#define IGC_TSCTC\t0x040F8  /* TCP Segmentation Context Tx - R/clr */\n+#define IGC_TSCTFC\t0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */\n+#define IGC_IAC\t0x04100  /* Interrupt Assertion Count */\n+/* Interrupt Cause */\n+#define IGC_ICRXPTC\t0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */\n+#define IGC_ICRXATC\t0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */\n+#define IGC_ICTXPTC\t0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */\n+#define IGC_ICTXATC\t0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */\n+#define IGC_ICTXQEC\t0x04118  /* Interrupt Cause Tx Queue Empty Count */\n+#define IGC_ICTXQMTC\t0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */\n+#define IGC_ICRXDMTC\t0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */\n+#define IGC_ICRXOC\t0x04124  /* Interrupt Cause Receiver Overrun Count */\n+#define IGC_CRC_OFFSET\t0x05F50  /* CRC Offset register */\n+\n+#define IGC_VFGPRC\t0x00F10\n+#define IGC_VFGORC\t0x00F18\n+#define IGC_VFMPRC\t0x00F3C\n+#define IGC_VFGPTC\t0x00F14\n+#define IGC_VFGOTC\t0x00F34\n+#define IGC_VFGOTLBC\t0x00F50\n+#define IGC_VFGPTLBC\t0x00F44\n+#define IGC_VFGORLBC\t0x00F48\n+#define IGC_VFGPRLBC\t0x00F40\n+/* Virtualization statistical counters */\n+#define IGC_PFVFGPRC(_n)\t(0x010010 + (0x100 * (_n)))\n+#define IGC_PFVFGPTC(_n)\t(0x010014 + (0x100 * (_n)))\n+#define IGC_PFVFGORC(_n)\t(0x010018 + (0x100 * (_n)))\n+#define IGC_PFVFGOTC(_n)\t(0x010034 + (0x100 * (_n)))\n+#define IGC_PFVFMPRC(_n)\t(0x010038 + (0x100 * (_n)))\n+#define IGC_PFVFGPRLBC(_n)\t(0x010040 + (0x100 * (_n)))\n+#define IGC_PFVFGPTLBC(_n)\t(0x010044 + (0x100 * (_n)))\n+#define IGC_PFVFGORLBC(_n)\t(0x010048 + (0x100 * (_n)))\n+#define IGC_PFVFGOTLBC(_n)\t(0x010050 + (0x100 * (_n)))\n+\n+/* LinkSec */\n+#define IGC_LSECTXUT\t\t0x04300  /* Tx Untagged Pkt Cnt */\n+#define IGC_LSECTXPKTE\t0x04304  /* Encrypted Tx Pkts Cnt */\n+#define IGC_LSECTXPKTP\t0x04308  /* Protected Tx Pkt Cnt */\n+#define IGC_LSECTXOCTE\t0x0430C  /* Encrypted Tx Octets Cnt */\n+#define IGC_LSECTXOCTP\t0x04310  /* Protected Tx Octets Cnt */\n+#define IGC_LSECRXUT\t\t0x04314  /* Untagged non-Strict Rx Pkt Cnt */\n+#define IGC_LSECRXOCTD\t0x0431C  /* Rx Octets Decrypted Count */\n+#define IGC_LSECRXOCTV\t0x04320  /* Rx Octets Validated */\n+#define IGC_LSECRXBAD\t\t0x04324  /* Rx Bad Tag */\n+#define IGC_LSECRXNOSCI\t0x04328  /* Rx Packet No SCI Count */\n+#define IGC_LSECRXUNSCI\t0x0432C  /* Rx Packet Unknown SCI Count */\n+#define IGC_LSECRXUNCH\t0x04330  /* Rx Unchecked Packets Count */\n+#define IGC_LSECRXDELAY\t0x04340  /* Rx Delayed Packet Count */\n+#define IGC_LSECRXLATE\t0x04350  /* Rx Late Packets Count */\n+#define IGC_LSECRXOK(_n)\t(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */\n+#define IGC_LSECRXINV(_n)\t(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */\n+#define IGC_LSECRXNV(_n)\t(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */\n+#define IGC_LSECRXUNSA\t0x043C0  /* Rx Unused SA Count */\n+#define IGC_LSECRXNUSA\t0x043D0  /* Rx Not Using SA Count */\n+#define IGC_LSECTXCAP\t\t0x0B000  /* Tx Capabilities Register - RO */\n+#define IGC_LSECRXCAP\t\t0x0B300  /* Rx Capabilities Register - RO */\n+#define IGC_LSECTXCTRL\t0x0B004  /* Tx Control - RW */\n+#define IGC_LSECRXCTRL\t0x0B304  /* Rx Control - RW */\n+#define IGC_LSECTXSCL\t\t0x0B008  /* Tx SCI Low - RW */\n+#define IGC_LSECTXSCH\t\t0x0B00C  /* Tx SCI High - RW */\n+#define IGC_LSECTXSA\t\t0x0B010  /* Tx SA0 - RW */\n+#define IGC_LSECTXPN0\t\t0x0B018  /* Tx SA PN 0 - RW */\n+#define IGC_LSECTXPN1\t\t0x0B01C  /* Tx SA PN 1 - RW */\n+#define IGC_LSECRXSCL\t\t0x0B3D0  /* Rx SCI Low - RW */\n+#define IGC_LSECRXSCH\t\t0x0B3E0  /* Rx SCI High - RW */\n+/* LinkSec Tx 128-bit Key 0 - WO */\n+#define IGC_LSECTXKEY0(_n)\t(0x0B020 + (0x04 * (_n)))\n+/* LinkSec Tx 128-bit Key 1 - WO */\n+#define IGC_LSECTXKEY1(_n)\t(0x0B030 + (0x04 * (_n)))\n+#define IGC_LSECRXSA(_n)\t(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */\n+#define IGC_LSECRXPN(_n)\t(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */\n+/* LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit\n+ * key - RW.\n+ */\n+#define IGC_LSECRXKEY(_n, _m)\t(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))\n+\n+#define IGC_SSVPC\t\t0x041A0 /* Switch Security Violation Pkt Cnt */\n+#define IGC_IPSCTRL\t\t0xB430  /* IpSec Control Register */\n+#define IGC_IPSRXCMD\t\t0x0B408 /* IPSec Rx Command Register - RW */\n+#define IGC_IPSRXIDX\t\t0x0B400 /* IPSec Rx Index - RW */\n+/* IPSec Rx IPv4/v6 Address - RW */\n+#define IGC_IPSRXIPADDR(_n)\t(0x0B420 + (0x04 * (_n)))\n+/* IPSec Rx 128-bit Key - RW */\n+#define IGC_IPSRXKEY(_n)\t(0x0B410 + (0x04 * (_n)))\n+#define IGC_IPSRXSALT\t\t0x0B404  /* IPSec Rx Salt - RW */\n+#define IGC_IPSRXSPI\t\t0x0B40C  /* IPSec Rx SPI - RW */\n+/* IPSec Tx 128-bit Key - RW */\n+#define IGC_IPSTXKEY(_n)\t(0x0B460 + (0x04 * (_n)))\n+#define IGC_IPSTXSALT\t\t0x0B454  /* IPSec Tx Salt - RW */\n+#define IGC_IPSTXIDX\t\t0x0B450  /* IPSec Tx SA IDX - RW */\n+#define IGC_PCS_CFG0\t0x04200  /* PCS Configuration 0 - RW */\n+#define IGC_PCS_LCTL\t0x04208  /* PCS Link Control - RW */\n+#define IGC_PCS_LSTAT\t0x0420C  /* PCS Link Status - RO */\n+#define IGC_CBTMPC\t0x0402C  /* Circuit Breaker Tx Packet Count */\n+#define IGC_HTDPMC\t0x0403C  /* Host Transmit Discarded Packets */\n+#define IGC_CBRDPC\t0x04044  /* Circuit Breaker Rx Dropped Count */\n+#define IGC_CBRMPC\t0x040FC  /* Circuit Breaker Rx Packet Count */\n+#define IGC_RPTHC\t0x04104  /* Rx Packets To Host */\n+#define IGC_HGPTC\t0x04118  /* Host Good Packets Tx Count */\n+#define IGC_HTCBDPC\t0x04124  /* Host Tx Circuit Breaker Dropped Count */\n+#define IGC_HGORCL\t0x04128  /* Host Good Octets Received Count Low */\n+#define IGC_HGORCH\t0x0412C  /* Host Good Octets Received Count High */\n+#define IGC_HGOTCL\t0x04130  /* Host Good Octets Transmit Count Low */\n+#define IGC_HGOTCH\t0x04134  /* Host Good Octets Transmit Count High */\n+#define IGC_LENERRS\t0x04138  /* Length Errors Count */\n+#define IGC_SCVPC\t0x04228  /* SerDes/SGMII Code Violation Pkt Count */\n+#define IGC_HRMPC\t0x0A018  /* Header Redirection Missed Packet Count */\n+#define IGC_PCS_ANADV\t0x04218  /* AN advertisement - RW */\n+#define IGC_PCS_LPAB\t0x0421C  /* Link Partner Ability - RW */\n+#define IGC_PCS_NPTX\t0x04220  /* AN Next Page Transmit - RW */\n+#define IGC_PCS_LPABNP\t0x04224 /* Link Partner Ability Next Pg - RW */\n+#define IGC_RXCSUM\t0x05000  /* Rx Checksum Control - RW */\n+#define IGC_RLPML\t0x05004  /* Rx Long Packet Max Length */\n+#define IGC_RFCTL\t0x05008  /* Receive Filter Control*/\n+#define IGC_MTA\t0x05200  /* Multicast Table Array - RW Array */\n+#define IGC_RA\t0x05400  /* Receive Address - RW Array */\n+#define IGC_RA2\t0x054E0  /* 2nd half of Rx address array - RW Array */\n+#define IGC_VFTA\t0x05600  /* VLAN Filter Table Array - RW Array */\n+#define IGC_VT_CTL\t0x0581C  /* VMDq Control - RW */\n+#define IGC_CIAA\t0x05B88  /* Config Indirect Access Address - RW */\n+#define IGC_CIAD\t0x05B8C  /* Config Indirect Access Data - RW */\n+#define IGC_VFQA0\t0x0B000  /* VLAN Filter Queue Array 0 - RW Array */\n+#define IGC_VFQA1\t0x0B200  /* VLAN Filter Queue Array 1 - RW Array */\n+#define IGC_WUC\t0x05800  /* Wakeup Control - RW */\n+#define IGC_WUFC\t0x05808  /* Wakeup Filter Control - RW */\n+#define IGC_WUS\t0x05810  /* Wakeup Status - RO */\n+/* Management registers */\n+#define IGC_MANC\t0x05820  /* Management Control - RW */\n+#define IGC_IPAV\t0x05838  /* IP Address Valid - RW */\n+#define IGC_IP4AT\t0x05840  /* IPv4 Address Table - RW Array */\n+#define IGC_IP6AT\t0x05880  /* IPv6 Address Table - RW Array */\n+#define IGC_WUPL\t0x05900  /* Wakeup Packet Length - RW */\n+#define IGC_WUPM\t0x05A00  /* Wakeup Packet Memory - RO A */\n+#define IGC_WUPM_EXT\t0x0B800  /* Wakeup Packet Memory Extended - RO Array */\n+#define IGC_WUFC_EXT\t0x0580C  /* Wakeup Filter Control Extended - RW */\n+#define IGC_WUS_EXT\t0x05814  /* Wakeup Status Extended - RW1C */\n+#define IGC_FHFTSL\t0x05804  /* Flex Filter Indirect Table Select - RW */\n+#define IGC_PROXYFCEX\t0x05590  /* Proxy Filter Control Extended - RW1C */\n+#define IGC_PROXYEXS\t0x05594  /* Proxy Extended Status - RO */\n+#define IGC_WFUTPF\t0x05500  /* Wake Flex UDP TCP Port Filter - RW Array */\n+#define IGC_RFUTPF\t0x05580  /* Range Flex UDP TCP Port Filter - RW */\n+#define IGC_RWPFC\t0x05584  /* Range Wake Port Filter Control - RW */\n+#define IGC_WFUTPS\t0x05588  /* Wake Filter UDP TCP Status - RW1C */\n+#define IGC_WCS\t0x0558C  /* Wake Control Status - RW1C */\n+/* MSI-X Table Register Descriptions */\n+#define IGC_PBACL\t0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */\n+#define IGC_FFLT\t0x05F00  /* Flexible Filter Length Table - RW Array */\n+#define IGC_HOST_IF\t0x08800  /* Host Interface */\n+#define IGC_HIBBA\t0x8F40   /* Host Interface Buffer Base Address */\n+/* Flexible Host Filter Table */\n+#define IGC_FHFT(_n)\t(0x09000 + ((_n) * 0x100))\n+/* Ext Flexible Host Filter Table */\n+#define IGC_FHFT_EXT(_n)\t(0x09A00 + ((_n) * 0x100))\n+\n+\n+#define IGC_KMRNCTRLSTA\t0x00034 /* MAC-PHY interface - RW */\n+#define IGC_MANC2H\t\t0x05860 /* Management Control To Host - RW */\n+/* Management Decision Filters */\n+#define IGC_MDEF(_n)\t\t(0x05890 + (4 * (_n)))\n+/* Semaphore registers */\n+#define IGC_SW_FW_SYNC\t0x05B5C /* SW-FW Synchronization - RW */\n+#define IGC_CCMCTL\t0x05B48 /* CCM Control Register */\n+#define IGC_GIOCTL\t0x05B44 /* GIO Analog Control Register */\n+#define IGC_SCCTL\t0x05B4C /* PCIc PLL Configuration Register */\n+/* PCIe Register Description */\n+#define IGC_GCR\t0x05B00 /* PCI-Ex Control */\n+#define IGC_GCR2\t0x05B64 /* PCI-Ex Control #2 */\n+#define IGC_GSCL_1\t0x05B10 /* PCI-Ex Statistic Control #1 */\n+#define IGC_GSCL_2\t0x05B14 /* PCI-Ex Statistic Control #2 */\n+#define IGC_GSCL_3\t0x05B18 /* PCI-Ex Statistic Control #3 */\n+#define IGC_GSCL_4\t0x05B1C /* PCI-Ex Statistic Control #4 */\n+/* Function Active and Power State to MNG */\n+#define IGC_FACTPS\t0x05B30\n+#define IGC_SWSM\t0x05B50 /* SW Semaphore */\n+#define IGC_FWSM\t0x05B54 /* FW Semaphore */\n+/* Driver-only SW semaphore (not used by BOOT agents) */\n+#define IGC_SWSM2\t0x05B58\n+#define IGC_DCA_ID\t0x05B70 /* DCA Requester ID Information - RO */\n+#define IGC_DCA_CTRL\t0x05B74 /* DCA Control - RW */\n+#define IGC_UFUSE\t0x05B78 /* UFUSE - RO */\n+#define IGC_FFLT_DBG\t0x05F04 /* Debug Register */\n+#define IGC_HICR\t0x08F00 /* Host Interface Control */\n+#define IGC_FWSTS\t0x08F0C /* FW Status */\n+\n+/* RSS registers */\n+#define IGC_CPUVEC\t0x02C10 /* CPU Vector Register - RW */\n+#define IGC_MRQC\t0x05818 /* Multiple Receive Control - RW */\n+#define IGC_IMIR(_i)\t(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */\n+#define IGC_IMIREXT(_i)\t(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/\n+#define IGC_IMIRVP\t\t0x05AC0 /* Immediate INT Rx VLAN Priority -RW */\n+#define IGC_MSIXBM(_i)\t(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */\n+/* Redirection Table - RW Array */\n+#define IGC_RETA(_i)\t(0x05C00 + ((_i) * 4))\n+/* RSS Random Key - RW Array */\n+#define IGC_RSSRK(_i)\t(0x05C80 + ((_i) * 4))\n+#define IGC_RSSIM\t0x05864 /* RSS Interrupt Mask */\n+#define IGC_RSSIR\t0x05868 /* RSS Interrupt Request */\n+#define IGC_UTA\t0x0A000 /* Unicast Table Array - RW */\n+/* VT Registers */\n+#define IGC_SWPBS\t0x03004 /* Switch Packet Buffer Size - RW */\n+#define IGC_MBVFICR\t0x00C80 /* Mailbox VF Cause - RWC */\n+#define IGC_MBVFIMR\t0x00C84 /* Mailbox VF int Mask - RW */\n+#define IGC_VFLRE\t0x00C88 /* VF Register Events - RWC */\n+#define IGC_VFRE\t0x00C8C /* VF Receive Enables */\n+#define IGC_VFTE\t0x00C90 /* VF Transmit Enables */\n+#define IGC_QDE\t0x02408 /* Queue Drop Enable - RW */\n+#define IGC_DTXSWC\t0x03500 /* DMA Tx Switch Control - RW */\n+#define IGC_WVBR\t0x03554 /* VM Wrong Behavior - RWS */\n+#define IGC_RPLOLR\t0x05AF0 /* Replication Offload - RW */\n+#define IGC_IOVTCL\t0x05BBC /* IOV Control Register */\n+#define IGC_VMRCTL\t0X05D80 /* Virtual Mirror Rule Control */\n+#define IGC_VMRVLAN\t0x05D90 /* Virtual Mirror Rule VLAN */\n+#define IGC_VMRVM\t0x05DA0 /* Virtual Mirror Rule VM */\n+#define IGC_MDFB\t0x03558 /* Malicious Driver free block */\n+#define IGC_LVMMC\t0x03548 /* Last VM Misbehavior cause */\n+#define IGC_TXSWC\t0x05ACC /* Tx Switch Control */\n+#define IGC_SCCRL\t0x05DB0 /* Storm Control Control */\n+#define IGC_BSCTRH\t0x05DB8 /* Broadcast Storm Control Threshold */\n+#define IGC_MSCTRH\t0x05DBC /* Multicast Storm Control Threshold */\n+/* These act per VF so an array friendly macro is used */\n+#define IGC_V2PMAILBOX(_n)\t(0x00C40 + (4 * (_n)))\n+#define IGC_P2VMAILBOX(_n)\t(0x00C00 + (4 * (_n)))\n+#define IGC_VMBMEM(_n)\t(0x00800 + (64 * (_n)))\n+#define IGC_VFVMBMEM(_n)\t(0x00800 + (_n))\n+#define IGC_VMOLR(_n)\t\t(0x05AD0 + (4 * (_n)))\n+/* VLAN Virtual Machine Filter - RW */\n+#define IGC_VLVF(_n)\t\t(0x05D00 + (4 * (_n)))\n+#define IGC_VMVIR(_n)\t\t(0x03700 + (4 * (_n)))\n+#define IGC_DVMOLR(_n)\t(0x0C038 + (0x40 * (_n))) /* DMA VM offload */\n+#define IGC_VTCTRL(_n)\t(0x10000 + (0x100 * (_n))) /* VT Control */\n+#define IGC_TSYNCRXCTL\t0x0B620 /* Rx Time Sync Control register - RW */\n+#define IGC_TSYNCTXCTL\t0x0B614 /* Tx Time Sync Control register - RW */\n+#define IGC_TSYNCRXCFG\t0x05F50 /* Time Sync Rx Configuration - RW */\n+#define IGC_RXSTMPL\t0x0B624 /* Rx timestamp Low - RO */\n+#define IGC_RXSTMPH\t0x0B628 /* Rx timestamp High - RO */\n+#define IGC_RXSATRL\t0x0B62C /* Rx timestamp attribute low - RO */\n+#define IGC_RXSATRH\t0x0B630 /* Rx timestamp attribute high - RO */\n+#define IGC_TXSTMPL\t0x0B618 /* Tx timestamp value Low - RO */\n+#define IGC_TXSTMPH\t0x0B61C /* Tx timestamp value High - RO */\n+#define IGC_SYSTIML\t0x0B600 /* System time register Low - RO */\n+#define IGC_SYSTIMH\t0x0B604 /* System time register High - RO */\n+#define IGC_TIMINCA\t0x0B608 /* Increment attributes register - RW */\n+#define IGC_TIMADJL\t0x0B60C /* Time sync time adjustment offset Low - RW */\n+#define IGC_TIMADJH\t0x0B610 /* Time sync time adjustment offset High - RW */\n+#define IGC_TSAUXC\t0x0B640 /* Timesync Auxiliary Control register */\n+#define\tIGC_SYSSTMPL\t0x0B648 /* HH Timesync system stamp low register */\n+#define\tIGC_SYSSTMPH\t0x0B64C /* HH Timesync system stamp hi register */\n+#define\tIGC_PLTSTMPL\t0x0B640 /* HH Timesync platform stamp low register */\n+#define\tIGC_PLTSTMPH\t0x0B644 /* HH Timesync platform stamp hi register */\n+#define IGC_SYSTIMR\t0x0B6F8 /* System time register Residue */\n+#define IGC_TSICR\t0x0B66C /* Interrupt Cause Register */\n+#define IGC_TSIM\t0x0B674 /* Interrupt Mask Register */\n+#define IGC_RXMTRL\t0x0B634 /* Time sync Rx EtherType and Msg Type - RW */\n+#define IGC_RXUDP\t0x0B638 /* Time Sync Rx UDP Port - RW */\n+\n+/* Filtering Registers */\n+#define IGC_SAQF(_n)\t(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */\n+#define IGC_DAQF(_n)\t(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */\n+#define IGC_SPQF(_n)\t(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */\n+#define IGC_FTQF(_n)\t(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */\n+#define IGC_TTQF(_n)\t(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */\n+#define IGC_SYNQF(_n)\t(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */\n+#define IGC_ETQF(_n)\t(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */\n+\n+#define IGC_RTTDCS\t0x3600 /* Reedtown Tx Desc plane control and status */\n+#define IGC_RTTPCS\t0x3474 /* Reedtown Tx Packet Plane control and status */\n+#define IGC_RTRPCS\t0x2474 /* Rx packet plane control and status */\n+#define IGC_RTRUP2TC\t0x05AC4 /* Rx User Priority to Traffic Class */\n+#define IGC_RTTUP2TC\t0x0418 /* Transmit User Priority to Traffic Class */\n+/* Tx Desc plane TC Rate-scheduler config */\n+#define IGC_RTTDTCRC(_n)\t(0x3610 + ((_n) * 4))\n+/* Tx Packet plane TC Rate-Scheduler Config */\n+#define IGC_RTTPTCRC(_n)\t(0x3480 + ((_n) * 4))\n+/* Rx Packet plane TC Rate-Scheduler Config */\n+#define IGC_RTRPTCRC(_n)\t(0x2480 + ((_n) * 4))\n+/* Tx Desc Plane TC Rate-Scheduler Status */\n+#define IGC_RTTDTCRS(_n)\t(0x3630 + ((_n) * 4))\n+/* Tx Desc Plane TC Rate-Scheduler MMW */\n+#define IGC_RTTDTCRM(_n)\t(0x3650 + ((_n) * 4))\n+/* Tx Packet plane TC Rate-Scheduler Status */\n+#define IGC_RTTPTCRS(_n)\t(0x34A0 + ((_n) * 4))\n+/* Tx Packet plane TC Rate-scheduler MMW */\n+#define IGC_RTTPTCRM(_n)\t(0x34C0 + ((_n) * 4))\n+/* Rx Packet plane TC Rate-Scheduler Status */\n+#define IGC_RTRPTCRS(_n)\t(0x24A0 + ((_n) * 4))\n+/* Rx Packet plane TC Rate-Scheduler MMW */\n+#define IGC_RTRPTCRM(_n)\t(0x24C0 + ((_n) * 4))\n+/* Tx Desc plane VM Rate-Scheduler MMW*/\n+#define IGC_RTTDVMRM(_n)\t(0x3670 + ((_n) * 4))\n+/* Tx BCN Rate-Scheduler MMW */\n+#define IGC_RTTBCNRM(_n)\t(0x3690 + ((_n) * 4))\n+#define IGC_RTTDQSEL\t0x3604  /* Tx Desc Plane Queue Select */\n+#define IGC_RTTDVMRC\t0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */\n+#define IGC_RTTDVMRS\t0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */\n+#define IGC_RTTBCNRC\t0x36B0  /* Tx BCN Rate-Scheduler Config */\n+#define IGC_RTTBCNRS\t0x36B4  /* Tx BCN Rate-Scheduler Status */\n+#define IGC_RTTBCNCR\t0xB200  /* Tx BCN Control Register */\n+#define IGC_RTTBCNTG\t0x35A4  /* Tx BCN Tagging */\n+#define IGC_RTTBCNCP\t0xB208  /* Tx BCN Congestion point */\n+#define IGC_RTRBCNCR\t0xB20C  /* Rx BCN Control Register */\n+#define IGC_RTTBCNRD\t0x36B8  /* Tx BCN Rate Drift */\n+#define IGC_PFCTOP\t0x1080  /* Priority Flow Control Type and Opcode */\n+#define IGC_RTTBCNIDX\t0xB204  /* Tx BCN Congestion Point */\n+#define IGC_RTTBCNACH\t0x0B214 /* Tx BCN Control High */\n+#define IGC_RTTBCNACL\t0x0B210 /* Tx BCN Control Low */\n+\n+/* DMA Coalescing registers */\n+#define IGC_DMACR\t0x02508 /* Control Register */\n+#define IGC_DMCTXTH\t0x03550 /* Transmit Threshold */\n+#define IGC_DMCTLX\t0x02514 /* Time to Lx Request */\n+#define IGC_DMCRTRH\t0x05DD0 /* Receive Packet Rate Threshold */\n+#define IGC_DMCCNT\t0x05DD4 /* Current Rx Count */\n+#define IGC_FCRTC\t0x02170 /* Flow Control Rx high watermark */\n+#define IGC_PCIEMISC\t0x05BB8 /* PCIE misc config register */\n+\n+/* PCIe Parity Status Register */\n+#define IGC_PCIEERRSTS\t0x05BA8\n+\n+#define IGC_PROXYS\t0x5F64 /* Proxying Status */\n+#define IGC_PROXYFC\t0x5F60 /* Proxying Filter Control */\n+/* Thermal sensor configuration and status registers */\n+#define IGC_THMJT\t0x08100 /* Junction Temperature */\n+#define IGC_THLOWTC\t0x08104 /* Low Threshold Control */\n+#define IGC_THMIDTC\t0x08108 /* Mid Threshold Control */\n+#define IGC_THHIGHTC\t0x0810C /* High Threshold Control */\n+#define IGC_THSTAT\t0x08110 /* Thermal Sensor Status */\n+\n+/* Energy Efficient Ethernet \"EEE\" registers */\n+#define IGC_IPCNFG\t0x0E38 /* Internal PHY Configuration */\n+#define IGC_LTRC\t0x01A0 /* Latency Tolerance Reporting Control */\n+#define IGC_EEER\t0x0E30 /* Energy Efficient Ethernet \"EEE\"*/\n+#define IGC_EEE_SU\t0x0E34 /* EEE Setup */\n+#define IGC_EEE_SU_2P5\t0x0E3C /* EEE 2.5G Setup */\n+#define IGC_TLPIC\t0x4148 /* EEE Tx LPI Count - TLPIC */\n+#define IGC_RLPIC\t0x414C /* EEE Rx LPI Count - RLPIC */\n+\n+/* OS2BMC Registers */\n+#define IGC_B2OSPC\t0x08FE0 /* BMC2OS packets sent by BMC */\n+#define IGC_B2OGPRC\t0x04158 /* BMC2OS packets received by host */\n+#define IGC_O2BGPTC\t0x08FE4 /* OS2BMC packets received by BMC */\n+#define IGC_O2BSPC\t0x0415C /* OS2BMC packets transmitted by host */\n+\n+#define IGC_LTRMINV\t0x5BB0 /* LTR Minimum Value */\n+#define IGC_LTRMAXV\t0x5BB4 /* LTR Maximum Value */\n+\n+\n+/* IEEE 1588 TIMESYNCH */\n+#define IGC_TRGTTIML0\t0x0B644 /* Target Time Register 0 Low  - RW */\n+#define IGC_TRGTTIMH0\t0x0B648 /* Target Time Register 0 High - RW */\n+#define IGC_TRGTTIML1\t0x0B64C /* Target Time Register 1 Low  - RW */\n+#define IGC_TRGTTIMH1\t0x0B650 /* Target Time Register 1 High - RW */\n+#define IGC_FREQOUT0\t0x0B654 /* Frequency Out 0 Control Register - RW */\n+#define IGC_FREQOUT1\t0x0B658 /* Frequency Out 1 Control Register - RW */\n+#define IGC_TSSDP\t0x0003C  /* Time Sync SDP Configuration Register - RW */\n+\n+#define IGC_LTRC_EEEMS_EN\t\t\t(1 << 5)\n+#define IGC_TW_SYSTEM_100_MASK\t\t0xff00\n+#define IGC_TW_SYSTEM_100_SHIFT\t8\n+#define IGC_TW_SYSTEM_1000_MASK\t0xff\n+#define IGC_LTRMINV_SCALE_1024\t\t0x02\n+#define IGC_LTRMINV_SCALE_32768\t0x03\n+#define IGC_LTRMAXV_SCALE_1024\t\t0x02\n+#define IGC_LTRMAXV_SCALE_32768\t0x03\n+#define IGC_LTRMINV_LTRV_MASK\t\t0x1ff\n+#define IGC_LTRMINV_LSNP_REQ\t\t0x80\n+#define IGC_LTRMINV_SCALE_SHIFT\t10\n+#define IGC_LTRMAXV_LTRV_MASK\t\t0x1ff\n+#define IGC_LTRMAXV_LSNP_REQ\t\t0x80\n+#define IGC_LTRMAXV_SCALE_SHIFT\t10\n+\n+#define IGC_MRQC_ENABLE_MASK\t\t0x00000007\n+#define IGC_MRQC_RSS_FIELD_IPV6_EX\t0x00080000\n+#define IGC_RCTL_DTYP_MASK\t\t0x00000C00 /* Descriptor type mask */\n+\n+#endif\ndiff --git a/drivers/net/igc/base/meson.build b/drivers/net/igc/base/meson.build\nnew file mode 100644\nindex 0000000..f51026e\n--- /dev/null\n+++ b/drivers/net/igc/base/meson.build\n@@ -0,0 +1,28 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Intel Corporation\n+\n+sources = [\n+\t'e1000_api.c',\n+\t'e1000_base.c',\n+\t'e1000_i225.c',\n+\t'e1000_mac.c',\n+\t'e1000_manage.c',\n+\t'e1000_nvm.c',\n+\t'e1000_osdep.c',\n+\t'e1000_phy.c',\n+]\n+\n+error_cflags = ['-Wno-unused-parameter', '-Wno-unused-variable']\n+c_args = cflags\n+\n+foreach flag: error_cflags\n+\tif cc.has_argument(flag)\n+\t\tc_args += flag\n+\tendif\n+endforeach\n+\n+base_lib = static_library('igc_base', sources,\n+\tdependencies: static_rte_eal,\n+\tc_args: c_args)\n+\n+base_objs = base_lib.extract_all_objects()\ndiff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c\nindex cd2ffd6..0a1d740 100644\n--- a/drivers/net/igc/igc_ethdev.c\n+++ b/drivers/net/igc/igc_ethdev.c\n@@ -11,11 +11,8 @@\n #include \"igc_ethdev.h\"\n \n #define IGC_INTEL_VENDOR_ID\t\t0x8086\n-#define IGC_DEV_ID_I225_LM\t\t0x15F2\n-#define IGC_DEV_ID_I225_V\t\t0x15F3\n-#define IGC_DEV_ID_I225_K\t\t0x3100\n-#define IGC_DEV_ID_I225_I\t\t0x15F8\n-#define IGC_DEV_ID_I220_V\t\t0x15F7\n+\n+#define IGC_FC_PAUSE_TIME\t\t0x0680\n \n static const struct rte_pci_id pci_id_igc_map[] = {\n \t{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) },\n@@ -83,6 +80,90 @@ static int eth_igc_infos_get(struct rte_eth_dev *dev,\n \tRTE_SET_USED(dev);\n }\n \n+/*\n+ *  Get hardware rx-buffer size.\n+ */\n+static inline int\n+igc_get_rx_buffer_size(struct igc_hw *hw)\n+{\n+\treturn (IGC_READ_REG(hw, IGC_RXPBS) & 0x3f) << 10;\n+}\n+\n+/*\n+ * igc_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.\n+ * For ASF and Pass Through versions of f/w this means\n+ * that the driver is loaded.\n+ */\n+static void\n+igc_hw_control_acquire(struct igc_hw *hw)\n+{\n+\tuint32_t ctrl_ext;\n+\n+\t/* Let firmware know the driver has taken over */\n+\tctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);\n+\tIGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);\n+}\n+\n+/*\n+ * igc_hw_control_release resets CTRL_EXT:DRV_LOAD bit.\n+ * For ASF and Pass Through versions of f/w this means that the\n+ * driver is no longer loaded.\n+ */\n+static void\n+igc_hw_control_release(struct igc_hw *hw)\n+{\n+\tuint32_t ctrl_ext;\n+\n+\t/* Let firmware taken over control of h/w */\n+\tctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);\n+\tIGC_WRITE_REG(hw, IGC_CTRL_EXT,\n+\t\t\tctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);\n+}\n+\n+static int\n+igc_hardware_init(struct igc_hw *hw)\n+{\n+\tuint32_t rx_buf_size;\n+\tint diag;\n+\n+\t/* Let the firmware know the OS is in control */\n+\tigc_hw_control_acquire(hw);\n+\n+\t/* Issue a global reset */\n+\tigc_reset_hw(hw);\n+\n+\t/* disable all wake up */\n+\tIGC_WRITE_REG(hw, IGC_WUC, 0);\n+\n+\t/*\n+\t * Hardware flow control\n+\t * - High water mark should allow for at least two standard size (1518)\n+\t *   frames to be received after sending an XOFF.\n+\t * - Low water mark works best when it is very near the high water mark.\n+\t *   This allows the receiver to restart by sending XON when it has\n+\t *   drained a bit. Here we use an arbitrary value of 1500 which will\n+\t *   restart after one full frame is pulled from the buffer. There\n+\t *   could be several smaller frames in the buffer and if so they will\n+\t *   not trigger the XON until their total number reduces the buffer\n+\t *   by 1500.\n+\t */\n+\trx_buf_size = igc_get_rx_buffer_size(hw);\n+\thw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);\n+\thw->fc.low_water = hw->fc.high_water - 1500;\n+\thw->fc.pause_time = IGC_FC_PAUSE_TIME;\n+\thw->fc.send_xon = 1;\n+\thw->fc.requested_mode = igc_fc_full;\n+\n+\tdiag = igc_init_hw(hw);\n+\tif (diag < 0)\n+\t\treturn diag;\n+\n+\tigc_get_phy_info(hw);\n+\tigc_check_for_link(hw);\n+\n+\treturn 0;\n+}\n+\n static int\n eth_igc_start(struct rte_eth_dev *dev)\n {\n@@ -91,17 +172,91 @@ static int eth_igc_infos_get(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static int\n+igc_reset_swfw_lock(struct igc_hw *hw)\n+{\n+\tint ret_val;\n+\n+\t/*\n+\t * Do mac ops initialization manually here, since we will need\n+\t * some function pointers set by this call.\n+\t */\n+\tret_val = igc_init_mac_params(hw);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/*\n+\t * SMBI lock should not fail in this early stage. If this is the case,\n+\t * it is due to an improper exit of the application.\n+\t * So force the release of the faulty lock.\n+\t */\n+\tif (igc_get_hw_semaphore_generic(hw) < 0)\n+\t\tPMD_DRV_LOG(DEBUG, \"SMBI lock released\");\n+\n+\tigc_put_hw_semaphore_generic(hw);\n+\n+\tif (hw->mac.ops.acquire_swfw_sync != NULL) {\n+\t\tuint16_t mask;\n+\n+\t\t/*\n+\t\t * Phy lock should not fail in this early stage.\n+\t\t * If this is the case, it is due to an improper exit of the\n+\t\t * application. So force the release of the faulty lock.\n+\t\t */\n+\t\tmask = IGC_SWFW_PHY0_SM;\n+\t\tif (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"SWFW phy%d lock released\",\n+\t\t\t\t    hw->bus.func);\n+\t\t}\n+\t\thw->mac.ops.release_swfw_sync(hw, mask);\n+\n+\t\t/*\n+\t\t * This one is more tricky since it is common to all ports; but\n+\t\t * swfw_sync retries last long enough (1s) to be almost sure\n+\t\t * that if lock can not be taken it is due to an improper lock\n+\t\t * of the semaphore.\n+\t\t */\n+\t\tmask = IGC_SWFW_EEP_SM;\n+\t\tif (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0)\n+\t\t\tPMD_DRV_LOG(DEBUG, \"SWFW common locks released\");\n+\n+\t\thw->mac.ops.release_swfw_sync(hw, mask);\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\n+\n static void\n eth_igc_close(struct rte_eth_dev *dev)\n {\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\n \tPMD_INIT_FUNC_TRACE();\n-\t RTE_SET_USED(dev);\n+\n+\tigc_phy_hw_reset(hw);\n+\tigc_hw_control_release(hw);\n+\n+\t/* Reset any pending lock */\n+\tigc_reset_swfw_lock(hw);\n+}\n+\n+static void\n+igc_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\n+\thw->vendor_id = pci_dev->id.vendor_id;\n+\thw->device_id = pci_dev->id.device_id;\n+\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n+\thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n }\n \n static int\n eth_igc_dev_init(struct rte_eth_dev *dev)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tint error = 0;\n \n \tPMD_INIT_FUNC_TRACE();\n \tdev->dev_ops = &eth_igc_ops;\n@@ -116,12 +271,89 @@ static int eth_igc_infos_get(struct rte_eth_dev *dev,\n \n \trte_eth_copy_pci_info(dev, pci_dev);\n \n+\thw->back = pci_dev;\n+\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n+\n+\tigc_identify_hardware(dev, pci_dev);\n+\tif (igc_setup_init_funcs(hw, false) != IGC_SUCCESS) {\n+\t\terror = -EIO;\n+\t\tgoto err_late;\n+\t}\n+\n+\tigc_get_bus_info(hw);\n+\n+\t/* Reset any pending lock */\n+\tif (igc_reset_swfw_lock(hw) != IGC_SUCCESS) {\n+\t\terror = -EIO;\n+\t\tgoto err_late;\n+\t}\n+\n+\t/* Finish initialization */\n+\tif (igc_setup_init_funcs(hw, true) != IGC_SUCCESS) {\n+\t\terror = -EIO;\n+\t\tgoto err_late;\n+\t}\n+\n+\thw->mac.autoneg = 1;\n+\thw->phy.autoneg_wait_to_complete = 0;\n+\thw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;\n+\n+\t/* Copper options */\n+\tif (hw->phy.media_type == igc_media_type_copper) {\n+\t\thw->phy.mdix = 0; /* AUTO_ALL_MODES */\n+\t\thw->phy.disable_polarity_correction = 0;\n+\t\thw->phy.ms_type = igc_ms_hw_default;\n+\t}\n+\n+\t/*\n+\t * Start from a known state, this is important in reading the nvm\n+\t * and mac from that.\n+\t */\n+\tigc_reset_hw(hw);\n+\n+\t/* Make sure we have a good EEPROM before we read from it */\n+\tif (igc_validate_nvm_checksum(hw) < 0) {\n+\t\t/*\n+\t\t * Some PCI-E parts fail the first check due to\n+\t\t * the link being in sleep state, call it again,\n+\t\t * if it fails a second time its a real issue.\n+\t\t */\n+\t\tif (igc_validate_nvm_checksum(hw) < 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"EEPROM checksum invalid\");\n+\t\t\terror = -EIO;\n+\t\t\tgoto err_late;\n+\t\t}\n+\t}\n+\n+\t/* Read the permanent MAC address out of the EEPROM */\n+\tif (igc_read_mac_addr(hw) != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"EEPROM error while reading MAC address\");\n+\t\terror = -EIO;\n+\t\tgoto err_late;\n+\t}\n+\n+\t/* Allocate memory for storing MAC addresses */\n \tdev->data->mac_addrs = rte_zmalloc(\"igc\",\n-\t\tRTE_ETHER_ADDR_LEN, 0);\n+\t\tRTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);\n \tif (dev->data->mac_addrs == NULL) {\n \t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d bytes needed to \"\n-\t\t\t\t\"store MAC addresses\", RTE_ETHER_ADDR_LEN);\n-\t\treturn -ENOMEM;\n+\t\t\t\t\"store MAC addresses\",\n+\t\t\t\tRTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);\n+\t\terror = -ENOMEM;\n+\t\tgoto err_late;\n+\t}\n+\n+\t/* Copy the permanent MAC address */\n+\trte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,\n+\t\t\t&dev->data->mac_addrs[0]);\n+\n+\t/* Now initialize the hardware */\n+\tif (igc_hardware_init(hw) != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Hardware initialization failed\");\n+\t\trte_free(dev->data->mac_addrs);\n+\t\tdev->data->mac_addrs = NULL;\n+\t\terror = -ENODEV;\n+\t\tgoto err_late;\n \t}\n \n \t/* Pass the information to the rte_eth_dev_close() that it should also\n@@ -129,11 +361,22 @@ static int eth_igc_infos_get(struct rte_eth_dev *dev,\n \t */\n \tdev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;\n \n+\thw->mac.get_link_status = 1;\n+\n+\t/* Indicate SOL/IDER usage */\n+\tif (igc_check_reset_block(hw) < 0)\n+\t\tPMD_INIT_LOG(ERR, \"PHY reset is blocked due to\"\n+\t\t\t\t\" SOL/IDER session.\");\n+\n \tPMD_INIT_LOG(DEBUG, \"port_id %d vendorID=0x%x deviceID=0x%x\",\n \t\t\tdev->data->port_id, pci_dev->id.vendor_id,\n \t\t\tpci_dev->id.device_id);\n \n \treturn 0;\n+\n+err_late:\n+\tigc_hw_control_release(hw);\n+\treturn error;\n }\n \n static int\n@@ -223,7 +466,8 @@ static int eth_igc_infos_get(struct rte_eth_dev *dev,\n \tstruct rte_pci_device *pci_dev)\n {\n \tPMD_INIT_FUNC_TRACE();\n-\treturn rte_eth_dev_pci_generic_probe(pci_dev, 0, eth_igc_dev_init);\n+\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n+\t\tsizeof(struct igc_adapter), eth_igc_dev_init);\n }\n \n static int\ndiff --git a/drivers/net/igc/igc_ethdev.h b/drivers/net/igc/igc_ethdev.h\nindex a774413..73ca0bf 100644\n--- a/drivers/net/igc/igc_ethdev.h\n+++ b/drivers/net/igc/igc_ethdev.h\n@@ -5,12 +5,31 @@\n #ifndef _IGC_ETHDEV_H_\n #define _IGC_ETHDEV_H_\n \n+#include <rte_ethdev.h>\n+\n+#include \"base/e1000_osdep.h\"\n+#include \"base/e1000_hw.h\"\n+#include \"base/e1000_i225.h\"\n+#include \"base/e1000_api.h\"\n+\n #ifdef __cplusplus\n extern \"C\" {\n #endif\n \n #define IGC_QUEUE_PAIRS_NUM\t\t4\n \n+/*\n+ * Structure to store private data for each driver instance (for each port).\n+ */\n+struct igc_adapter {\n+\tstruct igc_hw\t\thw;\n+};\n+\n+#define IGC_DEV_PRIVATE(_dev)\t((_dev)->data->dev_private)\n+\n+#define IGC_DEV_PRIVATE_HW(_dev) \\\n+\t(&((struct igc_adapter *)(_dev)->data->dev_private)->hw)\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/net/igc/meson.build b/drivers/net/igc/meson.build\nindex 927938f..ffa62f1 100644\n--- a/drivers/net/igc/meson.build\n+++ b/drivers/net/igc/meson.build\n@@ -1,7 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2020 Intel Corporation\n \n+subdir('base')\n+objs = [base_objs]\n+\n sources = files(\n \t'igc_logs.c',\n \t'igc_ethdev.c'\n )\n+\n+includes += include_directories('base')\n",
    "prefixes": [
        "v2",
        "02/14"
    ]
}