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{
    "id": 66785,
    "url": "https://patches.dpdk.org/api/patches/66785/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1584459511-5353-3-git-send-email-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1584459511-5353-3-git-send-email-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1584459511-5353-3-git-send-email-venkatkumar.duvvuru@broadcom.com",
    "date": "2020-03-17T15:38:00",
    "name": "[02/33] net/bnxt: update hwrm prep to use ptr",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "15f6649b712d4f3dc574f1d8147f04ac2e295b5b",
    "submitter": {
        "id": 1635,
        "url": "https://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1584459511-5353-3-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 8955,
            "url": "https://patches.dpdk.org/api/series/8955/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=8955",
            "date": "2020-03-17T15:37:58",
            "name": "add support for host based flow table management",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/8955/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/66785/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/66785/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        ],
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        "X-Received": "by 2002:adf:d1a9:: with SMTP id w9mr5426264wrc.17.1584459542586;\n Tue, 17 Mar 2020 08:39:02 -0700 (PDT)",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Randy Schacher <stuart.schacher@broadcom.com>",
        "Date": "Tue, 17 Mar 2020 21:08:00 +0530",
        "Message-Id": "\n <1584459511-5353-3-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "References": "\n <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH 02/33] net/bnxt: update hwrm prep to use ptr",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Randy Schacher <stuart.schacher@broadcom.com>\n\n- Change HWRM_PREP to use pointer and use the full\n  HWRM enum\n\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h      |   3 +-\n drivers/net/bnxt/bnxt_hwrm.c | 206 ++++++++++++++++++++++---------------------\n 2 files changed, 107 insertions(+), 102 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 3ae08a2..07fb4df 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -594,7 +594,7 @@ struct bnxt {\n \n \tuint8_t\t\t\tmac_addr[RTE_ETHER_ADDR_LEN];\n \n-\tuint16_t\t\t\thwrm_cmd_seq;\n+\tuint16_t\t\t\tchimp_cmd_seq;\n \tuint16_t\t\t\tkong_cmd_seq;\n \tvoid\t\t\t\t*hwrm_cmd_resp_addr;\n \trte_iova_t\t\t\thwrm_cmd_resp_dma_addr;\n@@ -610,6 +610,7 @@ struct bnxt {\n #define DFLT_HWRM_CMD_TIMEOUT\t\t500000\n \t /* short command timeout value of 50ms */\n #define SHORT_HWRM_CMD_TIMEOUT\t\t50000\n+#define HWRM_CMD_TIMEOUT_TRUFLOW        DFLT_HWRM_CMD_TIMEOUT\n \t/* default HWRM request timeout value */\n \tuint32_t\t\t\thwrm_cmd_timeout;\n \ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex a9c9c72..2fb78b6 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -100,7 +100,11 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,\n \tif (bp->flags & BNXT_FLAG_FATAL_ERROR)\n \t\treturn 0;\n \n-\ttimeout = bp->hwrm_cmd_timeout;\n+\t/* For VER_GET command, set timeout as 50ms */\n+\tif (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)\n+\t\ttimeout = HWRM_CMD_TIMEOUT_TRUFLOW;\n+\telse\n+\t\ttimeout = bp->hwrm_cmd_timeout;\n \n \tif (bp->flags & BNXT_FLAG_SHORT_CMD ||\n \t    msg_len > bp->max_req_len) {\n@@ -182,19 +186,19 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,\n  *\n  * HWRM_UNLOCK() must be called after all response processing is completed.\n  */\n-#define HWRM_PREP(req, type, kong) do { \\\n+#define HWRM_PREP(req, type, kong) do {\t\\\n \trte_spinlock_lock(&bp->hwrm_lock); \\\n \tif (bp->hwrm_cmd_resp_addr == NULL) { \\\n \t\trte_spinlock_unlock(&bp->hwrm_lock); \\\n \t\treturn -EACCES; \\\n \t} \\\n \tmemset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \\\n-\treq.req_type = rte_cpu_to_le_16(HWRM_##type); \\\n-\treq.cmpl_ring = rte_cpu_to_le_16(-1); \\\n-\treq.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\\\n-\t\trte_cpu_to_le_16(bp->hwrm_cmd_seq++); \\\n-\treq.target_id = rte_cpu_to_le_16(0xffff); \\\n-\treq.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \\\n+\t(req)->req_type = rte_cpu_to_le_16(type); \\\n+\t(req)->cmpl_ring = rte_cpu_to_le_16(-1); \\\n+\t(req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\\\n+\t\trte_cpu_to_le_16(bp->chimp_cmd_seq++); \\\n+\t(req)->target_id = rte_cpu_to_le_16(0xffff); \\\n+\t(req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \\\n } while (0)\n \n #define HWRM_CHECK_RESULT_SILENT() do {\\\n@@ -263,7 +267,7 @@ int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \tstruct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };\n \tstruct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);\n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \treq.mask = 0;\n \n@@ -288,7 +292,7 @@ int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,\n \tif (vnic->fw_vnic_id == INVALID_HW_RING_ID)\n \t\treturn rc;\n \n-\tHWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);\n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \n \tif (vnic->flags & BNXT_VNIC_INFO_BCAST)\n@@ -347,7 +351,7 @@ int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,\n \t\t\t\treturn 0;\n \t\t}\n \t}\n-\tHWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(fid);\n \n \treq.vlan_tag_mask_tbl_addr =\n@@ -389,7 +393,7 @@ int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,\n \tif (l2_filter->l2_ref_cnt > 0)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);\n \n@@ -440,7 +444,7 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp,\n \tif (filter->fw_l2_filter_id != UINT64_MAX)\n \t\tbnxt_hwrm_clear_l2_filter(bp, filter);\n \n-\tHWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);\n \n \treq.flags = rte_cpu_to_le_32(filter->flags);\n \n@@ -503,7 +507,7 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)\n \tif (!ptp)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (ptp->rx_filter)\n \t\tflags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;\n@@ -536,7 +540,7 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)\n \tif (ptp)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);\n \n \treq.port_id = rte_cpu_to_le_16(bp->pf.port_id);\n \n@@ -591,7 +595,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \tuint32_t flags;\n \tint i;\n \n-\tHWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(0xffff);\n \n@@ -721,7 +725,7 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)\n \tstruct hwrm_vnic_qcaps_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);\n \n \treq.target_id = rte_cpu_to_le_16(0xffff);\n \n@@ -748,7 +752,7 @@ int bnxt_hwrm_func_reset(struct bnxt *bp)\n \tstruct hwrm_func_reset_input req = {.req_type = 0 };\n \tstruct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);\n \n \treq.enables = rte_cpu_to_le_32(0);\n \n@@ -781,7 +785,7 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp)\n \tif ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))\n \t\tflags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;\n \n-\tHWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);\n \treq.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |\n \t\t\tHWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);\n \treq.ver_maj = RTE_VER_YEAR;\n@@ -853,7 +857,7 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)\n \tstruct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tstruct hwrm_func_vf_cfg_input req = {0};\n \n-\tHWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n \n \tenables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |\n \t\t  HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |\n@@ -919,7 +923,7 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)\n \tstruct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;\n \tstruct hwrm_func_resource_qcaps_input req = {0};\n \n-\tHWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(0xffff);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -964,7 +968,7 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)\n \n \tbp->max_req_len = HWRM_MAX_REQ_LEN;\n \tbp->hwrm_cmd_timeout = timeout;\n-\tHWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);\n \n \treq.hwrm_intf_maj = HWRM_VERSION_MAJOR;\n \treq.hwrm_intf_min = HWRM_VERSION_MINOR;\n@@ -1104,7 +1108,7 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)\n \tif (!(bp->flags & BNXT_FLAG_REGISTERED))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);\n \treq.flags = flags;\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -1122,7 +1126,7 @@ static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)\n \tstruct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tuint32_t enables = 0;\n \n-\tHWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (conf->link_up) {\n \t\t/* Setting Fixed Speed. But AutoNeg is ON, So disable it */\n@@ -1186,7 +1190,7 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,\n \tstruct hwrm_port_phy_qcfg_input req = {0};\n \tstruct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -1265,7 +1269,7 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)\n \tint i;\n \n get_rx_info:\n-\tHWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);\n \n \treq.flags = rte_cpu_to_le_32(dir);\n \t/* HWRM Version >= 1.9.1 only if COS Classification is not required. */\n@@ -1353,7 +1357,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,\n \tstruct rte_mempool *mb_pool;\n \tuint16_t rx_buf_size;\n \n-\tHWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);\n \n \treq.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);\n \treq.fbo = rte_cpu_to_le_32(0);\n@@ -1477,7 +1481,7 @@ int bnxt_hwrm_ring_free(struct bnxt *bp,\n \tstruct hwrm_ring_free_input req = {.req_type = 0 };\n \tstruct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.ring_type = ring_type;\n \treq.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);\n@@ -1525,7 +1529,7 @@ int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)\n \tstruct hwrm_ring_grp_alloc_input req = {.req_type = 0 };\n \tstruct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);\n \n \treq.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);\n \treq.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);\n@@ -1549,7 +1553,7 @@ int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)\n \tstruct hwrm_ring_grp_free_input req = {.req_type = 0 };\n \tstruct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);\n \n@@ -1571,7 +1575,7 @@ int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)\n \tif (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)\n \t\treturn rc;\n \n-\tHWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);\n \n \treq.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);\n \n@@ -1590,7 +1594,7 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,\n \tstruct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };\n \tstruct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);\n \n \treq.update_period_ms = rte_cpu_to_le_32(0);\n \n@@ -1614,7 +1618,7 @@ int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,\n \tstruct hwrm_stat_ctx_free_input req = {.req_type = 0 };\n \tstruct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);\n \n@@ -1648,7 +1652,7 @@ int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \n skip_ring_grps:\n \tvnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);\n-\tHWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);\n \n \tif (vnic->func_default)\n \t\treq.flags =\n@@ -1671,7 +1675,7 @@ static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,\n \tstruct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);\n \n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \n@@ -1704,7 +1708,7 @@ static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,\n \t\treturn rc;\n \t}\n \n-\tHWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \treq.flags = rte_cpu_to_le_32(pmode->flags);\n@@ -1743,7 +1747,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \tif (rc)\n \t\treturn rc;\n \n-\tHWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (BNXT_CHIP_THOR(bp)) {\n \t\tint dflt_rxq = vnic->start_grp_id;\n@@ -1847,7 +1851,7 @@ int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,\n \t\tPMD_DRV_LOG(DEBUG, \"VNIC QCFG ID %d\\n\", vnic->fw_vnic_id);\n \t\treturn rc;\n \t}\n-\tHWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);\n \n \treq.enables =\n \t\trte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);\n@@ -1890,7 +1894,7 @@ int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,\n \tstruct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =\n \t\t\t\t\t\tbp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -1919,7 +1923,7 @@ int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,\n \t\tPMD_DRV_LOG(DEBUG, \"VNIC RSS Rule %x\\n\", vnic->rss_rule);\n \t\treturn rc;\n \t}\n-\tHWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);\n \n@@ -1964,7 +1968,7 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \t\treturn rc;\n \t}\n \n-\tHWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \n@@ -1991,7 +1995,7 @@ bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n \tfor (i = 0; i < nr_ctxs; i++) {\n-\t\tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n+\t\tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \t\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \t\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n@@ -2029,7 +2033,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \tif (BNXT_CHIP_THOR(bp))\n \t\treturn bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);\n \n-\tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n \treq.hash_mode_flags = vnic->hash_mode;\n@@ -2062,7 +2066,7 @@ int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,\n \t\treturn rc;\n \t}\n \n-\tHWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.flags = rte_cpu_to_le_32(\n \t\t\tHWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);\n@@ -2103,7 +2107,7 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,\n \t\treturn 0;\n \t}\n \n-\tHWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (enable) {\n \t\treq.enables = rte_cpu_to_le_32(\n@@ -2143,7 +2147,7 @@ int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)\n \tmemcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));\n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -2161,7 +2165,7 @@ int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,\n \tstruct hwrm_func_qstats_input req = {.req_type = 0};\n \tstruct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(fid);\n \n@@ -2184,7 +2188,7 @@ int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,\n \tstruct hwrm_func_qstats_input req = {.req_type = 0};\n \tstruct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(fid);\n \n@@ -2221,7 +2225,7 @@ int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)\n \tstruct hwrm_func_clr_stats_input req = {.req_type = 0};\n \tstruct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(fid);\n \n@@ -2928,7 +2932,7 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)\n \tuint16_t flags;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(0xffff);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -3037,7 +3041,7 @@ static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)\n \treq.fid = rte_cpu_to_le_16(0xffff);\n \treq.enables = rte_cpu_to_le_32(enables);\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3109,7 +3113,7 @@ static int reserve_resources_from_vf(struct bnxt *bp,\n \tint rc;\n \n \t/* Get the actual allocated values now */\n-\tHWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3147,7 +3151,7 @@ int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)\n \tint rc;\n \n \t/* Check for zero MAC address */\n-\tHWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -3165,7 +3169,7 @@ static int update_pf_resource_max(struct bnxt *bp)\n \tint rc;\n \n \t/* And copy the allocated numbers into the pf struct */\n-\tHWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);\n \treq.fid = rte_cpu_to_le_16(0xffff);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -3268,7 +3272,7 @@ int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)\n \tfor (i = 0; i < num_vfs; i++) {\n \t\tadd_random_mac_if_needed(bp, &req, i);\n \n-\t\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\t\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \t\treq.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);\n \t\treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);\n \t\trc = bnxt_hwrm_send_message(bp,\n@@ -3324,7 +3328,7 @@ int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)\n \tstruct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(0xffff);\n \treq.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);\n@@ -3344,7 +3348,7 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,\n \tstruct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);\n \treq.tunnel_type = tunnel_type;\n \treq.tunnel_dst_port_val = port;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -3375,7 +3379,7 @@ int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,\n \tstruct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.tunnel_type = tunnel_type;\n \treq.tunnel_dst_port_id = rte_cpu_to_be_16(port);\n@@ -3394,7 +3398,7 @@ int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,\n \tstruct hwrm_func_cfg_input req = {0};\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \treq.flags = rte_cpu_to_le_32(flags);\n@@ -3424,7 +3428,7 @@ int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)\n \tstruct hwrm_func_buf_rgtr_input req = {.req_type = 0 };\n \tstruct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);\n \n \treq.req_buf_num_pages = rte_cpu_to_le_16(1);\n \treq.req_buf_page_size = rte_cpu_to_le_16(\n@@ -3455,7 +3459,7 @@ int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)\n \tif (!(BNXT_PF(bp) && bp->pdev->max_vfs))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3471,7 +3475,7 @@ int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)\n \tstruct hwrm_func_cfg_input req = {0};\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(0xffff);\n \treq.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);\n@@ -3493,7 +3497,7 @@ int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)\n \tstruct hwrm_func_vf_cfg_input req = {0};\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.enables = rte_cpu_to_le_32(\n \t\t\tHWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);\n@@ -3515,7 +3519,7 @@ int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)\n \tuint32_t func_cfg_flags;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (is_vf) {\n \t\tdflt_vlan = bp->pf.vf_info[vf].dflt_vlan;\n@@ -3547,7 +3551,7 @@ int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,\n \tstruct hwrm_func_cfg_input req = {0};\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \treq.enables |= rte_cpu_to_le_32(enables);\n@@ -3567,7 +3571,7 @@ int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)\n \tstruct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);\n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n@@ -3604,7 +3608,7 @@ int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,\n \tif (ec_size > sizeof(req.encap_request))\n \t\treturn -1;\n \n-\tHWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);\n \n \treq.encap_resp_target_id = rte_cpu_to_le_16(target_id);\n \tmemcpy(req.encap_request, encaped, ec_size);\n@@ -3624,7 +3628,7 @@ int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,\n \tstruct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -3648,7 +3652,7 @@ int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,\n \tif (ec_size > sizeof(req.encap_request))\n \t\treturn -1;\n \n-\tHWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);\n \n \treq.encap_resp_target_id = rte_cpu_to_le_16(target_id);\n \tmemcpy(req.encap_request, encaped, ec_size);\n@@ -3668,7 +3672,7 @@ int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,\n \tstruct hwrm_stat_ctx_query_input req = {.req_type = 0};\n \tstruct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);\n \n \treq.stat_ctx_id = rte_cpu_to_le_32(cid);\n \n@@ -3706,7 +3710,7 @@ int bnxt_hwrm_port_qstats(struct bnxt *bp)\n \tstruct bnxt_pf_info *pf = &bp->pf;\n \tint rc;\n \n-\tHWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);\n \n \treq.port_id = rte_cpu_to_le_16(pf->port_id);\n \treq.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);\n@@ -3731,7 +3735,7 @@ int bnxt_hwrm_port_clr_stats(struct bnxt *bp)\n \t    BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);\n \n \treq.port_id = rte_cpu_to_le_16(pf->port_id);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -3751,7 +3755,7 @@ int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)\n \tif (BNXT_VF(bp))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);\n \treq.port_id = bp->pf.port_id;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3793,7 +3797,7 @@ int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)\n \tif (!bp->num_leds || BNXT_VF(bp))\n \t\treturn -EOPNOTSUPP;\n \n-\tHWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);\n \n \tif (led_on) {\n \t\tled_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;\n@@ -3826,7 +3830,7 @@ int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,\n \tstruct hwrm_nvm_get_dir_info_input req = {0};\n \tstruct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3869,7 +3873,7 @@ int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)\n \t\t\t\"unable to map response address to physical memory\\n\");\n \t\treturn -ENOMEM;\n \t}\n-\tHWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);\n \treq.host_dest_addr = rte_cpu_to_le_64(dma_handle);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -3903,7 +3907,7 @@ int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,\n \t\t\t\"unable to map response address to physical memory\\n\");\n \t\treturn -ENOMEM;\n \t}\n-\tHWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);\n \treq.host_dest_addr = rte_cpu_to_le_64(dma_handle);\n \treq.dir_idx = rte_cpu_to_le_16(index);\n \treq.offset = rte_cpu_to_le_32(offset);\n@@ -3925,7 +3929,7 @@ int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)\n \tstruct hwrm_nvm_erase_dir_entry_input req = {0};\n \tstruct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tHWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);\n \treq.dir_idx = rte_cpu_to_le_16(index);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -3958,7 +3962,7 @@ int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,\n \t}\n \tmemcpy(buf, data, data_len);\n \n-\tHWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);\n \n \treq.dir_type = rte_cpu_to_le_16(dir_type);\n \treq.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);\n@@ -4009,7 +4013,7 @@ static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,\n \tint rc;\n \n \t/* First query all VNIC ids */\n-\tHWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);\n \n \treq.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);\n \treq.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);\n@@ -4091,7 +4095,7 @@ int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,\n \tstruct hwrm_func_cfg_input req = {0};\n \tint rc;\n \n-\tHWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);\n \treq.enables |= rte_cpu_to_le_32(\n@@ -4166,7 +4170,7 @@ int bnxt_hwrm_set_em_filter(struct bnxt *bp,\n \tif (filter->fw_em_filter_id != UINT64_MAX)\n \t\tbnxt_hwrm_clear_em_filter(bp, filter);\n \n-\tHWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));\n+\tHWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));\n \n \treq.flags = rte_cpu_to_le_32(filter->flags);\n \n@@ -4238,7 +4242,7 @@ int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)\n \tif (filter->fw_em_filter_id == UINT64_MAX)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));\n+\tHWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));\n \n \treq.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);\n \n@@ -4266,7 +4270,7 @@ int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,\n \tif (filter->fw_ntuple_filter_id != UINT64_MAX)\n \t\tbnxt_hwrm_clear_ntuple_filter(bp, filter);\n \n-\tHWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);\n \n \treq.flags = rte_cpu_to_le_32(filter->flags);\n \n@@ -4346,7 +4350,7 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,\n \tif (filter->fw_ntuple_filter_id == UINT64_MAX)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);\n \n \treq.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);\n \n@@ -4377,7 +4381,7 @@ bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \t\tstruct bnxt_rx_ring_info *rxr;\n \t\tstruct bnxt_cp_ring_info *cpr;\n \n-\t\tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n+\t\tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \t\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \t\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n@@ -4509,7 +4513,7 @@ static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,\n \tuint16_t flags;\n \tint rc;\n \n-\tHWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n \n@@ -4546,7 +4550,7 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp,\n \t\treturn 0;\n \t}\n \n-\tHWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);\n \treq.ring_id = rte_cpu_to_le_16(ring_id);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -4571,7 +4575,7 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n \t    bp->ctx)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT_SILENT();\n \n@@ -4650,7 +4654,7 @@ int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)\n \tif (!ctx)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);\n \treq.enables = rte_cpu_to_le_32(enables);\n \n \tif (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {\n@@ -4743,7 +4747,7 @@ int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)\n \t      bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);\n \n \treq.port_id = rte_cpu_to_le_16(pf->port_id);\n \tif (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {\n@@ -4784,7 +4788,7 @@ bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)\n \t\tbp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);\n \treq.tunnel_type = type;\n \treq.dest_fid = bp->fw_fid;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -4803,7 +4807,7 @@ bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)\n \t\tbp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);\n \treq.tunnel_type = type;\n \treq.dest_fid = bp->fw_fid;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -4821,7 +4825,7 @@ int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)\n \t\tbp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);\n \treq.src_fid = bp->fw_fid;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT();\n@@ -4842,7 +4846,7 @@ int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,\n \t\tbp->hwrm_cmd_resp_addr;\n \tint rc = 0;\n \n-\tHWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);\n \treq.src_fid = bp->fw_fid;\n \treq.tunnel_type = tun_type;\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n@@ -4867,7 +4871,7 @@ int bnxt_hwrm_set_mac(struct bnxt *bp)\n \tif (!BNXT_VF(bp))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.enables =\n \t\trte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);\n@@ -4900,7 +4904,7 @@ int bnxt_hwrm_if_change(struct bnxt *bp, bool up)\n \tif (!up && (bp->flags & BNXT_FLAG_FW_RESET))\n \t\treturn 0;\n \n-\tHWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);\n \n \tif (up)\n \t\treq.flags =\n@@ -4946,7 +4950,7 @@ int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)\n \t\tmemset(info, 0, sizeof(*info));\n \t}\n \n-\tHWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n@@ -5022,7 +5026,7 @@ int bnxt_hwrm_fw_reset(struct bnxt *bp)\n \tif (!BNXT_PF(bp))\n \t\treturn -EOPNOTSUPP;\n \n-\tHWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));\n+\tHWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));\n \n \treq.embedded_proc_type =\n \t\tHWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;\n@@ -5050,7 +5054,7 @@ int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)\n \tif (!ptp)\n \t\treturn 0;\n \n-\tHWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);\n+\tHWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);\n \n \tswitch (path) {\n \tcase BNXT_PTP_FLAGS_PATH_TX:\n@@ -5098,7 +5102,7 @@ int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)\n \t\treturn 0;\n \t}\n \n-\tHWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));\n+\tHWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));\n \n \tHWRM_CHECK_RESULT();\n",
    "prefixes": [
        "02/33"
    ]
}