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GET /api/patches/6659/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 6659,
    "url": "https://patches.dpdk.org/api/patches/6659/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/2601191342CEEE43887BDE71AB97725836A69E3D@irsmsx105.ger.corp.intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<2601191342CEEE43887BDE71AB97725836A69E3D@irsmsx105.ger.corp.intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/2601191342CEEE43887BDE71AB97725836A69E3D@irsmsx105.ger.corp.intel.com",
    "date": "2015-07-29T18:12:15",
    "name": "[dpdk-dev] Issue with non-scattered rx in ixgbe and i40e when mbuf private area size is odd",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "4f856a3dbb30541dbc7391fbbc5d2b0e016d3675",
    "submitter": {
        "id": 33,
        "url": "https://patches.dpdk.org/api/people/33/?format=api",
        "name": "Ananyev, Konstantin",
        "email": "konstantin.ananyev@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/2601191342CEEE43887BDE71AB97725836A69E3D@irsmsx105.ger.corp.intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/6659/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/6659/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0D673C390;\n\tWed, 29 Jul 2015 20:12:22 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 744ECC372\n\tfor <dev@dpdk.org>; Wed, 29 Jul 2015 20:12:19 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP; 29 Jul 2015 11:12:17 -0700",
            "from irsmsx110.ger.corp.intel.com ([163.33.3.25])\n\tby orsmga001.jf.intel.com with ESMTP; 29 Jul 2015 11:12:16 -0700",
            "from irsmsx105.ger.corp.intel.com ([169.254.7.223]) by\n\tirsmsx110.ger.corp.intel.com ([169.254.15.29]) with mapi id\n\t14.03.0224.002; Wed, 29 Jul 2015 19:12:15 +0100"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.15,572,1432623600\"; d=\"scan'208\";a=\"738064036\"",
        "From": "\"Ananyev, Konstantin\" <konstantin.ananyev@intel.com>",
        "To": "Martin Weiser <martin.weiser@allegro-packets.com>, \"Zhang, Helin\"\n\t<helin.zhang@intel.com>,\n\t\"olivier.matz@6wind.com\" <olivier.matz@6wind.com>",
        "Thread-Topic": "[dpdk-dev] Issue with non-scattered rx in ixgbe and i40e when\n\tmbuf private area size is odd",
        "Thread-Index": "AQHQyhBbcJ5kz811kUqP+U4E1qdbJZ3ymcUg",
        "Date": "Wed, 29 Jul 2015 18:12:15 +0000",
        "Message-ID": "<2601191342CEEE43887BDE71AB97725836A69E3D@irsmsx105.ger.corp.intel.com>",
        "References": "<55B8EC16.60404@allegro-packets.com>",
        "In-Reply-To": "<55B8EC16.60404@allegro-packets.com>",
        "Accept-Language": "en-IE, en-US",
        "Content-Language": "en-US",
        "X-MS-Has-Attach": "",
        "X-MS-TNEF-Correlator": "",
        "x-originating-ip": "[163.33.239.182]",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "base64",
        "MIME-Version": "1.0",
        "Cc": "\"dev@dpdk.org\" <dev@dpdk.org>",
        "Subject": "Re: [dpdk-dev] Issue with non-scattered rx in ixgbe and i40e when\n\tmbuf private area size is odd",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Hi Martin,\r\n\r\n> -----Original Message-----\r\n> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Martin Weiser\r\n> Sent: Wednesday, July 29, 2015 4:07 PM\r\n> To: Zhang, Helin; olivier.matz@6wind.com\r\n> Cc: dev@dpdk.org\r\n> Subject: [dpdk-dev] Issue with non-scattered rx in ixgbe and i40e when mbuf private area size is odd\r\n> \r\n> Hi Helin, Hi Olivier,\r\n> \r\n> we are seeing an issue with the ixgbe and i40e drivers which we could\r\n> track down to our setting of the private area size of the mbufs.\r\n> The issue can be easily reproduced with the l2fwd example application\r\n> when a small modification is done: just set the priv_size parameter in\r\n> the call to the rte_pktmbuf_pool_create function to an odd number like\r\n> 1. In our tests this causes every call to rte_eth_rx_burst to return 32\r\n> (which is the setting of nb_pkts) nonsense mbufs although no packets are\r\n> received on the interface and the hardware counters do not report any\r\n> received packets.\r\n\r\nFrom Niantic datasheet:\r\n\r\n\"7.1.6.1 Advanced Receive Descriptors — Read Format\r\nTable 7-15 lists the advanced receive descriptor programming by the software. The\r\n...\r\nPacket Buffer Address (64)\r\nThis is the physical address of the packet buffer. The lowest bit is A0 (LSB of the\r\naddress).\r\nHeader Buffer Address (64)\r\nThe physical address of the header buffer with the lowest bit being Descriptor Done (DD).\r\nWhen a packet spans in multiple descriptors, the header buffer address is used only on\r\nthe first descriptor. During the programming phase, software must set the DD bit to zero\r\n(see the description of the DD bit in this section). This means that header buffer\r\naddresses are always word aligned.\"\r\n\r\nRight now, in ixgbe PMD we always setup  Packet Buffer Address (PBA)and Header Buffer Address (HBA) to the same value:\r\nbuf_physaddr + RTE_PKTMBUF_HEADROOM\r\nSo when pirv_size==1, DD bit in RXD is always set to one by SW itself, and then SW considers that HW already done with it.\r\nIn other words, right now for ixgbe you can't use RX buffer that is not aligned on word boundary.\r\n\r\nSo the advice would be, right now - don't set priv_size to the odd value.\r\nAs we don't support split header feature anyway, I think we can fix it just by  always setting HBA in the RXD to zero.\r\nCould you try the fix for ixgbe below?\r\n\r\nSame story with FVL, I believe.\r\nKonstantin\r\n\r\n\r\n> Interestingly this does not happen if we force the scattered rx path.\r\n> \r\n> I assume the drivers have some expectations regarding the alignment of\r\n> the buf_addr in the mbuf and setting an odd private are size breaks this\r\n> alignment in the rte_pktmbuf_init function. If this is the case then one\r\n> possible fix might be to enforce an alignment on the private area size.\r\n> \r\n> Best regards,\r\n> Martin",
    "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\r\nindex a0c8847..94967c5 100644\r\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\r\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\r\n@@ -1183,7 +1183,7 @@ ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)\r\n\r\n                /* populate the descriptors */\r\n                dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\r\n-               rxdp[i].read.hdr_addr = dma_addr;\r\n+               rxdp[i].read.hdr_addr = 0;\r\n                rxdp[i].read.pkt_addr = dma_addr;\r\n        }\r\n\r\n@@ -1414,7 +1414,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n                rxe->mbuf = nmb;\r\n                dma_addr =\r\n                        rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\r\n-               rxdp->read.hdr_addr = dma_addr;\r\n+               rxdp->read.hdr_addr = 0;\r\n                rxdp->read.pkt_addr = dma_addr;\r\n\r\n                /*\r\n@@ -1741,7 +1741,7 @@ next_desc:\r\n                        rxe->mbuf = nmb;\r\n\r\n                        rxm->data_off = RTE_PKTMBUF_HEADROOM;\r\n-                       rxdp->read.hdr_addr = dma;\r\n+                       rxdp->read.hdr_addr = 0;\r\n                        rxdp->read.pkt_addr = dma;\r\n                } else\r\n                        rxe->mbuf = NULL;\r\n@@ -3633,7 +3633,7 @@ ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)\r\n                dma_addr =\r\n                        rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\r\n                rxd = &rxq->rx_ring[i];\r\n-               rxd->read.hdr_addr = dma_addr;\r\n+               rxd->read.hdr_addr = 0;\r\n                rxd->read.pkt_addr = dma_addr;\r\n                rxe[i].mbuf = mbuf;\r\n        }\r\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec.c b/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\nindex 6c1647e..16a9c64 100644\r\n--- a/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\n+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\n@@ -56,6 +56,8 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\r\n                        RTE_PKTMBUF_HEADROOM);\r\n        __m128i dma_addr0, dma_addr1;\r\n\r\n+       const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);\r\n+\r\n        rxdp = rxq->rx_ring + rxq->rxrearm_start;\r\n\r\n        /* Pull 'n' more MBUFs into the software ring */\r\n@@ -108,6 +110,9 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\r\n                dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\r\n                dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\r\n\r\n+               dma_addr0 =  _mm_and_si128(dma_addr0, hba_msk);\r\n+               dma_addr1 =  _mm_and_si128(dma_addr1, hba_msk);\r\n+\r\n                /* flush desc with pa dma_addr */\r\n                _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\r\n                _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\r\nbash-4.2$ cat patch1\r\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\r\nindex a0c8847..94967c5 100644\r\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\r\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\r\n@@ -1183,7 +1183,7 @@ ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)\r\n\r\n                /* populate the descriptors */\r\n                dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\r\n-               rxdp[i].read.hdr_addr = dma_addr;\r\n+               rxdp[i].read.hdr_addr = 0;\r\n                rxdp[i].read.pkt_addr = dma_addr;\r\n        }\r\n\r\n@@ -1414,7 +1414,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\r\n                rxe->mbuf = nmb;\r\n                dma_addr =\r\n                        rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\r\n-               rxdp->read.hdr_addr = dma_addr;\r\n+               rxdp->read.hdr_addr = 0;\r\n                rxdp->read.pkt_addr = dma_addr;\r\n\r\n                /*\r\n@@ -1741,7 +1741,7 @@ next_desc:\r\n                        rxe->mbuf = nmb;\r\n\r\n                        rxm->data_off = RTE_PKTMBUF_HEADROOM;\r\n-                       rxdp->read.hdr_addr = dma;\r\n+                       rxdp->read.hdr_addr = 0;\r\n                        rxdp->read.pkt_addr = dma;\r\n                } else\r\n                        rxe->mbuf = NULL;\r\n@@ -3633,7 +3633,7 @@ ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)\r\n                dma_addr =\r\n                        rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\r\n                rxd = &rxq->rx_ring[i];\r\n-               rxd->read.hdr_addr = dma_addr;\r\n+               rxd->read.hdr_addr = 0;\r\n                rxd->read.pkt_addr = dma_addr;\r\n                rxe[i].mbuf = mbuf;\r\n        }\r\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec.c b/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\nindex 6c1647e..16a9c64 100644\r\n--- a/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\n+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec.c\r\n@@ -56,6 +56,8 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\r\n                        RTE_PKTMBUF_HEADROOM);\r\n        __m128i dma_addr0, dma_addr1;\r\n\r\n+       const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);\r\n+\r\n        rxdp = rxq->rx_ring + rxq->rxrearm_start;\r\n\r\n        /* Pull 'n' more MBUFs into the software ring */\r\n@@ -108,6 +110,9 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\r\n                dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\r\n                dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\r\n\r\n+               dma_addr0 =  _mm_and_si128(dma_addr0, hba_msk);\r\n+               dma_addr1 =  _mm_and_si128(dma_addr1, hba_msk);\r\n+\r\n                /* flush desc with pa dma_addr */\r\n                _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\r\n                _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\r\n",
    "prefixes": [
        "dpdk-dev"
    ]
}