Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/66385/?format=api
{ "id": 66385, "url": "https://patches.dpdk.org/api/patches/66385/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1583742247-370386-7-git-send-email-alvinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1583742247-370386-7-git-send-email-alvinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1583742247-370386-7-git-send-email-alvinx.zhang@intel.com", "date": "2020-03-09T08:23:59", "name": "[v1,07/15] net/igc: enable Rx queue interrupts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a2c84c06fd624fe580b916da6843186c9a1e86c3", "submitter": { "id": 1398, "url": "https://patches.dpdk.org/api/people/1398/?format=api", "name": "Alvin Zhang", "email": "alvinx.zhang@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1583742247-370386-7-git-send-email-alvinx.zhang@intel.com/mbox/", "series": [ { "id": 8831, "url": "https://patches.dpdk.org/api/series/8831/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=8831", "date": "2020-03-09T08:23:53", "name": "[v1,01/15] net/igc: add igc PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/8831/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/66385/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/66385/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7876CA052E;\n\tMon, 9 Mar 2020 09:29:47 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 94F041C07B;\n\tMon, 9 Mar 2020 09:29:04 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id A58031C069\n for <dev@dpdk.org>; Mon, 9 Mar 2020 09:29:02 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 01:29:02 -0700", "from unknown (HELO dpdk-zhangalvin-dev.sh.intel.com)\n ([10.240.179.50])\n by orsmga002.jf.intel.com with ESMTP; 09 Mar 2020 01:29:00 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,518,1574150400\"; d=\"scan'208\";a=\"260350731\"", "From": "alvinx.zhang@intel.com", "To": "dev@dpdk.org", "Cc": "haiyue.wang@intel.com, xiaolong.ye@intel.com, qi.z.zhang@intel.com,\n beilei.xing@intel.com, Alvin Zhang <alvinx.zhang@intel.com>", "Date": "Mon, 9 Mar 2020 16:23:59 +0800", "Message-Id": "<1583742247-370386-7-git-send-email-alvinx.zhang@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1583742247-370386-1-git-send-email-alvinx.zhang@intel.com>", "References": "<1583742247-370386-1-git-send-email-alvinx.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v1 07/15] net/igc: enable Rx queue interrupts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Alvin Zhang <alvinx.zhang@intel.com>\n\nSetup NIC to generate MSI-X interrupts.\nSet the IVAR register to map interrupt causes to vectors.\nImplement interrupt enable/disable functions.\n\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\n---\n doc/guides/nics/features/igc.ini | 1 +\n drivers/net/igc/igc_ethdev.c | 170 ++++++++++++++++++++++++++++++++++++++-\n drivers/net/igc/igc_ethdev.h | 2 +-\n 3 files changed, 168 insertions(+), 5 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/igc.ini b/doc/guides/nics/features/igc.ini\nindex 9ba817d..79bfb2d 100644\n--- a/doc/guides/nics/features/igc.ini\n+++ b/doc/guides/nics/features/igc.ini\n@@ -25,6 +25,7 @@ L4 checksum offload = Y\n Basic stats = Y\n Extended stats = Y\n Stats per queue = Y\n+Rx interrupt = Y\n Linux UIO = Y\n Linux VFIO = Y\n x86-64 = Y\ndiff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c\nindex 6f03ad1..0a5d37e 100644\n--- a/drivers/net/igc/igc_ethdev.c\n+++ b/drivers/net/igc/igc_ethdev.c\n@@ -203,6 +203,10 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n static int\n eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev,\n \tuint16_t queue_id, uint8_t stat_idx, uint8_t is_rx);\n+static int\n+eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);\n+static int\n+eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);\n \n static const struct eth_dev_ops eth_igc_ops = {\n \t.dev_configure\t\t= eth_igc_configure,\n@@ -247,6 +251,8 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t.stats_reset\t\t= eth_igc_xstats_reset,\n \t.xstats_reset\t\t= eth_igc_xstats_reset,\n \t.queue_stats_mapping_set = eth_igc_queue_stats_mapping_set,\n+\t.rx_queue_intr_enable\t= eth_igc_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable\t= eth_igc_rx_queue_intr_disable,\n };\n \n /*\n@@ -612,6 +618,56 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \n \t/* Clean datapath event and queue/vec mapping */\n \trte_intr_efd_disable(intr_handle);\n+\tif (intr_handle->intr_vec != NULL) {\n+\t\trte_free(intr_handle->intr_vec);\n+\t\tintr_handle->intr_vec = NULL;\n+\t}\n+}\n+\n+/*\n+ * write interrupt vector allocation register\n+ * @hw\n+ * board private structure\n+ * @queue_index\n+ * queue index, valid 0,1,2,3\n+ * @tx\n+ * tx:1, rx:0\n+ * @msix_vector\n+ * msix-vector, valid 0,1,2,3,4\n+ */\n+static void\n+igc_write_ivar(struct igc_hw *hw, uint8_t queue_index,\n+\t\tbool tx, uint8_t msix_vector)\n+{\n+\tuint8_t offset = 0;\n+\tuint8_t reg_index = queue_index >> 1;\n+\tuint32_t val;\n+\n+\t/*\n+\t * IVAR(0)\n+\t * bit31...24\tbit23...16\tbit15...8\tbit7...0\n+\t * TX1\t\tRX1\t\tTX0\t\tRX0\n+\t *\n+\t * IVAR(1)\n+\t * bit31...24\tbit23...16\tbit15...8\tbit7...0\n+\t * TX3\t\tRX3\t\tTX2\t\tRX2\n+\t */\n+\n+\tif (tx)\n+\t\toffset = 8;\n+\n+\tif (queue_index & 1)\n+\t\toffset += 16;\n+\n+\tval = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, reg_index);\n+\n+\t/* clear bits */\n+\tval &= ~((uint32_t)0xFF << offset);\n+\n+\t/* write vector and valid bit */\n+\tval |= (msix_vector | IGC_IVAR_VALID) << offset;\n+\n+\tIGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, reg_index, val);\n }\n \n /* Sets up the hardware to generate MSI-X interrupts properly\n@@ -626,20 +682,32 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \n \tuint32_t intr_mask;\n+\tuint32_t vec = IGC_MISC_VEC_ID;\n+\tuint32_t base = IGC_MISC_VEC_ID;\n+\tuint32_t misc_shift = 0;\n+\tint i;\n \n \t/* won't configure msix register if no mapping is done\n \t * between intr vector and event fd\n \t */\n-\tif (!rte_intr_dp_is_en(intr_handle) ||\n-\t\t!dev->data->dev_conf.intr_conf.lsc)\n+\tif (!rte_intr_dp_is_en(intr_handle))\n \t\treturn;\n \n+\tif (rte_intr_allow_others(intr_handle)) {\n+\t\tbase = IGC_RX_VEC_START;\n+\t\tvec = base;\n+\t\tmisc_shift = 1;\n+\t}\n+\n \t/* turn on MSI-X capability first */\n \tIGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE |\n \t\t\t\tIGC_GPIE_PBA | IGC_GPIE_EIAME |\n \t\t\t\tIGC_GPIE_NSICR);\n+\tintr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<\n+\t\tmisc_shift;\n \n-\tintr_mask = (1 << IGC_MSIX_OTHER_INTR_VEC);\n+\tif (dev->data->dev_conf.intr_conf.lsc)\n+\t\tintr_mask |= (1 << IGC_MSIX_OTHER_INTR_VEC);\n \n \t/* enable msix auto-clear */\n \tigc_read_reg_check_set_bits(hw, IGC_EIAC, intr_mask);\n@@ -651,6 +719,13 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t/* enable auto-mask */\n \tigc_read_reg_check_set_bits(hw, IGC_EIAM, intr_mask);\n \n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tigc_write_ivar(hw, i, 0, vec);\n+\t\tintr_handle->intr_vec[i] = vec;\n+\t\tif (vec < base + intr_handle->nb_efd - 1)\n+\t\t\tvec++;\n+\t}\n+\n \tIGC_WRITE_FLUSH(hw);\n }\n \n@@ -674,6 +749,29 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n }\n \n /*\n+ * It enables the interrupt.\n+ * It will be called once only during nic initialized.\n+ */\n+static void\n+igc_rxq_interrupt_setup(struct rte_eth_dev *dev)\n+{\n+\tuint32_t mask;\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;\n+\n+\t/* won't configure msix register if no mapping is done\n+\t * between intr vector and event fd\n+\t */\n+\tif (!rte_intr_dp_is_en(intr_handle))\n+\t\treturn;\n+\n+\tmask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift;\n+\tIGC_WRITE_REG(hw, IGC_EIMS, mask);\n+}\n+\n+/*\n * Get hardware rx-buffer size.\n */\n static inline int\n@@ -793,7 +891,25 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t}\n \tadapter->stopped = 0;\n \n-\t/* confiugre msix for rx interrupt */\n+\t/* check and configure queue intr-vector mapping */\n+\tif (rte_intr_cap_multiple(intr_handle) &&\n+\t\tdev->data->dev_conf.intr_conf.rxq) {\n+\t\tuint32_t intr_vector = dev->data->nb_rx_queues;\n+\t\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n+\t\t\treturn -1;\n+\t}\n+\n+\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n+\t\tintr_handle->intr_vec = rte_zmalloc(\"intr_vec\",\n+\t\t\tdev->data->nb_rx_queues * sizeof(int), 0);\n+\t\tif (intr_handle->intr_vec == NULL) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate %d rx_queues\"\n+\t\t\t\t \" intr_vec\", dev->data->nb_rx_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\t/* configure msix for rx interrupt */\n \tigc_configure_msix_intr(dev);\n \n \tigc_tx_init(dev);\n@@ -889,6 +1005,11 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \trte_eal_alarm_set(IGC_ALARM_INTERVAL,\n \t\t\tigc_update_queue_stats_handler, dev);\n \n+\t/* check if rxq interrupt is enabled */\n+\tif (dev->data->dev_conf.intr_conf.rxq &&\n+\t\t\trte_intr_dp_is_en(intr_handle))\n+\t\tigc_rxq_interrupt_setup(dev);\n+\n \t/* resume enabled intr since hw reset */\n \tigc_intr_other_enable(dev);\n \n@@ -1161,6 +1282,7 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t\tigc->txq_stats_map[i] = -1;\n \t\tigc->rxq_stats_map[i] = -1;\n \t}\n+\n \treturn 0;\n \n err_late:\n@@ -1908,6 +2030,46 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n }\n \n static int\n+eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tuint32_t vec = IGC_MISC_VEC_ID;\n+\n+\tif (rte_intr_allow_others(intr_handle))\n+\t\tvec = IGC_RX_VEC_START;\n+\n+\tuint32_t mask = 1 << (queue_id + vec);\n+\n+\tIGC_WRITE_REG(hw, IGC_EIMC, mask);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tuint32_t vec = IGC_MISC_VEC_ID;\n+\n+\tif (rte_intr_allow_others(intr_handle))\n+\t\tvec = IGC_RX_VEC_START;\n+\n+\tuint32_t mask = 1 << (queue_id + vec);\n+\n+\tIGC_WRITE_REG(hw, IGC_EIMS, mask);\n+\tIGC_WRITE_FLUSH(hw);\n+\n+\trte_intr_enable(intr_handle);\n+\n+\treturn 0;\n+}\n+\n+static int\n eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tstruct rte_pci_device *pci_dev)\n {\ndiff --git a/drivers/net/igc/igc_ethdev.h b/drivers/net/igc/igc_ethdev.h\nindex 20738df..557aa81 100644\n--- a/drivers/net/igc/igc_ethdev.h\n+++ b/drivers/net/igc/igc_ethdev.h\n@@ -118,7 +118,7 @@ struct igc_adapter {\n \tint16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];\n \tint16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];\n \n-\tstruct igc_interrupt intr;\n+\tstruct igc_interrupt\tintr;\n \tbool\t\tstopped;\n };\n \n", "prefixes": [ "v1", "07/15" ] }