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GET /api/patches/658/?format=api
{ "id": 658, "url": "https://patches.dpdk.org/api/patches/658/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1412058028-10971-6-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1412058028-10971-6-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1412058028-10971-6-git-send-email-helin.zhang@intel.com", "date": "2014-09-30T06:20:26", "name": "[dpdk-dev,v3,5/7] i40e: add hardware initialization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "761fb0700fa2172456ed35aa3c29ccbde78b7258", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1412058028-10971-6-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/658/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5D6537DDC;\n\tTue, 30 Sep 2014 08:14:10 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 14EA47E1C\n\tfor <dev@dpdk.org>; Tue, 30 Sep 2014 08:14:05 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP; 29 Sep 2014 23:11:22 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 29 Sep 2014 23:20:44 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8U6KgsG003458;\n\tTue, 30 Sep 2014 14:20:42 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8U6KeSx011042; Tue, 30 Sep 2014 14:20:42 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8U6KeXG011038; \n\tTue, 30 Sep 2014 14:20:40 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,625,1406617200\"; d=\"scan'208\";a=\"598618392\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 30 Sep 2014 14:20:26 +0800", "Message-Id": "<1412058028-10971-6-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1412058028-10971-1-git-send-email-helin.zhang@intel.com>", "References": "<1412058028-10971-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 5/7] i40e: add hardware initialization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "As global registers will be reset only after a whole chip reset,\nthose registers might not be in an initial state after each\nlaunching a physical port. The hardware initialization is added\nto put specific global registers into an initial state.\n\nv3 changes:\n* Renamed hardware initialization function.\n* Added initialization of register 'PFQF_CTL_0'.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nAcked-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 78 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 78 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex ee7c9de..f23e0bf 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -209,6 +209,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\t\t\tenum rte_filter_type filter_type,\n \t\t\t\tenum rte_filter_op filter_op,\n \t\t\t\tvoid *arg);\n+static void i40e_hw_init(struct i40e_hw *hw);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];\n@@ -390,6 +391,9 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n \t/* Make sure all is clean before doing PF reset */\n \ti40e_clear_hw(hw);\n \n+\t/* Initialize the hardware */\n+\ti40e_hw_init(hw);\n+\n \t/* Reset here to make sure all is clean for each PF */\n \tret = i40e_pf_reset(hw);\n \tif (ret) {\n@@ -4533,3 +4537,77 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \n \treturn ret;\n }\n+\n+/* Initialization for hash function */\n+static void\n+i40e_hash_function_hw_init(struct i40e_hw *hw)\n+{\n+\tuint32_t i;\n+\tconst struct rte_eth_sym_hash_ena_info sym_hash_ena_info[] = {\n+\t\t{ETH_RSS_NONF_IPV4_UDP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV4_TCP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV4_SCTP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV4_OTHER_SHIFT, 0},\n+\t\t{ETH_RSS_FRAG_IPV4_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV6_UDP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV6_TCP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV6_SCTP_SHIFT, 0},\n+\t\t{ETH_RSS_NONF_IPV6_OTHER_SHIFT, 0},\n+\t\t{ETH_RSS_FRAG_IPV6_SHIFT, 0},\n+\t\t{ETH_RSS_L2_PAYLOAD_SHIFT, 0},\n+\t};\n+\tconst struct rte_eth_filter_swap_info swap_info[] = {\n+\t\t{ETH_RSS_NONF_IPV4_UDP_SHIFT,\n+\t\t\t0x1e, 0x36, 0x04, 0x3a, 0x3c, 0x02},\n+\t\t{ETH_RSS_NONF_IPV4_TCP_SHIFT,\n+\t\t\t0x1e, 0x36, 0x04, 0x3a, 0x3c, 0x02},\n+\t\t{ETH_RSS_NONF_IPV4_SCTP_SHIFT,\n+\t\t\t0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_NONF_IPV4_OTHER_SHIFT,\n+\t\t\t0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_FRAG_IPV4_SHIFT,\n+\t\t\t0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_NONF_IPV6_UDP_SHIFT,\n+\t\t\t0x1a, 0x2a, 0x10, 0x3a, 0x3c, 0x02},\n+\t\t{ETH_RSS_NONF_IPV6_TCP_SHIFT,\n+\t\t\t0x1a, 0x2a, 0x10, 0x3a, 0x3c, 0x02},\n+\t\t{ETH_RSS_NONF_IPV6_SCTP_SHIFT,\n+\t\t\t0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_NONF_IPV6_OTHER_SHIFT,\n+\t\t\t0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_FRAG_IPV6_SHIFT,\n+\t\t\t0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},\n+\t\t{ETH_RSS_L2_PAYLOAD_SHIFT,\n+\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t};\n+\n+\t/* Disable symmetric hash per PCTYPE */\n+\tfor (i = 0; i < RTE_DIM(sym_hash_ena_info); i++)\n+\t\ti40e_set_symmetric_hash_enable_per_pctype(hw,\n+\t\t\t\t\t&sym_hash_ena_info[i]);\n+\n+\t/* Disable symmetric hash per port */\n+\ti40e_set_symmetric_hash_enable_per_port(hw, 0);\n+\n+\t/* Initialize filter swap */\n+\tfor (i = 0; i < RTE_DIM(swap_info); i++)\n+\t\ti40e_set_filter_swap(hw, &swap_info[i]);\n+\n+\t/* Set hash function to Toeplitz by default */\n+\ti40e_set_hash_function(hw, RTE_ETH_HASH_FUNCTION_TOEPLITZ);\n+}\n+\n+/*\n+ * As global registers wouldn't be reset unless a global hardware reset,\n+ * hardware initialization is needed to put those registers into an\n+ * expected initial state.\n+ */\n+static void\n+i40e_hw_init(struct i40e_hw *hw)\n+{\n+\t/* clear the PF Queue Filter control register */\n+\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);\n+\n+\t/* Initialize hardware for hash function */\n+\ti40e_hash_function_hw_init(hw);\n+}\n", "prefixes": [ "dpdk-dev", "v3", "5/7" ] }