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{
    "id": 638,
    "url": "https://patches.dpdk.org/api/patches/638/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411974986-28137-18-git-send-email-changchun.ouyang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1411974986-28137-18-git-send-email-changchun.ouyang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-18-git-send-email-changchun.ouyang@intel.com",
    "date": "2014-09-29T07:16:25",
    "name": "[dpdk-dev,v2,17/18] ixgbe: Support X550 in IXGBE base code",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d923340b5508f456dcdf534d0d7de3aff245d32c",
    "submitter": {
        "id": 31,
        "url": "https://patches.dpdk.org/api/people/31/?format=api",
        "name": "Ouyang Changchun",
        "email": "changchun.ouyang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411974986-28137-18-git-send-email-changchun.ouyang@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/638/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/638/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1A2357E38;\n\tMon, 29 Sep 2014 09:11:05 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id BB5ED7E50\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:59 +0200 (CEST)",
            "from azsmga001.ch.intel.com ([10.2.17.19])\n\tby orsmga101.jf.intel.com with ESMTP; 29 Sep 2014 00:17:30 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby azsmga001.ch.intel.com with ESMTP; 29 Sep 2014 00:17:26 -0700",
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            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7HM55028454; Mon, 29 Sep 2014 15:17:24 +0800",
            "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7HMXb028450; \n\tMon, 29 Sep 2014 15:17:22 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"480666753\"",
        "From": "Ouyang Changchun <changchun.ouyang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Mon, 29 Sep 2014 15:16:25 +0800",
        "Message-Id": "<1411974986-28137-18-git-send-email-changchun.ouyang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>",
        "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] =?utf-8?q?=5BPATCH_v2_17/18=5D_ixgbe=3A_Support_X550_i?=\n\t=?utf-8?q?n_IXGBE_base_code?=",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds new file to support controller X550, therefore update the Makefile and README file.\nIt also updates the API functions, DCB related functions, mailbox related functions etc to support X550.\nIn addition, some new MACROs used by X550 are added.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/Makefile             |    2 +\n lib/librte_pmd_ixgbe/ixgbe/README         |    3 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c  |    9 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c    |   25 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h    |    2 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c |   12 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb.c    |   20 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c    |    4 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h  |    2 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c    |    1 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h    |    5 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h   |  267 ++++-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.h     |    3 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c   | 1809 +++++++++++++++++++++++++++++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h   |   88 ++\n 15 files changed, 2246 insertions(+), 6 deletions(-)\n create mode 100644 lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c\n create mode 100644 lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h",
    "diff": "diff --git a/lib/librte_pmd_ixgbe/Makefile b/lib/librte_pmd_ixgbe/Makefile\nindex 00ccedb..0b647bd 100644\n--- a/lib/librte_pmd_ixgbe/Makefile\n+++ b/lib/librte_pmd_ixgbe/Makefile\n@@ -64,6 +64,7 @@ CFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\n \n ifeq ($(shell test $(GCC_MAJOR_VERSION) -ge 4 -a $(GCC_MINOR_VERSION) -ge 6 && echo 1), 1)\n CFLAGS_ixgbe_common.o += -Wno-unused-but-set-variable\n+CFLAGS_ixgbe_x550.o += -Wno-unused-but-set-variable -Wno-maybe-uninitialized\n endif\n endif\n \n@@ -83,6 +84,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_common.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82598.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x540.c\n+SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x550.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_phy.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_api.c\n SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_vf.c\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/README b/lib/librte_pmd_ixgbe/ixgbe/README\nindex fc71e85..e0e5f0d 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/README\n+++ b/lib/librte_pmd_ixgbe/ixgbe/README\n@@ -34,7 +34,7 @@ Intel® IXGBE driver\n ===================\n \n This directory contains source code of FreeBSD ixgbe driver of version\n-cid-10g-shared-code.2014.03.13 released by LAD. The sub-directory of lad/\n+cid-10g-shared-code.2014.09.04 released by LAD. The sub-directory of lad/\n contains the original source package.\n This driver is valid for the product(s) listed below\n \n@@ -50,6 +50,7 @@ This driver is valid for the product(s) listed below\n * Intel® Ethernet Controller X540-AT2\n * Intel® Ethernet Server Adapter X520 Series\n * Intel® Ethernet Server Adapter X520-T2\n+* Intel® Ethernet Controller X550-BT2\n \n Updating driver\n ===============\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex 2b74374..a06b57c 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -1918,6 +1918,15 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t/* write both the same so that UDP and TCP use the same mask */\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);\n+\t/* also use it for SCTP */\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n \t/* store source and destination IP masks (big-endian) */\n \tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\nindex b3e89c5..1802760 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n@@ -81,8 +81,16 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n \tcase ixgbe_mac_X540:\n \t\tstatus = ixgbe_init_ops_X540(hw);\n \t\tbreak;\n+\tcase ixgbe_mac_X550:\n+\t\tstatus = ixgbe_init_ops_X550(hw);\n+\t\tbreak;\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tstatus = ixgbe_init_ops_X550EM(hw);\n+\t\tbreak;\n \tcase ixgbe_mac_82599_vf:\n \tcase ixgbe_mac_X540_vf:\n+\tcase ixgbe_mac_X550_vf:\n+\tcase ixgbe_mac_X550EM_x_vf:\n \t\tstatus = ixgbe_init_ops_vf(hw);\n \t\tbreak;\n \tdefault:\n@@ -157,6 +165,23 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n \tcase IXGBE_DEV_ID_X540T1:\n \t\thw->mac.type = ixgbe_mac_X540;\n \t\tbreak;\n+\tcase IXGBE_DEV_ID_X550T:\n+\t\thw->mac.type = ixgbe_mac_X550;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550EM_X:\n+\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n+\tcase IXGBE_DEV_ID_X550EM_X_KR:\n+\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n+\t\thw->mac.type = ixgbe_mac_X550EM_x;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550_VF:\n+\tcase IXGBE_DEV_ID_X550_VF_HV:\n+\t\thw->mac.type = ixgbe_mac_X550_vf;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550EM_X_VF:\n+\tcase IXGBE_DEV_ID_X550EM_X_VF_HV:\n+\t\thw->mac.type = ixgbe_mac_X550EM_x_vf;\n+\t\tbreak;\n \tdefault:\n \t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\nindex c63664a..1c12ff6 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n@@ -44,6 +44,8 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);\n+extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);\n+extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);\n \n s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex a799b40..37e5bae 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -184,6 +184,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \t\tcase IXGBE_DEV_ID_82599_T3_LOM:\n \t\tcase IXGBE_DEV_ID_X540T:\n \t\tcase IXGBE_DEV_ID_X540T1:\n+\t\tcase IXGBE_DEV_ID_X550T:\n \t\t\tsupported = true;\n \t\t\tbreak;\n \t\tdefault:\n@@ -563,7 +564,7 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n \t\t}\n \t}\n \n-\tif (hw->mac.type == ixgbe_mac_X540) {\n+\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {\n \t\tif (hw->phy.id == 0)\n \t\t\tixgbe_identify_phy(hw);\n \t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,\n@@ -3567,6 +3568,8 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tpcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;\n \t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n \t\tbreak;\n@@ -4080,8 +4083,13 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t}\n \n \tif ((links_reg & IXGBE_LINKS_SPEED_82599) ==\n-\t    IXGBE_LINKS_SPEED_10G_82599)\n+\t    IXGBE_LINKS_SPEED_10G_82599) {\n \t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n+\t\tif (hw->mac.type > ixgbe_mac_X550) {\n+\t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n+\t\t\t\t*speed = IXGBE_LINK_SPEED_2_5GB_FULL;\n+\t\t}\n+\t}\n \telse if ((links_reg & IXGBE_LINKS_SPEED_82599) ==\n \t\t IXGBE_LINKS_SPEED_1G_82599)\n \t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb.c\nindex 1c2459b..2245f27 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_dcb.c\n@@ -394,6 +394,8 @@ s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);\n \t\tbreak;\n \tdefault:\n@@ -420,6 +422,8 @@ s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);\n \t\tbreak;\n \tdefault:\n@@ -457,6 +461,8 @@ s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,\n \t\t\t\t\t\t\ttsa, map);\n \t\tbreak;\n@@ -494,6 +500,8 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,\n \t\t\t\t\t\t\t     bwgid, tsa);\n \t\tbreak;\n@@ -533,6 +541,8 @@ s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,\n \t\t\t\t\t\t\t     bwgid, tsa,\n \t\t\t\t\t\t\t     map);\n@@ -566,6 +576,8 @@ s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);\n \t\tbreak;\n \tdefault:\n@@ -590,6 +602,8 @@ s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);\n \t\tbreak;\n \tdefault:\n@@ -630,6 +644,8 @@ s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tixgbe_dcb_config_82599(hw, dcb_config);\n \t\tret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,\n \t\t\t\t\t\trefill, max, bwgid,\n@@ -660,6 +676,8 @@ s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);\n \t\tbreak;\n \tdefault:\n@@ -681,6 +699,8 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,\n \t\tbreak;\n \tcase ixgbe_mac_82599EB:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \t\tixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,\n \t\t\t\t\t\t  tsa, map);\n \t\tixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c\nindex 9389861..c00c2f7 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c\n@@ -615,6 +615,8 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n \tcase ixgbe_mac_82599EB:\n \t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));\n \t\tbreak;\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n \tcase ixgbe_mac_X540:\n \t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));\n \t\tbreak;\n@@ -761,6 +763,8 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)\n \tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n \n \tif (hw->mac.type != ixgbe_mac_82599EB &&\n+\t    hw->mac.type != ixgbe_mac_X550 &&\n+\t    hw->mac.type != ixgbe_mac_X550EM_x &&\n \t    hw->mac.type != ixgbe_mac_X540)\n \t\treturn;\n \ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h\nindex ab13d64..2d40bfd 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h\n@@ -97,6 +97,8 @@ enum {\n #define IXGBE_NTOHS(_i)\trte_be_to_cpu_16(_i)\n #define IXGBE_CPU_TO_LE32(_i)  rte_cpu_to_le_32(_i)\n #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n+#define IXGBE_CPU_TO_BE16(_i)  rte_cpu_to_be_16(_i)\n+#define IXGBE_CPU_TO_BE32(_i)  rte_cpu_to_be_32(_i)\n \n typedef uint8_t\t\tu8;\n typedef int8_t\t\ts8;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\nindex e1e560b..2305448 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n@@ -428,6 +428,7 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)\n \tcase TN1010_PHY_ID:\n \t\tphy_type = ixgbe_phy_tn;\n \t\tbreak;\n+\tcase X550_PHY_ID:\n \tcase X540_PHY_ID:\n \t\tphy_type = ixgbe_phy_aq;\n \t\tbreak;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\nindex c47812b..e262cc4 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\n@@ -82,6 +82,11 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_I2C_EEPROM_STATUS_FAIL\t0x2\n #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS\t0x3\n \n+#define IXGBE_CS4227\t\t\t0x9E\t/* CS4227 address */\n+#define IXGBE_CS4227_SPARE24_LSB\t0x12B0\t/* Reg to program EDC */\n+#define IXGBE_CS4227_EDC_MODE_CX1\t0x0002\n+#define IXGBE_CS4227_EDC_MODE_SR\t0x0004\n+\n /* Flow control defines */\n #define IXGBE_TAF_SYM_PAUSE\t\t0x400\n #define IXGBE_TAF_ASM_PAUSE\t\t0x800\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex 40ebed9..c67d462 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -126,6 +126,15 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_DEV_ID_X540_VF\t\t\t0x1515\n #define IXGBE_DEV_ID_X540_VF_HV\t\t\t0x1530\n #define IXGBE_DEV_ID_X540T1\t\t\t0x1560\n+#define IXGBE_DEV_ID_X550EM_X\t\t\t0x15A7\n+#define IXGBE_DEV_ID_X550EM_X_SFP\t\t0x15AC\n+#define IXGBE_DEV_ID_X550T\t\t\t0x1563\n+#define IXGBE_DEV_ID_X550EM_X_KX4\t\t0x15AA\n+#define IXGBE_DEV_ID_X550EM_X_KR\t\t0x15AB\n+#define IXGBE_DEV_ID_X550_VF_HV\t\t\t0x1564\n+#define IXGBE_DEV_ID_X550_VF\t\t\t0x1565\n+#define IXGBE_DEV_ID_X550EM_X_VF\t\t0x15A8\n+#define IXGBE_DEV_ID_X550EM_X_VF_HV\t\t0x15A9\n \n /* General Registers */\n #define IXGBE_CTRL\t\t0x00000\n@@ -333,6 +342,8 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_VLVF(_i)\t(0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */\n #define IXGBE_VLVFB(_i)\t(0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */\n #define IXGBE_VMVIR(_i)\t(0x08000 + ((_i) * 4))  /* 64 of these (0-63) */\n+#define IXGBE_PFFLPL\t\t0x050B0\n+#define IXGBE_PFFLPH\t\t0x050B4\n #define IXGBE_VT_CTL\t\t0x051B0\n #define IXGBE_PFMAILBOX(_i)\t(0x04B00 + (4 * (_i))) /* 64 total */\n /* 64 Mailboxes, 16 DW each */\n@@ -349,6 +360,12 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_MRCTL(_i)\t\t(0x0F600 + ((_i) * 4))\n #define IXGBE_VMRVLAN(_i)\t(0x0F610 + ((_i) * 4))\n #define IXGBE_VMRVM(_i)\t\t(0x0F630 + ((_i) * 4))\n+#define IXGBE_LVMMC_RX\t\t0x2FA8\n+#define IXGBE_LVMMC_TX\t\t0x8108\n+#define IXGBE_LMVM_RX\t\t0x2FA4\n+#define IXGBE_LMVM_TX\t\t0x8124\n+#define IXGBE_WQBR_RX(_i)\t(0x2FB0 + ((_i) * 4)) /* 4 total */\n+#define IXGBE_WQBR_TX(_i)\t(0x8130 + ((_i) * 4)) /* 4 total */\n #define IXGBE_L34T_IMIR(_i)\t(0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/\n #define IXGBE_RXFECCERR0\t0x051B8\n #define IXGBE_LLITHRESH\t\t0x0EC90\n@@ -357,8 +374,16 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_IMIRVP\t\t0x05AC0\n #define IXGBE_VMD_CTL\t\t0x0581C\n #define IXGBE_RETA(_i)\t\t(0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */\n+#define IXGBE_ERETA(_i)\t\t(0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */\n #define IXGBE_RSSRK(_i)\t\t(0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */\n \n+/* Registers for setting up RSS on X550 with SRIOV\n+ * _p - pool number (0..63)\n+ * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)\n+ */\n+#define IXGBE_PFVFMRQC(_p)\t(0x03400 + ((_p) * 4))\n+#define IXGBE_PFVFRSSRK(_i, _p)\t(0x018000 + ((_i) * 4) + ((_p) * 0x40))\n+#define IXGBE_PFVFRETA(_i, _p)\t(0x019000 + ((_i) * 4) + ((_p) * 0x40))\n \n /* Flow Director registers */\n #define IXGBE_FDIRCTRL\t0x0EE00\n@@ -412,6 +437,8 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_DMATXCTL_TE\t0x1 /* Transmit Enable */\n #define IXGBE_DMATXCTL_NS\t0x2 /* No Snoop LSO hdr buffer */\n #define IXGBE_DMATXCTL_GDV\t0x8 /* Global Double VLAN */\n+#define IXGBE_DMATXCTL_MDP_EN\t0x20 /* Bit 5 */\n+#define IXGBE_DMATXCTL_MBINTEN\t0x40 /* Bit 6 */\n #define IXGBE_DMATXCTL_VT_SHIFT\t16  /* VLAN EtherType */\n \n #define IXGBE_PFDTXGSWC_VT_LBEN\t0x1 /* Local L2 VT switch enable */\n@@ -443,16 +470,22 @@ struct ixgbe_thermal_sensor_data {\n \n #define IXGBE_WUPL\t0x05900\n #define IXGBE_WUPM\t0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */\n+#define IXGBE_PROXYS\t0x05F60 /* Proxying Status Register */\n+#define IXGBE_PROXYFC\t0x05F64 /* Proxying Filter Control Register */\n+#define IXGBE_VXLANCTRL\t0x0000507C /* Rx filter VXLAN UDPPORT Register */\n \n-#define IXGBE_FHFT(_n)\t(0x09000 + (_n * 0x100)) /* Flex host filter table */\n+#define IXGBE_FHFT(_n)\t(0x09000 + ((_n) * 0x100)) /* Flex host filter table */\n /* Ext Flexible Host Filter Table */\n-#define IXGBE_FHFT_EXT(_n)\t(0x09800 + (_n * 0x100))\n+#define IXGBE_FHFT_EXT(_n)\t(0x09800 + ((_n) * 0x100))\n+#define IXGBE_FHFT_EXT_X550(_n)\t(0x09600 + ((_n) * 0x100))\n \n /* Four Flexible Filters are supported */\n #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX\t\t4\n \n /* Six Flexible Filters are supported */\n #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6\t6\n+/* Eight Flexible Filters are supported */\n+#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8\t8\n #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX\t2\n \n /* Each Flexible Filter is at most 128 (0x80) bytes in length */\n@@ -485,10 +518,14 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_WUFC_FLX4\t0x00100000 /* Flexible Filter 4 Enable */\n #define IXGBE_WUFC_FLX5\t0x00200000 /* Flexible Filter 5 Enable */\n #define IXGBE_WUFC_FLX_FILTERS\t\t0x000F0000 /* Mask for 4 flex filters */\n+#define IXGBE_WUFC_FLX_FILTERS_6\t0x003F0000 /* Mask for 6 flex filters */\n+#define IXGBE_WUFC_FLX_FILTERS_8\t0x00FF0000 /* Mask for 8 flex filters */\n+#define IXGBE_WUFC_FW_RST_WK\t0x80000000 /* Ena wake on FW reset assertion */\n /* Mask for Ext. flex filters */\n #define IXGBE_WUFC_EXT_FLX_FILTERS\t0x00300000\n #define IXGBE_WUFC_ALL_FILTERS\t\t0x000F00FF /* Mask all 4 flex filters */\n #define IXGBE_WUFC_ALL_FILTERS_6\t0x003F00FF /* Mask all 6 flex filters */\n+#define IXGBE_WUFC_ALL_FILTERS_8\t0x00FF00FF /* Mask all 8 flex filters */\n #define IXGBE_WUFC_FLX_OFFSET\t16 /* Offset to the Flexible Filters bits */\n \n /* Wake Up Status */\n@@ -508,6 +545,23 @@ struct ixgbe_thermal_sensor_data {\n #define IXGBE_WUS_FLX4\t\tIXGBE_WUFC_FLX4\n #define IXGBE_WUS_FLX5\t\tIXGBE_WUFC_FLX5\n #define IXGBE_WUS_FLX_FILTERS\tIXGBE_WUFC_FLX_FILTERS\n+#define IXGBE_WUS_FW_RST_WK\tIXGBE_WUFC_FW_RST_WK\n+/* Proxy Status */\n+#define IXGBE_PROXYS_EX\t\t0x00000004 /* Exact packet received */\n+#define IXGBE_PROXYS_ARP_DIR\t0x00000020 /* ARP w/filter match received */\n+#define IXGBE_PROXYS_NS\t\t0x00000200 /* IPV6 NS received */\n+#define IXGBE_PROXYS_NS_DIR\t0x00000400 /* IPV6 NS w/DA match received */\n+#define IXGBE_PROXYS_ARP\t0x00000800 /* ARP request packet received */\n+#define IXGBE_PROXYS_MLD\t0x00001000 /* IPv6 MLD packet received */\n+\n+/* Proxying Filter Control */\n+#define IXGBE_PROXYFC_ENABLE\t0x00000001 /* Port Proxying Enable */\n+#define IXGBE_PROXYFC_EX\t0x00000004 /* Directed Exact Proxy Enable */\n+#define IXGBE_PROXYFC_ARP_DIR\t0x00000020 /* Directed ARP Proxy Enable */\n+#define IXGBE_PROXYFC_NS\t0x00000200 /* IPv6 Neighbor Solicitation */\n+#define IXGBE_PROXYFC_ARP\t0x00000800 /* ARP Request Proxy Enable */\n+#define IXGBE_PROXYFC_MLD\t0x00000800 /* IPv6 MLD Proxy Enable */\n+#define IXGBE_PROXYFC_NO_TCO\t0x00008000 /* Ignore TCO packets */\n \n #define IXGBE_WUPL_LENGTH_MASK\t0xFFFF\n \n@@ -715,6 +769,8 @@ struct ixgbe_dmac_config {\n \n \n /* FCoE DMA Context Registers */\n+/* FCoE Direct DMA Context */\n+#define IXGBE_FCDDC(_i, _j)\t(0x20000 + ((_i) * 0x4) + ((_j) * 0x10))\n #define IXGBE_FCPTRL\t\t0x02410 /* FC User Desc. PTR Low */\n #define IXGBE_FCPTRH\t\t0x02414 /* FC USer Desc. PTR High */\n #define IXGBE_FCBUFF\t\t0x02418 /* FC Buffer Control */\n@@ -738,6 +794,12 @@ struct ixgbe_dmac_config {\n #define IXGBE_REOFF\t\t0x05158 /* Rx FC EOF */\n #define IXGBE_RSOFF\t\t0x051F8 /* Rx FC SOF */\n /* FCoE Filter Context Registers */\n+#define IXGBE_FCD_ID\t\t0x05114 /* FCoE D_ID */\n+#define IXGBE_FCSMAC\t\t0x0510C /* FCoE Source MAC */\n+#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT\t16\n+/* FCoE Direct Filter Context */\n+#define IXGBE_FCDFC(_i, _j)\t(0x28000 + ((_i) * 0x4) + ((_j) * 0x10))\n+#define IXGBE_FCDFCD(_i)\t(0x30000 + ((_i) * 0x4))\n #define IXGBE_FCFLT\t\t0x05108 /* FC FLT Context */\n #define IXGBE_FCFLTRW\t\t0x05110 /* FC Filter RW Control */\n #define IXGBE_FCPARAM\t\t0x051d8 /* FC Offset Parameter */\n@@ -768,6 +830,10 @@ struct ixgbe_dmac_config {\n #define IXGBE_FCRETASEL_ENA\t0x2 /* FCoE FCRETASEL bit */\n #define IXGBE_FCRETA_SIZE\t8 /* Max entries in FCRETA */\n #define IXGBE_FCRETA_ENTRY_MASK\t0x0000007f /* 7 bits for the queue index */\n+#define IXGBE_FCRETA_SIZE_X550\t32 /* Max entries in FCRETA */\n+/* Higher 7 bits for the queue index */\n+#define IXGBE_FCRETA_ENTRY_HIGH_MASK\t0x007F0000\n+#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT\t16\n \n /* Stats registers */\n #define IXGBE_CRCERRS\t0x04000\n@@ -887,6 +953,7 @@ struct ixgbe_dmac_config {\n #define IXGBE_BMCIP_IPADDR_VALID\t0x00000002\n \n /* Management Bit Fields and Masks */\n+#define IXGBE_MANC_MPROXYE\t0x40000000 /* Management Proxy Enable */\n #define IXGBE_MANC_RCV_TCO_EN\t0x00020000 /* Rcv TCO packet enable */\n #define IXGBE_MANC_EN_BMC2OS\t0x10000000 /* Ena BMC2OS and OS2BMC traffic */\n #define IXGBE_MANC_EN_BMC2OS_SHIFT\t28\n@@ -949,6 +1016,12 @@ struct ixgbe_dmac_config {\n #define IXGBE_PBACLR_82599\t0x11068\n #define IXGBE_CIAA_82599\t0x11088\n #define IXGBE_CIAD_82599\t0x1108C\n+#define IXGBE_CIAA_X550\t\t0x11508\n+#define IXGBE_CIAD_X550\t\t0x11510\n+#define IXGBE_CIAA_BY_MAC(_hw)\t((((_hw)->mac.type >= ixgbe_mac_X550) ? \\\n+\t\t\t\t IXGBE_CIAA_X550 : IXGBE_CIAA_82599))\n+#define IXGBE_CIAD_BY_MAC(_hw)\t((((_hw)->mac.type >= ixgbe_mac_X550) ? \\\n+\t\t\t\t IXGBE_CIAD_X550 : IXGBE_CIAD_82599))\n #define IXGBE_PICAUSE\t\t0x110B0\n #define IXGBE_PIENA\t\t0x110B8\n #define IXGBE_CDQ_MBR_82599\t0x110B4\n@@ -985,6 +1058,7 @@ struct ixgbe_dmac_config {\n #define IXGBE_TXSTMPH\t0x08C08 /* Tx timestamp value High - RO */\n #define IXGBE_SYSTIML\t0x08C0C /* System time register Low - RO */\n #define IXGBE_SYSTIMH\t0x08C10 /* System time register High - RO */\n+#define IXGBE_SYSTIMR\t0x08C58 /* System time register Residue - RO */\n #define IXGBE_TIMINCA\t0x08C14 /* Increment attributes register - RW */\n #define IXGBE_TIMADJL\t0x08C18 /* Time Adjustment Offset register Low - RW */\n #define IXGBE_TIMADJH\t0x08C1C /* Time Adjustment Offset register High - RW */\n@@ -1001,6 +1075,9 @@ struct ixgbe_dmac_config {\n #define IXGBE_AUXSTMPH0\t0x08C40 /* Auxiliary Time Stamp 0 register High - RO */\n #define IXGBE_AUXSTMPL1\t0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */\n #define IXGBE_AUXSTMPH1\t0x08C48 /* Auxiliary Time Stamp 1 register High - RO */\n+#define IXGBE_TSIM\t0x08C68 /* TimeSync Interrupt Mask Register - RW */\n+#define IXGBE_TSICR\t0x08C60 /* TimeSync Interrupt Cause Register - WO */\n+#define IXGBE_TSSDP\t0x0003C /* TimeSync SDP Configuration Register - RW */\n \n /* Diagnostic Registers */\n #define IXGBE_RDSTATCTL\t\t0x02C20\n@@ -1157,6 +1234,7 @@ struct ixgbe_dmac_config {\n /* RDRXCTL Bit Masks */\n #define IXGBE_RDRXCTL_RDMTS_1_2\t\t0x00000000 /* Rx Desc Min THLD Size */\n #define IXGBE_RDRXCTL_CRCSTRIP\t\t0x00000002 /* CRC Strip */\n+#define IXGBE_RDRXCTL_PSP\t\t0x00000004 /* Pad Small Packet */\n #define IXGBE_RDRXCTL_MVMEN\t\t0x00000020\n #define IXGBE_RDRXCTL_RSC_PUSH_DIS\t0x00000020\n #define IXGBE_RDRXCTL_DMAIDONE\t\t0x00000008 /* DMA init cycle done */\n@@ -1166,6 +1244,8 @@ struct ixgbe_dmac_config {\n #define IXGBE_RDRXCTL_RSCLLIDIS\t\t0x00800000 /* Disable RSC compl on LLI*/\n #define IXGBE_RDRXCTL_RSCACKC\t\t0x02000000 /* must set 1 when RSC ena */\n #define IXGBE_RDRXCTL_FCOE_WRFIX\t0x04000000 /* must set 1 when RSC ena */\n+#define IXGBE_RDRXCTL_MBINTEN\t\t0x10000000\n+#define IXGBE_RDRXCTL_MDP_EN\t\t0x20000000\n \n /* RQTC Bit Masks and Shifts */\n #define IXGBE_RQTC_SHIFT_TC(_i)\t((_i) * 4)\n@@ -1344,6 +1424,7 @@ struct ixgbe_dmac_config {\n #define TN1010_PHY_ID\t0x00A19410\n #define TNX_FW_REV\t0xB\n #define X540_PHY_ID\t0x01540200\n+#define X550_PHY_ID\t0x01540220\n #define AQ_FW_REV\t0x20\n #define QT2022_PHY_ID\t0x0043A400\n #define ATH_PHY_ID\t0x03429050\n@@ -1699,12 +1780,14 @@ enum {\n  *\t1588 (0x88f7):\t Filter 3\n  *\tFIP  (0x8914):\t Filter 4\n  *\tLLDP (0x88CC):\t Filter 5\n+ *\tLACP (0x8809):\t Filter 6\n  */\n #define IXGBE_ETQF_FILTER_EAPOL\t\t0\n #define IXGBE_ETQF_FILTER_FCOE\t\t2\n #define IXGBE_ETQF_FILTER_1588\t\t3\n #define IXGBE_ETQF_FILTER_FIP\t\t4\n #define IXGBE_ETQF_FILTER_LLDP\t\t5\n+#define IXGBE_ETQF_FILTER_LACP\t\t6\n /* VLAN Control Bit Masks */\n #define IXGBE_VLNCTRL_VET\t\t0x0000FFFF  /* bits 0-15 */\n #define IXGBE_VLNCTRL_CFI\t\t0x10000000  /* bit 28 */\n@@ -1849,6 +1932,7 @@ enum {\n #define IXGBE_LINKS_TL_FAULT\t\t0x00001000\n #define IXGBE_LINKS_SIGNAL\t\t0x00000F00\n \n+#define IXGBE_LINKS_SPEED_NON_STD\t0x08000000\n #define IXGBE_LINKS_SPEED_82599\t\t0x30000000\n #define IXGBE_LINKS_SPEED_10G_82599\t0x30000000\n #define IXGBE_LINKS_SPEED_1G_82599\t0x20000000\n@@ -1929,6 +2013,9 @@ enum {\n #define IXGBE_EEPROM_WORD_SIZE_SHIFT\t6\n #define IXGBE_EEPROM_OPCODE_BITS\t8\n \n+/* FLA Register */\n+#define IXGBE_FLA_LOCKED\t0x00000040\n+\n /* Part Number String Length */\n #define IXGBE_PBANUM_LENGTH\t11\n \n@@ -1950,12 +2037,31 @@ enum {\n #define IXGBE_MAC1_PTR\t\t\t0x0C\n #define IXGBE_CSR0_CONFIG_PTR\t\t0x0D\n #define IXGBE_CSR1_CONFIG_PTR\t\t0x0E\n+#define IXGBE_PCIE_ANALOG_PTR_X550\t0x02\n+#define IXGBE_SHADOW_RAM_SIZE_X550\t0x4000\n+#define IXGBE_IXGBE_PCIE_GENERAL_SIZE\t0x24\n+#define IXGBE_PCIE_CONFIG_SIZE\t\t0x08\n+#define IXGBE_EEPROM_LAST_WORD\t\t0x41\n #define IXGBE_FW_PTR\t\t\t0x0F\n #define IXGBE_PBANUM0_PTR\t\t0x15\n #define IXGBE_PBANUM1_PTR\t\t0x16\n #define IXGBE_ALT_MAC_ADDR_PTR\t\t0x37\n #define IXGBE_FREE_SPACE_PTR\t\t0X3E\n \n+/* External Thermal Sensor Config */\n+#define IXGBE_ETS_CFG\t\t\t0x26\n+#define IXGBE_ETS_LTHRES_DELTA_MASK\t0x07C0\n+#define IXGBE_ETS_LTHRES_DELTA_SHIFT\t6\n+#define IXGBE_ETS_TYPE_MASK\t\t0x0038\n+#define IXGBE_ETS_TYPE_SHIFT\t\t3\n+#define IXGBE_ETS_TYPE_EMC\t\t0x000\n+#define IXGBE_ETS_NUM_SENSORS_MASK\t0x0007\n+#define IXGBE_ETS_DATA_LOC_MASK\t\t0x3C00\n+#define IXGBE_ETS_DATA_LOC_SHIFT\t10\n+#define IXGBE_ETS_DATA_INDEX_MASK\t0x0300\n+#define IXGBE_ETS_DATA_INDEX_SHIFT\t8\n+#define IXGBE_ETS_DATA_HTHRESH_MASK\t0x00FF\n+\n #define IXGBE_SAN_MAC_ADDR_PTR\t\t0x28\n #define IXGBE_DEVICE_CAPS\t\t0x2C\n #define IXGBE_SERIAL_NUMBER_MAC_ADDR\t0x11\n@@ -2148,6 +2254,14 @@ enum {\n #define IXGBE_TSAUXC_EN_CLK\t\t0x00000004\n #define IXGBE_TSAUXC_SYNCLK\t\t0x00000008\n #define IXGBE_TSAUXC_SDP0_INT\t\t0x00000040\n+#define IXGBE_TSAUXC_EN_TT0\t\t0x00000001\n+#define IXGBE_TSAUXC_EN_TT1\t\t0x00000002\n+#define IXGBE_TSAUXC_ST0\t\t0x00000010\n+#define IXGBE_TSAUXC_DISABLE_SYSTIME\t0x80000000\n+\n+#define IXGBE_TSSDP_TS_SDP0_SEL_MASK\t0x000000C0\n+#define IXGBE_TSSDP_TS_SDP0_CLK0\t0x00000080\n+#define IXGBE_TSSDP_TS_SDP0_EN\t\t0x00000100\n \n #define IXGBE_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n #define IXGBE_TSYNCTXCTL_ENABLED\t0x00000010 /* Tx timestamping enabled */\n@@ -2157,8 +2271,19 @@ enum {\n #define IXGBE_TSYNCRXCTL_TYPE_L2_V2\t0x00\n #define IXGBE_TSYNCRXCTL_TYPE_L4_V1\t0x02\n #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n+#define IXGBE_TSYNCRXCTL_TYPE_ALL\t0x08\n #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n #define IXGBE_TSYNCRXCTL_ENABLED\t0x00000010 /* Rx Timestamping enabled */\n+#define IXGBE_TSYNCRXCTL_TSIP_UT_EN\t0x00800000 /* Rx Timestamp in Packet */\n+#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK\t0xFF000000 /* Rx Timestamp UP Mask */\n+\n+#define IXGBE_TSIM_SYS_WRAP\t\t0x00000001\n+#define IXGBE_TSIM_TXTS\t\t\t0x00000002\n+#define IXGBE_TSIM_TADJ\t\t\t0x00000080\n+\n+#define IXGBE_TSICR_SYS_WRAP\t\tIXGBE_TSIM_SYS_WRAP\n+#define IXGBE_TSICR_TXTS\t\tIXGBE_TSIM_TXTS\n+#define IXGBE_TSICR_TADJ\t\tIXGBE_TSIM_TADJ\n \n #define IXGBE_RXMTRL_V1_CTRLT_MASK\t0x000000FF\n #define IXGBE_RXMTRL_V1_SYNC_MSG\t0x00\n@@ -2217,10 +2342,12 @@ enum {\n #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP\t0x00400000\n #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP\t0x00800000\n #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000\n+#define IXGBE_MRQC_MULTIPLE_RSS\t\t0x00002000\n #define IXGBE_MRQC_L3L4TXSWEN\t\t0x00008000\n \n /* Queue Drop Enable */\n #define IXGBE_QDE_ENABLE\t0x00000001\n+#define IXGBE_QDE_HIDE_VLAN\t0x00000002\n #define IXGBE_QDE_IDX_MASK\t0x00007F00\n #define IXGBE_QDE_IDX_SHIFT\t8\n #define IXGBE_QDE_WRITE\t\t0x00010000\n@@ -2262,10 +2389,12 @@ enum {\n #define IXGBE_RXD_STAT_IPCS\t0x40 /* IP xsum calculated */\n #define IXGBE_RXD_STAT_PIF\t0x80 /* passed in-exact filter */\n #define IXGBE_RXD_STAT_CRCV\t0x100 /* Speculative CRC Valid */\n+#define IXGBE_RXD_STAT_OUTERIPCS\t0x100 /* Cloud IP xsum calculated */\n #define IXGBE_RXD_STAT_VEXT\t0x200 /* 1st VLAN found */\n #define IXGBE_RXD_STAT_UDPV\t0x400 /* Valid UDP checksum */\n #define IXGBE_RXD_STAT_DYNINT\t0x800 /* Pkt caused INT via DYNINT */\n #define IXGBE_RXD_STAT_LLINT\t0x800 /* Pkt caused Low Latency Interrupt */\n+#define IXGBE_RXD_STAT_TSIP\t0x08000 /* Time Stamp in packet buffer */\n #define IXGBE_RXD_STAT_TS\t0x10000 /* Time Stamp */\n #define IXGBE_RXD_STAT_SECP\t0x20000 /* Security Processing */\n #define IXGBE_RXD_STAT_LB\t0x40000 /* Loopback Status */\n@@ -2279,6 +2408,7 @@ enum {\n #define IXGBE_RXD_ERR_IPE\t0x80 /* IP Checksum Error */\n #define IXGBE_RXDADV_ERR_MASK\t\t0xfff00000 /* RDESC.ERRORS mask */\n #define IXGBE_RXDADV_ERR_SHIFT\t\t20 /* RDESC.ERRORS shift */\n+#define IXGBE_RXDADV_ERR_OUTERIPER\t0x04000000 /* CRC IP Header error */\n #define IXGBE_RXDADV_ERR_RXE\t\t0x20000000 /* Any MAC Error */\n #define IXGBE_RXDADV_ERR_FCEOFE\t\t0x80000000 /* FCoEFe/IPE */\n #define IXGBE_RXDADV_ERR_FCERR\t\t0x00700000 /* FCERR/FDIRERR */\n@@ -2311,6 +2441,7 @@ enum {\n #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP\t0x00000020 /* 10: Recv. FCP_RSP */\n #define IXGBE_RXDADV_STAT_FCSTAT_DDP\t0x00000030 /* 11: Ctxt w/ DDP */\n #define IXGBE_RXDADV_STAT_TS\t\t0x00010000 /* IEEE1588 Time Stamp */\n+#define IXGBE_RXDADV_STAT_TSIP\t\t0x00008000 /* Time Stamp in packet buffer */\n \n /* PSRTYPE bit definitions */\n #define IXGBE_PSRTYPE_TCPHDR\t0x00000010\n@@ -2321,6 +2452,10 @@ enum {\n \n /* SRRCTL bit definitions */\n #define IXGBE_SRRCTL_BSIZEPKT_SHIFT\t10 /* so many KBs */\n+#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT\t2 /* 64byte resolution (>> 6)\n+\t\t\t\t\t   * + at bit 8 offset (<< 8)\n+\t\t\t\t\t   *  = (<< 2)\n+\t\t\t\t\t   */\n #define IXGBE_SRRCTL_RDMTS_SHIFT\t22\n #define IXGBE_SRRCTL_RDMTS_MASK\t\t0x01C00000\n #define IXGBE_SRRCTL_DROP_EN\t\t0x10000000\n@@ -2368,6 +2503,8 @@ enum {\n #define IXGBE_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n #define IXGBE_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n #define IXGBE_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n+#define IXGBE_RXDADV_PKTTYPE_VXLAN\t0x00000800 /* VXLAN hdr present */\n+#define IXGBE_RXDADV_PKTTYPE_TUNNEL\t0x00010000 /* Tunnel type */\n #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n #define IXGBE_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n@@ -2418,6 +2555,68 @@ enum {\n #define IXGBE_MBVFICR(_i)\t\t(0x00710 + ((_i) * 4))\n #define IXGBE_VFLRE(_i)\t\t\t(((_i & 1) ? 0x001C0 : 0x00600))\n #define IXGBE_VFLREC(_i)\t\t (0x00700 + ((_i) * 4))\n+/* Translated register #defines */\n+#define IXGBE_PVFCTRL(P)\t(0x00300 + (4 * (P)))\n+#define IXGBE_PVFSTATUS(P)\t(0x00008 + (0 * (P)))\n+#define IXGBE_PVFLINKS(P)\t(0x042A4 + (0 * (P)))\n+#define IXGBE_PVFRTIMER(P)\t(0x00048 + (0 * (P)))\n+#define IXGBE_PVFMAILBOX(P)\t(0x04C00 + (4 * (P)))\n+#define IXGBE_PVFRXMEMWRAP(P)\t(0x03190 + (0 * (P)))\n+#define IXGBE_PVTEICR(P)\t(0x00B00 + (4 * (P)))\n+#define IXGBE_PVTEICS(P)\t(0x00C00 + (4 * (P)))\n+#define IXGBE_PVTEIMS(P)\t(0x00D00 + (4 * (P)))\n+#define IXGBE_PVTEIMC(P)\t(0x00E00 + (4 * (P)))\n+#define IXGBE_PVTEIAC(P)\t(0x00F00 + (4 * (P)))\n+#define IXGBE_PVTEIAM(P)\t(0x04D00 + (4 * (P)))\n+#define IXGBE_PVTEITR(P)\t(((P) < 24) ? (0x00820 + ((P) * 4)) : \\\n+\t\t\t\t (0x012300 + (((P) - 24) * 4)))\n+#define IXGBE_PVTIVAR(P)\t(0x12500 + (4 * (P)))\n+#define IXGBE_PVTIVAR_MISC(P)\t(0x04E00 + (4 * (P)))\n+#define IXGBE_PVTRSCINT(P)\t(0x12000 + (4 * (P)))\n+#define IXGBE_VFPBACL(P)\t(0x110C8 + (4 * (P)))\n+#define IXGBE_PVFRDBAL(P)\t((P < 64) ? (0x01000 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D000 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFRDBAH(P)\t((P < 64) ? (0x01004 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D004 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFRDLEN(P)\t((P < 64) ? (0x01008 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D008 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFRDH(P)\t\t((P < 64) ? (0x01010 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D010 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFRDT(P)\t\t((P < 64) ? (0x01018 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D018 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFRXDCTL(P)\t((P < 64) ? (0x01028 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D028 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFSRRCTL(P)\t((P < 64) ? (0x01014 + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D014 + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFPSRTYPE(P)\t(0x0EA00 + (4 * (P)))\n+#define IXGBE_PVFTDBAL(P)\t(0x06000 + (0x40 * (P)))\n+#define IXGBE_PVFTDBAH(P)\t(0x06004 + (0x40 * (P)))\n+#define IXGBE_PVFTTDLEN(P)\t(0x06008 + (0x40 * (P)))\n+#define IXGBE_PVFTDH(P)\t\t(0x06010 + (0x40 * (P)))\n+#define IXGBE_PVFTDT(P)\t\t(0x06018 + (0x40 * (P)))\n+#define IXGBE_PVFTXDCTL(P)\t(0x06028 + (0x40 * (P)))\n+#define IXGBE_PVFTDWBAL(P)\t(0x06038 + (0x40 * (P)))\n+#define IXGBE_PVFTDWBAH(P)\t(0x0603C + (0x40 * (P)))\n+#define IXGBE_PVFDCA_RXCTRL(P)\t(((P) < 64) ? (0x0100C + (0x40 * (P))) \\\n+\t\t\t\t : (0x0D00C + (0x40 * ((P) - 64))))\n+#define IXGBE_PVFDCA_TXCTRL(P)\t(0x0600C + (0x40 * (P)))\n+#define IXGBE_PVFGPRC(x)\t(0x0101C + (0x40 * (x)))\n+#define IXGBE_PVFGPTC(x)\t(0x08300 + (0x04 * (x)))\n+#define IXGBE_PVFGORC_LSB(x)\t(0x01020 + (0x40 * (x)))\n+#define IXGBE_PVFGORC_MSB(x)\t(0x0D020 + (0x40 * (x)))\n+#define IXGBE_PVFGOTC_LSB(x)\t(0x08400 + (0x08 * (x)))\n+#define IXGBE_PVFGOTC_MSB(x)\t(0x08404 + (0x08 * (x)))\n+#define IXGBE_PVFMPRC(x)\t(0x0D01C + (0x40 * (x)))\n+\n+#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \\\n+\t\t(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))\n+#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \\\n+\t\t(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))\n+\n+#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \\\n+\t\t(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))\n+#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \\\n+\t\t(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))\n \n /* Little Endian defines */\n #ifndef __le16\n@@ -2541,7 +2740,17 @@ enum ixgbe_fdir_pballoc_type {\n #define FW_CEM_UNUSED_VER\t\t0x0\n #define FW_CEM_MAX_RETRIES\t\t3\n #define FW_CEM_RESP_STATUS_SUCCESS\t0x1\n-\n+#define FW_READ_SHADOW_RAM_CMD\t\t0x31\n+#define FW_READ_SHADOW_RAM_LEN\t\t0x6\n+#define FW_WRITE_SHADOW_RAM_CMD\t\t0x33\n+#define FW_WRITE_SHADOW_RAM_LEN\t\t0xA /* 8 plus 1 WORD to write */\n+#define FW_SHADOW_RAM_DUMP_CMD\t\t0x36\n+#define FW_SHADOW_RAM_DUMP_LEN\t\t0\n+#define FW_DEFAULT_CHECKSUM\t\t0xFF /* checksum always 0xFF */\n+#define FW_NVM_DATA_OFFSET\t\t3\n+#define FW_MAX_READ_BUFFER_SIZE\t\t1024\n+#define FW_DISABLE_RXEN_CMD\t\t0xDE\n+#define FW_DISABLE_RXEN_LEN\t\t0x1\n /* Host Interface Command Structures */\n \n struct ixgbe_hic_hdr {\n@@ -2554,6 +2763,13 @@ struct ixgbe_hic_hdr {\n \tu8 checksum;\n };\n \n+struct ixgbe_hic_hdr2 {\n+\tu8 cmd;\n+\tu8 buf_len1;\n+\tu8 buf_len2;\n+\tu8 checksum;\n+};\n+\n struct ixgbe_hic_drv_info {\n \tstruct ixgbe_hic_hdr hdr;\n \tu8 port_num;\n@@ -2565,6 +2781,33 @@ struct ixgbe_hic_drv_info {\n \tu16 pad2; /* end spacing to ensure length is mult. of dword2 */\n };\n \n+/* These need to be dword aligned */\n+struct ixgbe_hic_read_shadow_ram {\n+\tstruct ixgbe_hic_hdr2 hdr;\n+\tu32 address;\n+\tu16 length;\n+\tu16 pad2;\n+\tu16 data;\n+\tu16 pad3;\n+};\n+\n+struct ixgbe_hic_write_shadow_ram {\n+\tstruct ixgbe_hic_hdr2 hdr;\n+\tu32 address;\n+\tu16 length;\n+\tu16 pad2;\n+\tu16 data;\n+\tu16 pad3;\n+};\n+\n+struct ixgbe_hic_disable_rxen {\n+\tstruct ixgbe_hic_hdr hdr;\n+\tu8  port_number;\n+\tu8  pad2;\n+\tu16 pad3;\n+};\n+\n+\n /* Transmit Descriptor - Legacy */\n struct ixgbe_legacy_tx_desc {\n \tu64 buffer_addr; /* Address of the descriptor's data buffer */\n@@ -2706,6 +2949,12 @@ struct ixgbe_adv_tx_context_desc {\n #define IXGBE_ADVTXD_L4LEN_SHIFT\t8  /* Adv ctxt L4LEN shift */\n #define IXGBE_ADVTXD_MSS_SHIFT\t\t16  /* Adv ctxt MSS shift */\n \n+#define IXGBE_ADVTXD_OUTER_IPLEN\t16 /* Adv ctxt OUTERIPLEN shift */\n+#define IXGBE_ADVTXD_TUNNEL_LEN \t24 /* Adv ctxt TUNNELLEN shift */\n+#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT\t16 /* Adv Tx Desc Tunnel Type shift */\n+#define IXGBE_ADVTXD_OUTERIPCS_SHIFT\t17 /* Adv Tx Desc OUTERIPCS Shift */\n+#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE\t1  /* Adv Tx Desc Tunnel Type NVGRE */\n+\n /* Autonegotiation advertised speeds */\n typedef u32 ixgbe_autoneg_advertised;\n /* Link speed */\n@@ -2713,6 +2962,7 @@ typedef u32 ixgbe_link_speed;\n #define IXGBE_LINK_SPEED_UNKNOWN\t0\n #define IXGBE_LINK_SPEED_100_FULL\t0x0008\n #define IXGBE_LINK_SPEED_1GB_FULL\t0x0020\n+#define IXGBE_LINK_SPEED_2_5GB_FULL\t0x0040\n #define IXGBE_LINK_SPEED_10GB_FULL\t0x0080\n #define IXGBE_LINK_SPEED_82598_AUTONEG\t(IXGBE_LINK_SPEED_1GB_FULL | \\\n \t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n@@ -2909,6 +3159,15 @@ enum ixgbe_mac_type {\n \tixgbe_mac_82599_vf,\n \tixgbe_mac_X540,\n \tixgbe_mac_X540_vf,\n+\t/*\n+\t * X550EM MAC type decoder:\n+\t * ixgbe_mac_X550EM_x: \"x\" = Xeon\n+\t * ixgbe_mac_X550EM_a: \"a\" = Atom\n+\t */\n+\tixgbe_mac_X550,\n+\tixgbe_mac_X550EM_x,\n+\tixgbe_mac_X550_vf,\n+\tixgbe_mac_X550EM_x_vf,\n \tixgbe_num_macs\n };\n \n@@ -2917,6 +3176,8 @@ enum ixgbe_phy_type {\n \tixgbe_phy_none,\n \tixgbe_phy_tn,\n \tixgbe_phy_aq,\n+\tixgbe_phy_x550em_kr,\n+\tixgbe_phy_x550em_kx4,\n \tixgbe_phy_cu_unknown,\n \tixgbe_phy_qt,\n \tixgbe_phy_xaui,\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.h\nindex b84b4ba..3c1c168 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.h\n@@ -84,6 +84,9 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_VFGOTC_LSB\t0x02020\n #define IXGBE_VFGOTC_MSB\t0x02024\n #define IXGBE_VFMPRC\t\t0x01034\n+#define IXGBE_VFMRQC\t\t0x3000\n+#define IXGBE_VFRSSRK(x)\t(0x3100 + ((x) * 4))\n+#define IXGBE_VFRETA(x)\t(0x3200 + ((x) * 4))\n \n \n struct ixgbevf_hw_stats {\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c\nnew file mode 100644\nindex 0000000..06d66dd\n--- /dev/null\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c\n@@ -0,0 +1,1809 @@\n+/*******************************************************************************\n+\n+Copyright (c) 2001-2014, Intel Corporation\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+\n+ 1. Redistributions of source code must retain the above copyright notice,\n+    this list of conditions and the following disclaimer.\n+\n+ 2. Redistributions in binary form must reproduce the above copyright\n+    notice, this list of conditions and the following disclaimer in the\n+    documentation and/or other materials provided with the distribution.\n+\n+ 3. Neither the name of the Intel Corporation nor the names of its\n+    contributors may be used to endorse or promote products derived from\n+    this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+POSSIBILITY OF SUCH DAMAGE.\n+\n+***************************************************************************/\n+\n+#include \"ixgbe_x550.h\"\n+#include \"ixgbe_x540.h\"\n+#include \"ixgbe_type.h\"\n+#include \"ixgbe_api.h\"\n+#include \"ixgbe_common.h\"\n+#include \"ixgbe_phy.h\"\n+\n+/**\n+ *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Initialize the function pointers and assign the MAC type for X550.\n+ *  Does not touch the hardware.\n+ **/\n+s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"ixgbe_init_ops_X550\");\n+\n+\tret_val = ixgbe_init_ops_X540(hw);\n+\tmac->ops.dmac_config = &ixgbe_dmac_config_X550;\n+\tmac->ops.dmac_config_tcs = &ixgbe_dmac_config_tcs_X550;\n+\tmac->ops.dmac_update_tcs = &ixgbe_dmac_update_tcs_X550;\n+\tmac->ops.setup_eee = &ixgbe_setup_eee_X550;\n+\tmac->ops.set_source_address_pruning =\n+\t\t\t&ixgbe_set_source_address_pruning_X550;\n+\tmac->ops.set_ethertype_anti_spoofing =\n+\t\t\t&ixgbe_set_ethertype_anti_spoofing_X550;\n+\n+\tmac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;\n+\teeprom->ops.init_params = &ixgbe_init_eeprom_params_X550;\n+\teeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X550;\n+\teeprom->ops.read = &ixgbe_read_ee_hostif_X550;\n+\teeprom->ops.read_buffer = &ixgbe_read_ee_hostif_buffer_X550;\n+\teeprom->ops.write = &ixgbe_write_ee_hostif_X550;\n+\teeprom->ops.write_buffer = &ixgbe_write_ee_hostif_buffer_X550;\n+\teeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X550;\n+\teeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X550;\n+\n+\tmac->ops.disable_mdd = &ixgbe_disable_mdd_X550;\n+\tmac->ops.enable_mdd = &ixgbe_enable_mdd_X550;\n+\tmac->ops.mdd_event = &ixgbe_mdd_event_X550;\n+\tmac->ops.restore_mdd_vf = &ixgbe_restore_mdd_vf_X550;\n+\tmac->ops.disable_rx = &ixgbe_disable_rx_x550;\n+\treturn ret_val;\n+}\n+\n+/**\n+ * ixgbe_identify_phy_x550em - Get PHY type based on device id\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns error code\n+ */\n+STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)\n+{\n+\tu32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\n+\tswitch (hw->device_id) {\n+\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n+\t\t/* set up for CS4227 usage */\n+\t\thw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &\n+\t\t\t\t IXGBE_STATUS_LAN_ID_1;\n+\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;\n+\t\tif (hw->phy.lan_id) {\n+\n+\t\t\tesdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);\n+\t\t\tesdp |= IXGBE_ESDP_SDP1_DIR;\n+\t\t}\n+\t\tesdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\n+\t\treturn ixgbe_identify_module_generic(hw);\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n+\t\thw->phy.type = ixgbe_phy_x550em_kx4;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550EM_X_KR:\n+\tcase IXGBE_DEV_ID_X550EM_X:\n+\t\thw->phy.type = ixgbe_phy_x550em_kr;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t\t     u32 device_type, u16 *phy_data)\n+{\n+\tUNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);\n+\treturn IXGBE_NOT_IMPLEMENTED;\n+}\n+\n+STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t\t      u32 device_type, u16 phy_data)\n+{\n+\tUNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);\n+\treturn IXGBE_NOT_IMPLEMENTED;\n+}\n+\n+/**\n+*  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type\n+*  @hw: pointer to hardware structure\n+*\n+*  Initialize the function pointers and for MAC type X550EM.\n+*  Does not touch the hardware.\n+**/\n+s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\n+\tDEBUGFUNC(\"ixgbe_init_ops_X550EM\");\n+\n+\t/* Similar to X550 so start there. */\n+\tret_val = ixgbe_init_ops_X550(hw);\n+\n+\t/* Since this function eventually calls\n+\t * ixgbe_init_ops_540 by design, we are setting\n+\t * the pointers to NULL explicitly here to overwrite\n+\t * the values being set in the x540 function.\n+\t */\n+\t/* Thermal sensor not supported in x550EM */\n+\tmac->ops.get_thermal_sensor_data = NULL;\n+\tmac->ops.init_thermal_sensor_thresh = NULL;\n+\tmac->thermal_sensor_enabled = false;\n+\n+\t/* FCOE not supported in x550EM */\n+\tmac->ops.get_san_mac_addr = NULL;\n+\tmac->ops.set_san_mac_addr = NULL;\n+\tmac->ops.get_wwn_prefix = NULL;\n+\tmac->ops.get_fcoe_boot_status = NULL;\n+\n+\t/* IPsec not supported in x550EM */\n+\tmac->ops.disable_sec_rx_path = NULL;\n+\tmac->ops.enable_sec_rx_path = NULL;\n+\n+\t/* PCIe bus info not supported in X550EM */\n+\tmac->ops.get_bus_info = NULL;\n+\n+\tmac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;\n+\tmac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;\n+\tmac->ops.get_media_type = &ixgbe_get_media_type_X550em;\n+\tmac->ops.setup_sfp = &ixgbe_setup_sfp_modules_X550em;\n+\tmac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_X550em;\n+\tmac->ops.reset_hw = &ixgbe_reset_hw_X550em;\n+\tmac->ops.get_supported_physical_layer =\n+\t\t\t\t    &ixgbe_get_supported_physical_layer_X550em;\n+\n+\t/* PHY */\n+\tphy->ops.init = &ixgbe_init_phy_ops_X550em;\n+\tphy->ops.identify = &ixgbe_identify_phy_x550em;\n+\tphy->ops.read_reg = ixgbe_read_phy_reg_x550em;\n+\tphy->ops.write_reg = ixgbe_write_phy_reg_x550em;\n+\tphy->ops.setup_link = ixgbe_setup_kr_x550em;\n+\n+\n+\t/* EEPROM */\n+\teeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;\n+\teeprom->ops.read = &ixgbe_read_ee_hostif_X550;\n+\teeprom->ops.read_buffer = &ixgbe_read_ee_hostif_buffer_X550;\n+\teeprom->ops.write = &ixgbe_write_ee_hostif_X550;\n+\teeprom->ops.write_buffer = &ixgbe_write_ee_hostif_buffer_X550;\n+\teeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X550;\n+\teeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X550;\n+\teeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X550;\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  ixgbe_dmac_config_X550\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Configure DMA coalescing. If enabling dmac, dmac is activated.\n+ *  When disabling dmac, dmac enable dmac bit is cleared.\n+ **/\n+s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)\n+{\n+\tu32 reg, high_pri_tc;\n+\n+\tDEBUGFUNC(\"ixgbe_dmac_config_X550\");\n+\n+\t/* Disable DMA coalescing before configuring */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n+\treg &= ~IXGBE_DMACR_DMAC_EN;\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n+\n+\t/* Disable DMA Coalescing if the watchdog timer is 0 */\n+\tif (!hw->mac.dmac_config.watchdog_timer)\n+\t\tgoto out;\n+\n+\tixgbe_dmac_config_tcs_X550(hw);\n+\n+\t/* Configure DMA Coalescing Control Register */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n+\n+\t/* Set the watchdog timer in units of 40.96 usec */\n+\treg &= ~IXGBE_DMACR_DMACWT_MASK;\n+\treg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;\n+\n+\treg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;\n+\t/* If fcoe is enabled, set high priority traffic class */\n+\tif (hw->mac.dmac_config.fcoe_en) {\n+\t\thigh_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;\n+\t\treg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &\n+\t\t\tIXGBE_DMACR_HIGH_PRI_TC_MASK);\n+\t}\n+\treg |= IXGBE_DMACR_EN_MNG_IND;\n+\n+\t/* Enable DMA coalescing after configuration */\n+\treg |= IXGBE_DMACR_DMAC_EN;\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n+\n+out:\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_dmac_config_tcs_X550\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Configure DMA coalescing threshold per TC. The dmac enable bit must\n+ *  be cleared before configuring.\n+ **/\n+s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)\n+{\n+\tu32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;\n+\n+\tDEBUGFUNC(\"ixgbe_dmac_config_tcs_X550\");\n+\n+\t/* Configure DMA coalescing enabled */\n+\tswitch (hw->mac.dmac_config.link_speed) {\n+\tcase IXGBE_LINK_SPEED_100_FULL:\n+\t\tpb_headroom = IXGBE_DMACRXT_100M;\n+\t\tbreak;\n+\tcase IXGBE_LINK_SPEED_1GB_FULL:\n+\t\tpb_headroom = IXGBE_DMACRXT_1G;\n+\t\tbreak;\n+\tdefault:\n+\t\tpb_headroom = IXGBE_DMACRXT_10G;\n+\t\tbreak;\n+\t}\n+\n+\tmaxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>\n+\t\t\t     IXGBE_MHADD_MFS_SHIFT) / 1024);\n+\n+\t/* Set the per Rx packet buffer receive threshold */\n+\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {\n+\t\treg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));\n+\t\treg &= ~IXGBE_DMCTH_DMACRXT_MASK;\n+\n+\t\tif (tc < hw->mac.dmac_config.num_tcs) {\n+\t\t\t/* Get Rx PB size */\n+\t\t\trx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));\n+\t\t\trx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>\n+\t\t\t\tIXGBE_RXPBSIZE_SHIFT;\n+\n+\t\t\t/* Calculate receive buffer threshold in kilobytes */\n+\t\t\tif (rx_pb_size > pb_headroom)\n+\t\t\t\trx_pb_size = rx_pb_size - pb_headroom;\n+\t\t\telse\n+\t\t\t\trx_pb_size = 0;\n+\n+\t\t\t/* Minimum of MFS shall be set for DMCTH */\n+\t\t\treg |= (rx_pb_size > maxframe_size_kb) ?\n+\t\t\t\trx_pb_size : maxframe_size_kb;\n+\t\t}\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);\n+\t}\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_dmac_update_tcs_X550\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Disables dmac, updates per TC settings, and then enables dmac.\n+ **/\n+s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)\n+{\n+\tu32 reg;\n+\n+\tDEBUGFUNC(\"ixgbe_dmac_update_tcs_X550\");\n+\n+\t/* Disable DMA coalescing before configuring */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n+\treg &= ~IXGBE_DMACR_DMAC_EN;\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n+\n+\tixgbe_dmac_config_tcs_X550(hw);\n+\n+\t/* Enable DMA coalescing after configuration */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n+\treg |= IXGBE_DMACR_DMAC_EN;\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ *  ixgbe_hw struct in order to set up EEPROM access.\n+ **/\n+s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tu32 eec;\n+\tu16 eeprom_size;\n+\n+\tDEBUGFUNC(\"ixgbe_init_eeprom_params_X550\");\n+\n+\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n+\t\teeprom->semaphore_delay = 10;\n+\t\teeprom->type = ixgbe_flash;\n+\n+\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n+\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n+\t\t\t\t    IXGBE_EEC_SIZE_SHIFT);\n+\t\teeprom->word_size = 1 << (eeprom_size +\n+\t\t\t\t\t  IXGBE_EEPROM_WORD_SIZE_SHIFT);\n+\n+\t\tDEBUGOUT2(\"Eeprom params: type = %d, size = %d\\n\",\n+\t\t\t  eeprom->type, eeprom->word_size);\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_setup_eee_X550 - Enable/disable EEE support\n+ *  @hw: pointer to the HW structure\n+ *  @enable_eee: boolean flag to enable EEE\n+ *\n+ *  Enable/disable EEE based on enable_eee flag.\n+ *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n+ *  are modified.\n+ *\n+ **/\n+s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)\n+{\n+\tu32 eeer;\n+\tu16 autoneg_eee_reg;\n+\tu32 link_reg;\n+\ts32 status;\n+\n+\tDEBUGFUNC(\"ixgbe_setup_eee_X550\");\n+\n+\teeer = IXGBE_READ_REG(hw, IXGBE_EEER);\n+\t/* Enable or disable EEE per flag */\n+\tif (enable_eee) {\n+\t\teeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);\n+\n+\t\tif (hw->device_id == IXGBE_DEV_ID_X550T) {\n+\t\t\t/* Advertise EEE capability */\n+\t\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n+\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);\n+\n+\t\t\tautoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |\n+\t\t\t\tIXGBE_AUTO_NEG_1000BASE_EEE_ADVT |\n+\t\t\t\tIXGBE_AUTO_NEG_100BASE_EEE_ADVT);\n+\n+\t\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n+\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);\n+\t\t} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||\n+\t\t\t   hw->device_id == IXGBE_DEV_ID_X550EM_X) {\n+\t\t\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\treturn status;\n+\n+\t\t\tlink_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |\n+\t\t\t\t    IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;\n+\n+\t\t\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\treturn status;\n+\t\t}\n+\t} else {\n+\t\teeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);\n+\n+\t\tif (hw->device_id == IXGBE_DEV_ID_X550T) {\n+\t\t\t/* Disable advertised EEE capability */\n+\t\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n+\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);\n+\n+\t\t\tautoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |\n+\t\t\t\tIXGBE_AUTO_NEG_1000BASE_EEE_ADVT |\n+\t\t\t\tIXGBE_AUTO_NEG_100BASE_EEE_ADVT);\n+\n+\t\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n+\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);\n+\t\t} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||\n+\t\t\t   hw->device_id == IXGBE_DEV_ID_X550EM_X) {\n+\t\t\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\treturn status;\n+\n+\t\t\tlink_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |\n+\t\t\t\tIXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);\n+\n+\t\t\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\treturn status;\n+\t\t}\n+\t}\n+\tIXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable source address pruning\n+ * @pool: Rx pool to set source address pruning for\n+ **/\n+void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,\n+\t\t\t\t\t   unsigned int pool)\n+{\n+\tu64 pfflp;\n+\n+\t/* max rx pool is 63 */\n+\tif (pool > 63)\n+\t\treturn;\n+\n+\tpfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);\n+\tpfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;\n+\n+\tif (enable)\n+\t\tpfflp |= (1ULL << pool);\n+\telse\n+\t\tpfflp &= ~(1ULL << pool);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);\n+\tIXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));\n+}\n+\n+/**\n+ *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing\n+ *  @hw: pointer to hardware structure\n+ *  @enable: enable or disable switch for Ethertype anti-spoofing\n+ *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n+ *\n+ **/\n+void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,\n+\t\tbool enable, int vf)\n+{\n+\tint vf_target_reg = vf >> 3;\n+\tint vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;\n+\tu32 pfvfspoof;\n+\n+\tDEBUGFUNC(\"ixgbe_set_ethertype_anti_spoofing_X550\");\n+\n+\tpfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));\n+\tif (enable)\n+\t\tpfvfspoof |= (1 << vf_target_shift);\n+\telse\n+\t\tpfvfspoof &= ~(1 << vf_target_shift);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);\n+}\n+\n+/**\n+ *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF\n+ *  device\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit PHY register to write\n+ *  @device_type: 3 bit device type\n+ *  @data: Data to write to the register\n+ **/\n+s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t    u32 device_type, u32 data)\n+{\n+\tu32 i, command, error;\n+\n+\tcommand = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |\n+\t\t   (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));\n+\n+\t/* Write IOSF control register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);\n+\n+\t/* Write IOSF data register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);\n+\t/*\n+\t * Check every 10 usec to see if the address cycle completed.\n+\t * The SB IOSF BUSY bit will clear when the operation is\n+\t * complete\n+\t */\n+\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n+\t\tusec_delay(10);\n+\n+\t\tcommand = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);\n+\t\tif ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)\n+\t\t\tbreak;\n+\t}\n+\n+\tif ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {\n+\t\terror = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>\n+\t\t\t IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;\n+\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n+\t\t\t      \"Failed to write, error %x\\n\", error);\n+\t\treturn IXGBE_ERR_PHY;\n+\t}\n+\n+\tif (i == IXGBE_MDIO_COMMAND_TIMEOUT) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"Write timed out\\n\");\n+\t\treturn IXGBE_ERR_PHY;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF\n+ *  device\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit PHY register to write\n+ *  @device_type: 3 bit device type\n+ *  @phy_data: Pointer to read data from the register\n+ **/\n+s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t   u32 device_type, u32 *data)\n+{\n+\tu32 i, command, error;\n+\n+\tcommand = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |\n+\t\t   (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));\n+\n+\t/* Write IOSF control register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);\n+\n+\t/*\n+\t * Check every 10 usec to see if the address cycle completed.\n+\t * The SB IOSF BUSY bit will clear when the operation is\n+\t * complete\n+\t */\n+\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n+\t\tusec_delay(10);\n+\n+\t\tcommand = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);\n+\t\tif ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)\n+\t\t\tbreak;\n+\t}\n+\n+\tif ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {\n+\t\terror = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>\n+\t\t\t IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;\n+\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n+\t\t\t\t\"Failed to read, error %x\\n\", error);\n+\t\treturn IXGBE_ERR_PHY;\n+\t}\n+\n+\tif (i == IXGBE_MDIO_COMMAND_TIMEOUT) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"Read timed out\\n\");\n+\t\treturn IXGBE_ERR_PHY;\n+\t}\n+\n+\t*data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_disable_mdd_X550\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Disable malicious driver detection\n+ **/\n+void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)\n+{\n+\tu32 reg;\n+\n+\tDEBUGFUNC(\"ixgbe_disable_mdd_X550\");\n+\n+\t/* Disable MDD for TX DMA and interrupt */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n+\treg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);\n+\n+\t/* Disable MDD for RX and interrupt */\n+\treg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n+\treg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);\n+\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);\n+}\n+\n+/**\n+ *  ixgbe_enable_mdd_X550\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Enable malicious driver detection\n+ **/\n+void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)\n+{\n+\tu32 reg;\n+\n+\tDEBUGFUNC(\"ixgbe_enable_mdd_X550\");\n+\n+\t/* Enable MDD for TX DMA and interrupt */\n+\treg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n+\treg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);\n+\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);\n+\n+\t/* Enable MDD for RX and interrupt */\n+\treg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n+\treg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);\n+\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);\n+}\n+\n+/**\n+ *  ixgbe_restore_mdd_vf_X550\n+ *  @hw: pointer to hardware structure\n+ *  @vf: vf index\n+ *\n+ *  Restore VF that was disabled during malicious driver detection event\n+ **/\n+void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)\n+{\n+\tu32 idx, reg, num_qs, start_q, bitmask;\n+\n+\tDEBUGFUNC(\"ixgbe_restore_mdd_vf_X550\");\n+\n+\t/* Map VF to queues */\n+\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n+\tswitch (reg & IXGBE_MRQC_MRQE_MASK) {\n+\tcase IXGBE_MRQC_VMDQRT8TCEN:\n+\t\tnum_qs = 8;  /* 16 VFs / pools */\n+\t\tbitmask = 0x000000FF;\n+\t\tbreak;\n+\tcase IXGBE_MRQC_VMDQRSS32EN:\n+\tcase IXGBE_MRQC_VMDQRT4TCEN:\n+\t\tnum_qs = 4;  /* 32 VFs / pools */\n+\t\tbitmask = 0x0000000F;\n+\t\tbreak;\n+\tdefault:            /* 64 VFs / pools */\n+\t\tnum_qs = 2;\n+\t\tbitmask = 0x00000003;\n+\t\tbreak;\n+\t}\n+\tstart_q = vf * num_qs;\n+\n+\t/* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */\n+\tidx = start_q / 32;\n+\treg = 0;\n+\treg |= (bitmask << (start_q % 32));\n+\tIXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);\n+\tIXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);\n+}\n+\n+/**\n+ *  ixgbe_mdd_event_X550\n+ *  @hw: pointer to hardware structure\n+ *  @vf_bitmap: vf bitmap of malicious vfs\n+ *\n+ *  Handle malicious driver detection event.\n+ **/\n+void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)\n+{\n+\tu32 wqbr;\n+\tu32 i, j, reg, q, shift, vf, idx;\n+\n+\tDEBUGFUNC(\"ixgbe_mdd_event_X550\");\n+\n+\t/* figure out pool size for mapping to vf's */\n+\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n+\tswitch (reg & IXGBE_MRQC_MRQE_MASK) {\n+\tcase IXGBE_MRQC_VMDQRT8TCEN:\n+\t\tshift = 3;  /* 16 VFs / pools */\n+\t\tbreak;\n+\tcase IXGBE_MRQC_VMDQRSS32EN:\n+\tcase IXGBE_MRQC_VMDQRT4TCEN:\n+\t\tshift = 2;  /* 32 VFs / pools */\n+\t\tbreak;\n+\tdefault:\n+\t\tshift = 1;  /* 64 VFs / pools */\n+\t\tbreak;\n+\t}\n+\n+\t/* Read WQBR_TX and WQBR_RX and check for malicious queues */\n+\tfor (i = 0; i < 4; i++) {\n+\t\twqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));\n+\t\twqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));\n+\n+\t\tif (!wqbr)\n+\t\t\tcontinue;\n+\n+\t\t/* Get malicious queue */\n+\t\tfor (j = 0; j < 32 && wqbr; j++) {\n+\n+\t\t\tif (!(wqbr & (1 << j)))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Get queue from bitmask */\n+\t\t\tq = j + (i * 32);\n+\n+\t\t\t/* Map queue to vf */\n+\t\t\tvf = (q >> shift);\n+\n+\t\t\t/* Set vf bit in vf_bitmap */\n+\t\t\tidx = vf / 32;\n+\t\t\tvf_bitmap[idx] |= (1 << (vf % 32));\n+\t\t\twqbr &= ~(1 << j);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ *  ixgbe_get_media_type_X550em - Get media type\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Returns the media type (fiber, copper, backplane)\n+ */\n+enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)\n+{\n+\tenum ixgbe_media_type media_type;\n+\n+\tDEBUGFUNC(\"ixgbe_get_media_type_X550em\");\n+\n+\t/* Detect if there is a copper PHY attached. */\n+\tswitch (hw->device_id) {\n+\tcase IXGBE_DEV_ID_X550EM_X:\n+\tcase IXGBE_DEV_ID_X550EM_X_KR:\n+\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n+\t\tmedia_type = ixgbe_media_type_backplane;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n+\t\tmedia_type = ixgbe_media_type_fiber;\n+\t\tbreak;\n+\tdefault:\n+\t\tmedia_type = ixgbe_media_type_unknown;\n+\t\tbreak;\n+\t}\n+\treturn media_type;\n+}\n+\n+/**\n+ *  ixgbe_setup_sfp_modules_X550em - Setup SFP module\n+ *  @hw: pointer to hardware structure\n+ */\n+s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)\n+{\n+\tbool setup_linear;\n+\tu16 reg_slice, edc_mode;\n+\n+\tDEBUGFUNC(\"ixgbe_setup_sfp_modules_X550em\");\n+\n+\tswitch (hw->phy.sfp_type) {\n+\tcase ixgbe_sfp_type_unknown:\n+\t\treturn IXGBE_SUCCESS;\n+\tcase ixgbe_sfp_type_not_present:\n+\t\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n+\tcase ixgbe_sfp_type_da_cu_core0:\n+\tcase ixgbe_sfp_type_da_cu_core1:\n+\t\tsetup_linear = true;\n+\t\tbreak;\n+\tcase ixgbe_sfp_type_srlr_core0:\n+\tcase ixgbe_sfp_type_srlr_core1:\n+\tcase ixgbe_sfp_type_da_act_lmt_core0:\n+\tcase ixgbe_sfp_type_da_act_lmt_core1:\n+\tcase ixgbe_sfp_type_1g_sx_core0:\n+\tcase ixgbe_sfp_type_1g_sx_core1:\n+\tcase ixgbe_sfp_type_1g_lx_core0:\n+\tcase ixgbe_sfp_type_1g_lx_core1:\n+\t\tsetup_linear = false;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n+\t}\n+\n+\tixgbe_init_mac_link_ops_X550em(hw);\n+\thw->phy.ops.reset = NULL;\n+\n+\t/* The CS4227 slice address is the base address + the port-pair reg\n+\t * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.\n+\t */\n+\treg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);\n+\n+\tif (setup_linear)\n+\t\tedc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n+\telse\n+\t\tedc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n+\n+\t/* Configure CS4227 for connection type. */\n+\treturn hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227,\n+\t\t\t\t\t      reg_slice, edc_mode);\n+}\n+\n+/**\n+ *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers\n+ *  @hw: pointer to hardware structure\n+ */\n+void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\n+\tDEBUGFUNC(\"ixgbe_init_mac_link_ops_X550em\");\n+\n+\t/* CS4227 does not support autoneg, so disable the laser control\n+\t * functions for SFP+ fiber\n+\t */\n+\t if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {\n+\t\tmac->ops.disable_tx_laser = NULL;\n+\t\tmac->ops.enable_tx_laser = NULL;\n+\t\tmac->ops.flap_tx_laser = NULL;\n+\t }\n+}\n+\n+/**\n+ *  ixgbe_get_link_capabilities_x550em - Determines link capabilities\n+ *  @hw: pointer to hardware structure\n+ *  @speed: pointer to link speed\n+ *  @autoneg: true when autoneg or autotry is enabled\n+ */\n+s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n+\t\t\t\t       ixgbe_link_speed *speed,\n+\t\t\t\t       bool *autoneg)\n+{\n+\tDEBUGFUNC(\"ixgbe_get_link_capabilities_X550em\");\n+\n+\t/* SFP */\n+\tif (hw->phy.media_type == ixgbe_media_type_fiber) {\n+\n+\t\t/* CS4227 SFP must not enable auto-negotiation */\n+\t\t*autoneg = false;\n+\n+\t\t/* Check if 1G SFP module. */\n+\t\tif (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n+\t\t    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1\n+\t\t    || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n+\t\t    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {\n+\t\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n+\t\t\treturn IXGBE_SUCCESS;\n+\t\t}\n+\n+\t\t/* Link capabilities are based on SFP */\n+\t\tif (hw->phy.multispeed_fiber)\n+\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL |\n+\t\t\t\t  IXGBE_LINK_SPEED_1GB_FULL;\n+\t\telse\n+\t\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n+\t} else {\n+\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL |\n+\t\t\t  IXGBE_LINK_SPEED_1GB_FULL;\n+\t\t*autoneg = true;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Initialize any function pointers that were not able to be\n+ *  set during init_shared_code because the PHY/SFP type was\n+ *  not known.  Perform the SFP init if necessary.\n+ */\n+s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\tu32 esdp;\n+\n+\tDEBUGFUNC(\"ixgbe_init_phy_ops_X550em\");\n+\n+\tif (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tphy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &\n+\t\t\t      IXGBE_STATUS_LAN_ID_1;\n+\t\tphy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;\n+\t\tif (phy->lan_id) {\n+\t\t\tesdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);\n+\t\t\tesdp |= IXGBE_ESDP_SDP1_DIR;\n+\t\t}\n+\t\tesdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t}\n+\n+\t/* Identify the PHY or SFP module */\n+\tret_val = phy->ops.identify(hw);\n+\tif (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)\n+\t\treturn ret_val;\n+\n+\t/* Setup function pointers based on detected SFP module and speeds */\n+\tixgbe_init_mac_link_ops_X550em(hw);\n+\tif (phy->sfp_type != ixgbe_sfp_type_unknown)\n+\t\tphy->ops.reset = NULL;\n+\n+\t/* Set functions pointers based on phy type */\n+\tswitch (hw->phy.type) {\n+\tcase ixgbe_phy_x550em_kr:\n+\t\tphy->ops.setup_link = ixgbe_setup_kr_x550em;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn ret_val;\n+}\n+\n+/**\n+ *  ixgbe_reset_hw_X550em - Perform hardware reset\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Resets the hardware by resetting the transmit and receive units, masks\n+ *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n+ *  reset.\n+ */\n+s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)\n+{\n+\tixgbe_link_speed link_speed;\n+\ts32 status;\n+\tu32 ctrl = 0;\n+\tu32 i;\n+\tbool link_up = false;\n+\n+\tDEBUGFUNC(\"ixgbe_reset_hw_X550em\");\n+\n+\t/* Call adapter stop to disable Tx/Rx and clear interrupts */\n+\tstatus = hw->mac.ops.stop_adapter(hw);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* flush pending Tx transactions */\n+\tixgbe_clear_tx_pending(hw);\n+\n+\t/* PHY ops must be identified and initialized prior to reset */\n+\n+\t/* Identify PHY and related function pointers */\n+\tstatus = hw->phy.ops.init(hw);\n+\n+\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n+\t\treturn status;\n+\n+\t/* Setup SFP module if there is one present. */\n+\tif (hw->phy.sfp_setup_needed) {\n+\t\tstatus = hw->mac.ops.setup_sfp(hw);\n+\t\thw->phy.sfp_setup_needed = false;\n+\t}\n+\n+\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n+\t\treturn status;\n+\n+\t/* Reset PHY */\n+\tif (!hw->phy.reset_disable && hw->phy.ops.reset)\n+\t\thw->phy.ops.reset(hw);\n+\n+mac_reset_top:\n+\t/* Issue global reset to the MAC.  Needs to be SW reset if link is up.\n+\t * If link reset is used when link is up, it might reset the PHY when\n+\t * mng is using it.  If link is down or the flag to force full link\n+\t * reset is set, then perform link reset.\n+\t */\n+\tctrl = IXGBE_CTRL_LNK_RST;\n+\tif (!hw->force_full_reset) {\n+\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n+\t\tif (link_up)\n+\t\t\tctrl = IXGBE_CTRL_RST;\n+\t}\n+\n+\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\t/* Poll for reset bit to self-clear meaning reset is complete */\n+\tfor (i = 0; i < 10; i++) {\n+\t\tusec_delay(1);\n+\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n+\t\tstatus = IXGBE_ERR_RESET_FAILED;\n+\t\tDEBUGOUT(\"Reset polling failed to complete.\\n\");\n+\t}\n+\n+\tmsec_delay(50);\n+\n+\t/* Double resets are required for recovery from certain error\n+\t * conditions.  Between resets, it is necessary to stall to\n+\t * allow time for any pending HW events to complete.\n+\t */\n+\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n+\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n+\t\tgoto mac_reset_top;\n+\t}\n+\n+\t/* Store the permanent mac address */\n+\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n+\n+\t/* Store MAC address from RAR0, clear receive address registers, and\n+\t * clear the multicast table.  Also reset num_rar_entries to 128,\n+\t * since we modify this value when programming the SAN MAC address.\n+\t */\n+\thw->mac.num_rar_entries = 128;\n+\thw->mac.ops.init_rx_addrs(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_setup_kr_x550em - Configure the KR PHY.\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Configures the integrated KR PHY.\n+ **/\n+s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu32 reg_val;\n+\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;\n+\treg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |\n+\t\t     IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);\n+\n+\t/* Advertise 10G support. */\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n+\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;\n+\n+\t/* Advertise 1G support. */\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n+\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;\n+\n+\t/* Restart auto-negotiation. */\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Configures the integrated KR PHY to use iXFI mode.\n+ **/\n+s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu32 reg_val;\n+\n+\t/* Disable AN and force speed to 10G Serial. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n+\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Disable training protocol FSM. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Disable Flex from training TXFFE. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;\n+\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Enable override for coefficients. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;\n+\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;\n+\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;\n+\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\tIXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Toggle port SW reset by AN reset. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Configures the integrated KR PHY to use internal loopback mode.\n+ **/\n+s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu32 reg_val;\n+\n+\t/* Disable AN and force speed to 10G Serial. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n+\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;\n+\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Set near-end loopback clocks. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;\n+\treg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Set loopback enable. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* Training bypass. */\n+\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\treg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;\n+\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n+\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),\n+\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n+ *  assuming that the semaphore is already obtained.\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to read\n+ *  @data: word read from the EEPROM\n+ *\n+ *  Reads a 16 bit word from the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t   u16 *data)\n+{\n+\ts32 status;\n+\tstruct ixgbe_hic_read_shadow_ram buffer;\n+\n+\tDEBUGFUNC(\"ixgbe_read_ee_hostif_data_X550\");\n+\tbuffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;\n+\tbuffer.hdr.buf_len1 = 0;\n+\tbuffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;\n+\tbuffer.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\n+\t/* convert offset from words to bytes */\n+\tbuffer.address = IXGBE_CPU_TO_BE32(offset * 2);\n+\t/* one word */\n+\tbuffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));\n+\n+\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n+\t\t\t\t\t      sizeof(buffer), false);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\t*data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,\n+\t\t\t\t\t  FW_NVM_DATA_OFFSET);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to read\n+ *  @data: word read from the EEPROM\n+ *\n+ *  Reads a 16 bit word from the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t      u16 *data)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\n+\tDEBUGFUNC(\"ixgbe_read_ee_hostif_X550\");\n+\n+\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n+\t    IXGBE_SUCCESS) {\n+\t\tstatus = ixgbe_read_ee_hostif_data_X550(hw, offset, data);\n+\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+\t} else {\n+\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to read\n+ *  @words: number of words\n+ *  @data: word(s) read from the EEPROM\n+ *\n+ *  Reads a 16 bit word(s) from the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n+\t\t\t\t     u16 offset, u16 words, u16 *data)\n+{\n+\tstruct ixgbe_hic_read_shadow_ram buffer;\n+\tu32 current_word = 0;\n+\tu16 words_to_read;\n+\ts32 status;\n+\tu32 i;\n+\n+\tDEBUGFUNC(\"ixgbe_read_ee_hostif_buffer_X550\");\n+\n+\t/* Take semaphore for the entire operation. */\n+\tstatus = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+\tif (status) {\n+\t\tDEBUGOUT(\"EEPROM read buffer - semaphore failed\\n\");\n+\t\treturn status;\n+\t}\n+\twhile (words) {\n+\t\tif (words > FW_MAX_READ_BUFFER_SIZE / 2)\n+\t\t\twords_to_read = FW_MAX_READ_BUFFER_SIZE / 2;\n+\t\telse\n+\t\t\twords_to_read = words;\n+\n+\t\tbuffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;\n+\t\tbuffer.hdr.buf_len1 = 0;\n+\t\tbuffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;\n+\t\tbuffer.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\n+\t\t/* convert offset from words to bytes */\n+\t\tbuffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);\n+\t\tbuffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);\n+\n+\t\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n+\t\t\t\t\t\t      sizeof(buffer), false);\n+\n+\t\tif (status) {\n+\t\t\tDEBUGOUT(\"Host interface command failed\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tfor (i = 0; i < words_to_read; i++) {\n+\t\t\tu32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +\n+\t\t\t\t  2 * i;\n+\t\t\tu32 value = IXGBE_READ_REG(hw, reg);\n+\n+\t\t\tdata[current_word] = (u16)(value & 0xffff);\n+\t\t\tcurrent_word++;\n+\t\t\ti++;\n+\t\t\tif (i < words_to_read) {\n+\t\t\t\tvalue >>= 16;\n+\t\t\t\tdata[current_word] = (u16)(value & 0xffff);\n+\t\t\t\tcurrent_word++;\n+\t\t\t}\n+\t\t}\n+\t\twords -= words_to_read;\n+\t}\n+\n+out:\n+\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to write\n+ *  @data: word write to the EEPROM\n+ *\n+ *  Write a 16 bit word to the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t    u16 data)\n+{\n+\ts32 status;\n+\tstruct ixgbe_hic_write_shadow_ram buffer;\n+\n+\tDEBUGFUNC(\"ixgbe_write_ee_hostif_data_X550\");\n+\n+\tbuffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;\n+\tbuffer.hdr.buf_len1 = 0;\n+\tbuffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;\n+\tbuffer.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\n+\t /* one word */\n+\tbuffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));\n+\tbuffer.data = data;\n+\tbuffer.address = IXGBE_CPU_TO_BE32(offset * 2);\n+\n+\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n+\t\t\t\t\t      sizeof(buffer), false);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to write\n+ *  @data: word write to the EEPROM\n+ *\n+ *  Write a 16 bit word to the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t       u16 data)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\n+\tDEBUGFUNC(\"ixgbe_write_ee_hostif_X550\");\n+\n+\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n+\t    IXGBE_SUCCESS) {\n+\t\tstatus = ixgbe_write_ee_hostif_data_X550(hw, offset, data);\n+\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+\t} else {\n+\t\tDEBUGOUT(\"write ee hostif failed to get semaphore\");\n+\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif\n+ *  @hw: pointer to hardware structure\n+ *  @offset: offset of  word in the EEPROM to write\n+ *  @words: number of words\n+ *  @data: word(s) write to the EEPROM\n+ *\n+ *  Write a 16 bit word(s) to the EEPROM using the hostif.\n+ **/\n+s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n+\t\t\t\t      u16 offset, u16 words, u16 *data)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\tu32 i = 0;\n+\n+\tDEBUGFUNC(\"ixgbe_write_ee_hostif_buffer_X550\");\n+\n+\t/* Take semaphore for the entire operation. */\n+\tstatus = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\tDEBUGOUT(\"EEPROM write buffer - semaphore failed\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < words; i++) {\n+\t\tstatus = ixgbe_write_ee_hostif_data_X550(hw, offset + i,\n+\t\t\t\t\t\t\t data[i]);\n+\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\tDEBUGOUT(\"Eeprom buffered write failed\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n+out:\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_checksum_ptr_x550 - Checksum one pointer region\n+ * @hw: pointer to hardware structure\n+ * @ptr: pointer offset in eeprom\n+ * @size: size of section pointed by ptr, if 0 first word will be used as size\n+ * @csum: address of checksum to update\n+ *\n+ * Returns error status for any failure\n+ */\n+STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,\n+\t\t\t\t   u16 size, u16 *csum)\n+{\n+\tu16 buf[256];\n+\ts32 status;\n+\tu16 length, bufsz, i, start;\n+\n+\tbufsz = sizeof(buf) / sizeof(buf[0]);\n+\n+\t/* Read a chunk at the pointer location */\n+\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);\n+\tif (status) {\n+\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tif (size) {\n+\t\tstart = 0;\n+\t\tlength = size;\n+\t} else {\n+\t\tstart = 1;\n+\t\tlength = buf[0];\n+\n+\t\t/* Skip pointer section if length is invalid. */\n+\t\tif (length == 0xFFFF || length == 0 ||\n+\t\t    (ptr + length) >= hw->eeprom.word_size)\n+\t\t\treturn IXGBE_SUCCESS;\n+\t}\n+\n+\tfor (i = start; length; i++, length--) {\n+\t\tif (i == bufsz) {\n+\t\t\tptr += bufsz;\n+\t\t\ti = 0;\n+\t\t\tif (length < bufsz)\n+\t\t\t\tbufsz = length;\n+\n+\t\t\t/* Read a chunk at the pointer location */\n+\t\t\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,\n+\t\t\t\t\t\t\t\t  bufsz, buf);\n+\t\t\tif (status) {\n+\t\t\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n+\t\t\t\treturn status;\n+\t\t\t}\n+\t\t}\n+\t\t*csum += buf[i];\n+\t}\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Returns a negative error code on error, or the 16-bit checksum\n+ **/\n+s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)\n+{\n+\tu16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];\n+\ts32 status;\n+\tu16 checksum = 0;\n+\tu16 pointer, i, size;\n+\n+\tDEBUGFUNC(\"ixgbe_calc_eeprom_checksum_X550\");\n+\n+\thw->eeprom.ops.init_params(hw);\n+\n+\t/* Read pointer area */\n+\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, 0,\n+\t\t\t\t\t\t  IXGBE_EEPROM_LAST_WORD + 1,\n+\t\t\t\t\t\t  eeprom_ptrs);\n+\tif (status) {\n+\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n+\t\treturn status;\n+\t}\n+\n+\t/*\n+\t * For X550 hardware include 0x0-0x41 in the checksum, skip the\n+\t * checksum word itself\n+\t */\n+\tfor (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)\n+\t\tif (i != IXGBE_EEPROM_CHECKSUM)\n+\t\t\tchecksum += eeprom_ptrs[i];\n+\n+\t/*\n+\t * Include all data from pointers 0x3, 0x6-0xE.  This excludes the\n+\t * FW, PHY module, and PCIe Expansion/Option ROM pointers.\n+\t */\n+\tfor (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {\n+\t\tif (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)\n+\t\t\tcontinue;\n+\n+\t\tpointer = eeprom_ptrs[i];\n+\n+\t\t/* Skip pointer section if the pointer is invalid. */\n+\t\tif (pointer == 0xFFFF || pointer == 0 ||\n+\t\t    pointer >= hw->eeprom.word_size)\n+\t\t\tcontinue;\n+\n+\t\tswitch (i) {\n+\t\tcase IXGBE_PCIE_GENERAL_PTR:\n+\t\t\tsize = IXGBE_IXGBE_PCIE_GENERAL_SIZE;\n+\t\t\tbreak;\n+\t\tcase IXGBE_PCIE_CONFIG0_PTR:\n+\t\tcase IXGBE_PCIE_CONFIG1_PTR:\n+\t\t\tsize = IXGBE_PCIE_CONFIG_SIZE;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tsize = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tstatus = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n+\n+\treturn (s32)checksum;\n+}\n+\n+/**\n+ *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum\n+ *  @hw: pointer to hardware structure\n+ *  @checksum_val: calculated checksum\n+ *\n+ *  Performs checksum calculation and validates the EEPROM checksum.  If the\n+ *  caller does not need checksum_val, the value can be NULL.\n+ **/\n+s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,\n+\t\t\t\t\tu16 *checksum_val)\n+{\n+\ts32 status;\n+\tu16 checksum;\n+\tu16 read_checksum = 0;\n+\n+\tDEBUGFUNC(\"ixgbe_validate_eeprom_checksum_X550\");\n+\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n+\t * not continue or we could be in for a very long wait while every\n+\t * EEPROM read fails\n+\t */\n+\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n+\tif (status) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = hw->eeprom.ops.calc_checksum(hw);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\tchecksum = (u16)(status & 0xffff);\n+\n+\tstatus = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,\n+\t\t\t\t\t   &read_checksum);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Verify read checksum from EEPROM is the same as\n+\t * calculated checksum\n+\t */\n+\tif (read_checksum != checksum) {\n+\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n+\t\tERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,\n+\t\t\t     \"Invalid EEPROM checksum\");\n+\t}\n+\n+\t/* If the user cares, return the calculated checksum */\n+\tif (checksum_val)\n+\t\t*checksum_val = checksum;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash\n+ * @hw: pointer to hardware structure\n+ *\n+ * After writing EEPROM to shadow RAM using EEWR register, software calculates\n+ * checksum and updates the EEPROM and instructs the hardware to update\n+ * the flash.\n+ **/\n+s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu16 checksum = 0;\n+\n+\tDEBUGFUNC(\"ixgbe_update_eeprom_checksum_X550\");\n+\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n+\t * not continue or we could be in for a very long wait while every\n+\t * EEPROM read fails\n+\t */\n+\tstatus = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);\n+\tif (status) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_calc_eeprom_checksum_X550(hw);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\tchecksum = (u16)(status & 0xffff);\n+\n+\tstatus = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,\n+\t\t\t\t\t    checksum);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_update_flash_X550(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.\n+ **/\n+s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\tstruct ixgbe_hic_hdr2 buffer;\n+\n+\tDEBUGFUNC(\"ixgbe_update_flash_X550\");\n+\n+\tbuffer.cmd = FW_SHADOW_RAM_DUMP_CMD;\n+\tbuffer.buf_len1 = 0;\n+\tbuffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;\n+\tbuffer.checksum = FW_DEFAULT_CHECKSUM;\n+\n+\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n+\t\t\t\t\t      sizeof(buffer), false);\n+\n+\treturn status;\n+}\n+\n+/**\n+ *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Determines physical layer capabilities of the current configuration.\n+ **/\n+u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)\n+{\n+\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\n+\tDEBUGFUNC(\"ixgbe_get_supported_physical_layer_X550em\");\n+\n+\thw->phy.ops.identify(hw);\n+\n+\tswitch (hw->phy.type) {\n+\tcase ixgbe_phy_x550em_kr:\n+\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |\n+\t\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\t\tbreak;\n+\tcase ixgbe_phy_x550em_kx4:\n+\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |\n+\t\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)\n+\t\tphysical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);\n+\n+\treturn physical_layer;\n+}\n+\n+/**\n+ * ixgbe_disable_rx_x550 - Disable RX unit\n+ *\n+ * Enables the Rx DMA unit for x550\n+ **/\n+void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)\n+{\n+\tu32 rxctrl, pfdtxgswc;\n+\ts32 status;\n+\tstruct ixgbe_hic_disable_rxen fw_cmd;\n+\n+\tDEBUGFUNC(\"ixgbe_enable_rx_dma_x550\");\n+\n+\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n+\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n+\t\tpfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);\n+\t\tif (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {\n+\t\t\tpfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);\n+\t\t\thw->mac.set_lben = true;\n+\t\t} else {\n+\t\t\thw->mac.set_lben = false;\n+\t\t}\n+\n+\t\tfw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;\n+\t\tfw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;\n+\t\tfw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;\n+\t\tfw_cmd.port_number = hw->phy.lan_id;\n+\n+\t\tstatus = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,\n+\t\t\t\t\tsizeof(struct ixgbe_hic_disable_rxen),\n+\t\t\t\t\ttrue);\n+\n+\t\t/* If we fail - disable RX using register write */\n+\t\tif (status) {\n+\t\t\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n+\t\t\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n+\t\t\t\trxctrl &= ~IXGBE_RXCTRL_RXEN;\n+\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h\nnew file mode 100644\nindex 0000000..e8de134\n--- /dev/null\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h\n@@ -0,0 +1,88 @@\n+/*******************************************************************************\n+\n+Copyright (c) 2001-2014, Intel Corporation\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+\n+ 1. Redistributions of source code must retain the above copyright notice,\n+    this list of conditions and the following disclaimer.\n+\n+ 2. Redistributions in binary form must reproduce the above copyright\n+    notice, this list of conditions and the following disclaimer in the\n+    documentation and/or other materials provided with the distribution.\n+\n+ 3. Neither the name of the Intel Corporation nor the names of its\n+    contributors may be used to endorse or promote products derived from\n+    this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+POSSIBILITY OF SUCH DAMAGE.\n+\n+***************************************************************************/\n+\n+#ifndef _IXGBE_X550_H_\n+#define _IXGBE_X550_H_\n+\n+#include \"ixgbe_type.h\"\n+\n+s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,\n+\t\tu16 *checksum_val);\n+s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw);\n+s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n+\t\t\t\t      u16 offset, u16 words, u16 *data);\n+s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t       u16 data);\n+s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n+\t\t\t\t     u16 offset, u16 words, u16 *data);\n+s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n+u16\t\t\t\t*data);\n+s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t   u16 *data);\n+s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t    u16 data);\n+s32 ixgbe_set_eee_X550(struct ixgbe_hw *hw, bool enable_eee);\n+s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee);\n+void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,\n+\t\t\t\t\t   unsigned int pool);\n+void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,\n+\t\t\t\t\t    bool enable, int vf);\n+s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t\t u32 device_type, u32 data);\n+s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u32 *data);\n+void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw);\n+void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw);\n+void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap);\n+void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf);\n+enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw);\n+s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n+\t\t\t\t       ixgbe_link_speed *speed, bool *autoneg);\n+void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw);\n+s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw);\n+s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw);\n+u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);\n+void ixgbe_disable_rx_x550(struct ixgbe_hw *hw);\n+#endif /* _IXGBE_X550_H_ */\n+\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "17/18"
    ]
}