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GET /api/patches/63133/?format=api
{ "id": 63133, "url": "https://patches.dpdk.org/api/patches/63133/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191120034808.2760-6-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191120034808.2760-6-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191120034808.2760-6-pbhagavatula@marvell.com", "date": "2019-11-20T03:48:06", "name": "[v2,5/6] event/octeontx: add appication domain validation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f2a190d39075907c68954f3bc0ec747745a766f1", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191120034808.2760-6-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 7533, "url": "https://patches.dpdk.org/api/series/7533/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7533", "date": "2019-11-20T03:48:01", "name": "octeontx: sync with latest SDK", "version": 2, "mbox": "https://patches.dpdk.org/series/7533/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/63133/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/63133/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C509A04C1;\n\tWed, 20 Nov 2019 04:49:04 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0B31F1BC25;\n\tWed, 20 Nov 2019 04:48:29 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A02782C6D\n for <dev@dpdk.org>; Wed, 20 Nov 2019 04:48:27 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n xAK3kd2L029360 for <dev@dpdk.org>; Tue, 19 Nov 2019 19:48:26 -0800", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0a-0016f401.pphosted.com with ESMTP id 2wc8425sv4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 19 Nov 2019 19:48:26 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 19 Nov\n 2019 19:48:25 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n Transport; Tue, 19 Nov 2019 19:48:25 -0800", "from BG-LT7430.marvell.com (unknown [10.28.17.72])\n by maili.marvell.com (Postfix) with ESMTP id 9E5503F703F;\n Tue, 19 Nov 2019 19:48:23 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=sKvBKfLxrxVZBCS6nS63ZXSnyLcbhpxIu/DCPzRKeZc=;\n b=I2NCHC4MCc9cGh3YmhOoQtvu8fZ2xpgOmnQ0r+ug9dx+Zckp3OzzXqxQS82VdhKxy1bT\n FKESQoZlAlIr4BG1lhbxo35l0Tv78UD2+7z4rT4mIa79roicJzNZCtIqIVU/9hUf1XR8\n +/f92WNsHh/V+N4gyF+oSEL0Ic13QhUQk3cMldAkWCZmOAVRx+93o2SzBr/2M9+0iiBA\n IgdbUVzmIcFFTYP8i2j9KkOXCFFCID0Q0HEpdrgTefmRVNXGmU3iO8rpqDlXLLwTR8Gg\n 1dbopEfrw4ajRHPFCfH4XP7x+6U+ps1FOajUr1hqKZUeCA362qv2uH4tDEk3wUh7bOev Hg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Wed, 20 Nov 2019 09:18:06 +0530", "Message-ID": "<20191120034808.2760-6-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20191120034808.2760-1-pbhagavatula@marvell.com>", "References": "<20191120034808.2760-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2019-11-19_08:2019-11-15,2019-11-19 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 5/6] event/octeontx: add appication domain\n\tvalidation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd applicaton domain validation for OCTEON TX TIM vfs aka Event timer.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx/timvf_evdev.c | 12 ++---\n drivers/event/octeontx/timvf_evdev.h | 8 +---\n drivers/event/octeontx/timvf_probe.c | 65 ++++++++++++++++++----------\n 3 files changed, 49 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c\nindex abbc9a775..caa129087 100644\n--- a/drivers/event/octeontx/timvf_evdev.c\n+++ b/drivers/event/octeontx/timvf_evdev.c\n@@ -231,17 +231,15 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr)\n {\n \tchar pool_name[25];\n \tint ret;\n+\tuint8_t tim_ring_id;\n \tuint64_t nb_timers;\n \tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n \tstruct timvf_ring *timr;\n-\tstruct timvf_info tinfo;\n \tconst char *mempool_ops;\n \tunsigned int mp_flags = 0;\n \n-\tif (timvf_info(&tinfo) < 0)\n-\t\treturn -ENODEV;\n-\n-\tif (adptr->data->id >= tinfo.total_timvfs)\n+\ttim_ring_id = timvf_get_ring();\n+\tif (tim_ring_id == UINT8_MAX)\n \t\treturn -ENODEV;\n \n \ttimr = rte_zmalloc(\"octeontx_timvf_priv\",\n@@ -259,7 +257,7 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr)\n \t}\n \n \ttimr->clk_src = (int) rcfg->clk_src;\n-\ttimr->tim_ring_id = adptr->data->id;\n+\ttimr->tim_ring_id = tim_ring_id;\n \ttimr->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);\n \ttimr->max_tout = rcfg->max_tmo_ns;\n \ttimr->nb_bkts = (timr->max_tout / timr->tck_nsec);\n@@ -337,8 +335,10 @@ static int\n timvf_ring_free(struct rte_event_timer_adapter *adptr)\n {\n \tstruct timvf_ring *timr = adptr->data->adapter_priv;\n+\n \trte_mempool_free(timr->chunk_pool);\n \trte_free(timr->bkt);\n+\ttimvf_release_ring(timr->tim_ring_id);\n \trte_free(adptr->data->adapter_priv);\n \treturn 0;\n }\ndiff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h\nindex 0185593f1..d0e5921db 100644\n--- a/drivers/event/octeontx/timvf_evdev.h\n+++ b/drivers/event/octeontx/timvf_evdev.h\n@@ -115,11 +115,6 @@\n extern int otx_logtype_timvf;\n static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;\n \n-struct timvf_info {\n-\tuint16_t domain; /* Domain id */\n-\tuint8_t total_timvfs; /* Total timvf available in domain */\n-};\n-\n enum timvf_clk_src {\n \tTIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n \tTIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n@@ -196,7 +191,8 @@ bkt_and(uint32_t rel_bkt, uint32_t nb_bkts)\n \treturn rel_bkt & (nb_bkts - 1);\n }\n \n-int timvf_info(struct timvf_info *tinfo);\n+uint8_t timvf_get_ring(void);\n+void timvf_release_ring(uint8_t vfid);\n void *timvf_bar(uint8_t id, uint8_t bar);\n int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\tuint32_t *caps, const struct rte_event_timer_adapter_ops **ops,\ndiff --git a/drivers/event/octeontx/timvf_probe.c b/drivers/event/octeontx/timvf_probe.c\nindex af87625fd..59bba31e8 100644\n--- a/drivers/event/octeontx/timvf_probe.c\n+++ b/drivers/event/octeontx/timvf_probe.c\n@@ -20,6 +20,7 @@\n #define TIM_MAX_RINGS\t\t\t\t(64)\n \n struct timvf_res {\n+\tuint8_t in_use;\n \tuint16_t domain;\n \tuint16_t vfid;\n \tvoid *bar0;\n@@ -34,50 +35,65 @@ struct timdev {\n \n static struct timdev tdev;\n \n-int\n-timvf_info(struct timvf_info *tinfo)\n+uint8_t\n+timvf_get_ring(void)\n {\n+\tuint16_t global_domain = octeontx_get_global_domain();\n \tint i;\n-\tstruct ssovf_info info;\n \n-\tif (tinfo == NULL)\n-\t\treturn -EINVAL;\n+\tfor (i = 0; i < tdev.total_timvfs; i++) {\n+\t\tif (tdev.rings[i].domain != global_domain)\n+\t\t\tcontinue;\n+\t\tif (tdev.rings[i].in_use)\n+\t\t\tcontinue;\n \n-\tif (!tdev.total_timvfs)\n-\t\treturn -ENODEV;\n+\t\ttdev.rings[i].in_use = true;\n+\t\treturn tdev.rings[i].vfid;\n+\t}\n \n-\tif (ssovf_info(&info) < 0)\n-\t\treturn -EINVAL;\n+\treturn UINT8_MAX;\n+}\n+\n+void\n+timvf_release_ring(uint8_t tim_ring_id)\n+{\n+\tuint16_t global_domain = octeontx_get_global_domain();\n+\tint i;\n \n \tfor (i = 0; i < tdev.total_timvfs; i++) {\n-\t\tif (info.domain != tdev.rings[i].domain) {\n-\t\t\ttimvf_log_err(\"GRP error, vfid=%d/%d domain=%d/%d %p\",\n-\t\t\t\ti, tdev.rings[i].vfid,\n-\t\t\t\tinfo.domain, tdev.rings[i].domain,\n-\t\t\t\ttdev.rings[i].bar0);\n-\t\t\treturn -EINVAL;\n-\t\t}\n+\t\tif (tdev.rings[i].domain != global_domain)\n+\t\t\tcontinue;\n+\t\tif (tdev.rings[i].vfid == tim_ring_id)\n+\t\t\ttdev.rings[i].in_use = false;\n \t}\n-\n-\ttinfo->total_timvfs = tdev.total_timvfs;\n-\ttinfo->domain = info.domain;\n-\treturn 0;\n }\n \n void*\n-timvf_bar(uint8_t id, uint8_t bar)\n+timvf_bar(uint8_t vfid, uint8_t bar)\n {\n+\tuint16_t global_domain = octeontx_get_global_domain();\n+\tstruct timvf_res *res = NULL;\n+\tint i;\n+\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn NULL;\n \n-\tif (id > tdev.total_timvfs)\n+\tfor (i = 0; i < tdev.total_timvfs; i++) {\n+\t\tif (tdev.rings[i].domain != global_domain)\n+\t\t\tcontinue;\n+\t\tif (tdev.rings[i].vfid == vfid)\n+\t\t\tres = &tdev.rings[i];\n+\n+\t}\n+\n+\tif (res == NULL)\n \t\treturn NULL;\n \n \tswitch (bar) {\n \tcase 0:\n-\t\treturn tdev.rings[id].bar0;\n+\t\treturn res->bar0;\n \tcase 4:\n-\t\treturn tdev.rings[id].bar4;\n+\t\treturn res->bar4;\n \tdefault:\n \t\treturn NULL;\n \t}\n@@ -118,6 +134,7 @@ timvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tres->bar2 = pci_dev->mem_resource[2].addr;\n \tres->bar4 = pci_dev->mem_resource[4].addr;\n \tres->domain = (val >> 7) & 0xffff;\n+\tres->in_use = false;\n \ttdev.total_timvfs++;\n \trte_wmb();\n \n", "prefixes": [ "v2", "5/6" ] }