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GET /api/patches/61773/?format=api
{ "id": 61773, "url": "https://patches.dpdk.org/api/patches/61773/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191023152043.17887-1-kirankumark@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191023152043.17887-1-kirankumark@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191023152043.17887-1-kirankumark@marvell.com", "date": "2019-10-23T15:20:41", "name": "[1/2] net/octeontx2: add support to enable switch type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "81f57a2335477320182d95ec8f63d36653a4a22f", "submitter": { "id": 1260, "url": "https://patches.dpdk.org/api/people/1260/?format=api", "name": "Kiran Kumar Kokkilagadda", "email": "kirankumark@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191023152043.17887-1-kirankumark@marvell.com/mbox/", "series": [ { "id": 7018, "url": "https://patches.dpdk.org/api/series/7018/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7018", "date": "2019-10-23T15:20:41", "name": "[1/2] net/octeontx2: add support to enable switch type", "version": 1, "mbox": "https://patches.dpdk.org/series/7018/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/61773/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/61773/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 08ADD271;\n\tWed, 23 Oct 2019 17:21:28 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B10801C436\n\tfor <dev@dpdk.org>; Wed, 23 Oct 2019 17:21:25 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx9NFBSRH024657; Wed, 23 Oct 2019 08:21:24 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2vt9u5kccx-2\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tWed, 23 Oct 2019 08:21:24 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tWed, 23 Oct 2019 08:21:23 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Wed, 23 Oct 2019 08:21:23 -0700", "from localhost.localdomain (unknown [10.28.34.15])\n\tby maili.marvell.com (Postfix) with ESMTP id C9F823F703F;\n\tWed, 23 Oct 2019 08:21:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : mime-version : content-type; s=pfpt0818;\n\tbh=2WPS9K+OK9Flolf1vrzwjPWRjvGKH/vQCjBamRwHiQs=;\n\tb=K/nVXoc5HPqnUqWM7TnmX96UQwn4zWKlzRIYlk9XYV4Z8wxKdqezVQMm9+pKMJyIHNaP\n\t/gE5unwSBvYs4H9WaSUbP6RxTHy+DdQLATl5iNPoqxUrgAtZtlnC0g0iR9rVURzrOsCA\n\toPRcxGRC6KlTsTvHSFSuuYl06GNQFnM7eldzb+mRrnr8Q4F29okLiFy2NZbs2E83pwBp\n\t38c6t9ZSfNcK8LTZpNncY+W7VRzqXLiWmuk5ivBrvlgQEGuZ1KPUARqfzoPrYitCoLju\n\t81Bu+zZMjVzkQE7O4Pz+sVx05jxE+ddniW0oq6qHZtRO6j6Zwysm1mIuNgC+jO3+eOR3\n\tog== ", "From": "<kirankumark@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Wed, 23 Oct 2019 20:50:41 +0530", "Message-ID": "<20191023152043.17887-1-kirankumark@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-23_04:2019-10-23,2019-10-23 signatures=0", "Subject": "[dpdk-dev] [PATCH 1/2] net/octeontx2: add support to enable switch\n\ttype", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdding support to configure specific switch types like high2 and dsa\non a port. When this switch type is configured, it is expected that\nall the traffic on that port should be of specific type only.\n\nChange-Id: I41c47c4f8d844666cd6afe20a60397b83908e2f4\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n doc/guides/nics/octeontx2.rst | 12 +++++++++\n drivers/common/octeontx2/otx2_mbox.h | 19 ++++++++++++-\n drivers/net/octeontx2/otx2_ethdev.c | 30 +++++++++++++++++++++\n drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++-\n drivers/net/octeontx2/otx2_flow.h | 1 +\n 5 files changed, 82 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex fc8a130fb..adf7c7131 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -170,6 +170,18 @@ Runtime Config Options\n With the above configuration, each send queue's decscriptor buffer count is\n limited to a maximum of 64 buffers.\n \n+- ``switch header enable`` (default ``none``)\n+\n+ A port can be configured to a specific switch header type by using\n+ ``switch_header`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -w 0002:02:00.0,switch_header=\"higig2\"\n+\n+ With the above configuration, higig2 will be enabled on that port and the\n+ traffic on this port should be higig2 traffic only. Supported switch header\n+ types are \"higig2\" and \"dsa\".\n \n .. note::\n \ndiff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex 445b03e26..c2a9e9fe6 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -89,7 +89,7 @@ struct mbox_msghdr {\n #define OTX2_MBOX_RSP_SIG (0xbeef)\n \t/* Signature, for validating corrupted msgs */\n \tuint16_t __otx2_io sig;\n-#define OTX2_MBOX_VERSION (0x0002)\n+#define OTX2_MBOX_VERSION (0x0003)\n \t/* Version of msg's structure for this ID */\n \tuint16_t __otx2_io ver;\n \t/* Offset of next msg within mailbox region */\n@@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW,\t 0x600e, npc_delete_flow,\t\t\t\\\n M(NPC_MCAM_READ_ENTRY,\t 0x600f, npc_mcam_read_entry,\t\t\t\\\n \t\t\t\t npc_mcam_read_entry_req,\t\t\\\n \t\t\t\t npc_mcam_read_entry_rsp)\t\t\\\n+M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \\\n+\t\t\t\t npc_set_pkind, \\\n+\t\t\t\t msg_rsp) \\\n /* NIX mbox IDs (range 0x8000 - 0xFFFF) */\t\t\t\t\\\n M(NIX_LF_ALLOC,\t\t0x8000, nix_lf_alloc, nix_lf_alloc_req,\t\t\\\n \t\t\t\tnix_lf_alloc_rsp)\t\t\t\\\n@@ -329,6 +332,20 @@ struct ready_msg_rsp {\n \tuint16_t __otx2_io rclk_freq; /* RCLK frequency */\n };\n \n+/* Struct to set pkind */\n+struct npc_set_pkind {\n+\tstruct mbox_msghdr hdr;\n+#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)\n+#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)\n+#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)\n+#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)\n+\tuint64_t __otx2_io mode;\n+#define PKIND_TX\t\tBIT_ULL(0)\n+#define PKIND_RX\t\tBIT_ULL(1)\n+\tuint8_t __otx2_io dir;\n+\tuint8_t __otx2_io pkind; /* valid only in case custom flag */\n+};\n+\n /* Structure for requesting resource provisioning.\n * 'modify' flag to be used when either requesting more\n * or detach partial of a certain resource type.\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 62291c698..dfa8cd205 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)\n \treturn 0;\n }\n \n+static int\n+nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct npc_set_pkind *req;\n+\tstruct msg_resp *rsp;\n+\tint rc;\n+\n+\tif (dev->npc_flow.switch_header_type == 0)\n+\t\treturn 0;\n+\n+\t/* Notify AF about higig2 config */\n+\treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n+\treq->mode = dev->npc_flow.switch_header_type;\n+\treq->dir = PKIND_RX;\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n+\treq->mode = dev->npc_flow.switch_header_type;\n+\treq->dir = PKIND_TX;\n+\treturn otx2_mbox_process_msg(mbox, (void *)&rsp);\n+}\n+\n static int\n nix_lf_free(struct otx2_eth_dev *dev)\n {\n@@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto fail_offloads;\n \t}\n \n+\trc = nix_lf_switch_header_type_enable(dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to enable switch type nix_lf rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n \trc = nix_setup_lso_formats(dev);\n \tif (rc) {\n \t\totx2_err(\"failed to setup nix lso format fields, rc=%d\", rc);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c\nindex 7dc6e92be..ca9a5ffb8 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c\n@@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args)\n \treturn 0;\n }\n \n+static int\n+parse_switch_header_type(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\tif (strcmp(value, \"higig2\") == 0)\n+\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;\n+\n+\tif (strcmp(value, \"dsa\") == 0)\n+\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;\n+\n+\treturn 0;\n+}\n+\n #define OTX2_RSS_RETA_SIZE \"reta_size\"\n #define OTX2_PTYPE_DISABLE \"ptype_disable\"\n #define OTX2_SCL_ENABLE \"scalar_enable\"\n #define OTX2_MAX_SQB_COUNT \"max_sqb_count\"\n #define OTX2_FLOW_PREALLOC_SIZE \"flow_prealloc_size\"\n #define OTX2_FLOW_MAX_PRIORITY \"flow_max_priority\"\n+#define OTX2_SWITCH_HEADER_TYPE \"switch_header\"\n \n int\n otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n@@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n \tuint16_t rss_size = NIX_RSS_RETA_SIZE;\n \tuint16_t sqb_count = NIX_MAX_SQB;\n \tuint16_t flow_prealloc_size = 8;\n+\tuint16_t switch_header_type = 0;\n \tuint16_t flow_max_priority = 3;\n \tuint16_t scalar_enable = 0;\n \tstruct rte_kvargs *kvlist;\n@@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n \t\t\t &parse_flow_prealloc_size, &flow_prealloc_size);\n \trte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,\n \t\t\t &parse_flow_max_priority, &flow_max_priority);\n+\trte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,\n+\t\t\t &parse_switch_header_type, &switch_header_type);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n@@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n \tdev->rss_info.rss_size = rss_size;\n \tdev->npc_flow.flow_prealloc_size = flow_prealloc_size;\n \tdev->npc_flow.flow_max_priority = flow_max_priority;\n+\tdev->npc_flow.switch_header_type = switch_header_type;\n \treturn 0;\n \n exit:\n@@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,\n \t\t\t OTX2_SCL_ENABLE \"=1\"\n \t\t\t OTX2_MAX_SQB_COUNT \"=<8-512>\"\n \t\t\t OTX2_FLOW_PREALLOC_SIZE \"=<1-32>\"\n-\t\t\t OTX2_FLOW_MAX_PRIORITY \"=<1-32>\");\n+\t\t\t OTX2_FLOW_MAX_PRIORITY \"=<1-32>\"\n+\t\t\t OTX2_SWITCH_HEADER_TYPE \"=<higig2|dsa>\");\ndiff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h\nindex ab068b088..6bfd5afde 100644\n--- a/drivers/net/octeontx2/otx2_flow.h\n+++ b/drivers/net/octeontx2/otx2_flow.h\n@@ -190,6 +190,7 @@ struct otx2_npc_flow_info {\n \tuint16_t channel; /*rx channel */\n \tuint16_t flow_prealloc_size;\n \tuint16_t flow_max_priority;\n+\tuint16_t switch_header_type;\n };\n \n struct otx2_parse_state {\n", "prefixes": [ "1/2" ] }