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GET /api/patches/61339/?format=api
{ "id": 61339, "url": "https://patches.dpdk.org/api/patches/61339/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191016183356.350766-3-ying.a.wang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191016183356.350766-3-ying.a.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191016183356.350766-3-ying.a.wang@intel.com", "date": "2019-10-16T18:33:53", "name": "[v5,2/5] net/ice: add devargs to control pipeline mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "11dfe67daf2ae4a651e91c4ba1de47dd13ab530c", "submitter": { "id": 1280, "url": "https://patches.dpdk.org/api/people/1280/?format=api", "name": "Ying Wang", "email": "ying.a.wang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191016183356.350766-3-ying.a.wang@intel.com/mbox/", "series": [ { "id": 6890, "url": "https://patches.dpdk.org/api/series/6890/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6890", "date": "2019-10-16T18:33:52", "name": "rework for ice generic flow framework and switch filter", "version": 5, "mbox": "https://patches.dpdk.org/series/6890/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/61339/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/61339/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 86FAC1D50F;\n\tThu, 17 Oct 2019 04:57:26 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id A75DE1D449\n\tfor <dev@dpdk.org>; Thu, 17 Oct 2019 04:57:20 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Oct 2019 19:57:20 -0700", "from unknown (HELO npg-dpdk-cvl-yingwang-117d84.sh.intel.com)\n\t([10.67.117.96])\n\tby fmsmga004.fm.intel.com with ESMTP; 16 Oct 2019 19:57:18 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.67,306,1566889200\"; d=\"scan'208\";a=\"220980617\"", "From": "Ying Wang <ying.a.wang@intel.com>", "To": "xiaolong.ye@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, qiming.yang@intel.com, ying.a.wang@intel.com,\n\twei.zhao1@intel.com", "Date": "Thu, 17 Oct 2019 02:33:53 +0800", "Message-Id": "<20191016183356.350766-3-ying.a.wang@intel.com>", "X-Mailer": "git-send-email 2.15.1", "In-Reply-To": "<20191016183356.350766-1-ying.a.wang@intel.com>", "References": "<20191014034211.293048-2-ying.a.wang@intel.com>\n\t<20191016183356.350766-1-ying.a.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 2/5] net/ice: add devargs to control pipeline\n\tmode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Qiming Yang <qiming.yang@intel.com>\n\nAdded a devarg to control the mode in generic flow API.\nWe use none-pipeline mode by default.\n\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\nAcked-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n doc/guides/nics/ice.rst | 19 +++++++++++++++++++\n doc/guides/rel_notes/release_19_11.rst | 2 ++\n drivers/net/ice/ice_ethdev.c | 10 +++++++++-\n drivers/net/ice/ice_ethdev.h | 1 +\n 4 files changed, 31 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst\nindex 641f34840..933f63480 100644\n--- a/doc/guides/nics/ice.rst\n+++ b/doc/guides/nics/ice.rst\n@@ -61,6 +61,25 @@ Runtime Config Options\n NOTE: In Safe mode, only very limited features are available, features like RSS,\n checksum, fdir, tunneling ... are all disabled.\n \n+- ``Generic Flow Pipeline Mode Support`` (default ``0``)\n+\n+ In pipeline mode, a flow can be set at one specific stage by setting parameter\n+ ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with\n+ priority 0 located at the first pipeline stage which typically be used as a firewall\n+ to drop the packet on a blacklist(we called it permission stage). At this stage,\n+ flow rules are created for the device's exact match engine: switch. Flows with priority\n+ !0 located at the second stage, typically packets are classified here and be steered to\n+ specific queue or queue group (we called it distribution stage), At this stage, flow\n+ rules are created for device's flow director engine.\n+ For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director\n+ rule or a switch rule depends on its pattern/action and the resource allocation situation,\n+ all flows are virtually at the same pipeline stage.\n+ By default, generic flow API is enabled in none-pipeline mode, user can choose to\n+ use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``,\n+ for example::\n+\n+ -w 80:00.0,pipeline-mode-support=1\n+\n - ``Protocol extraction for per queue``\n \n Configure the RX queues to do protocol extraction into ``rte_mbuf::udata64``\ndiff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst\nindex 8634a7b81..34e149b92 100644\n--- a/doc/guides/rel_notes/release_19_11.rst\n+++ b/doc/guides/rel_notes/release_19_11.rst\n@@ -100,6 +100,8 @@ New Features\n * Added support for handling Receive Flex Descriptor.\n * Added support for protocol extraction on per Rx queue.\n * Added support for the ``RTE_ETH_DEV_CLOSE_REMOVE`` flag.\n+ * Generic filter enhancement\n+ - Supported pipeline mode.\n \n * **Updated the enic driver.**\n \ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 5567beb55..c6bfcdb74 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -19,10 +19,12 @@\n \n /* devargs */\n #define ICE_SAFE_MODE_SUPPORT_ARG \"safe-mode-support\"\n+#define ICE_PIPELINE_MODE_SUPPORT_ARG \"pipeline-mode-support\"\n #define ICE_PROTO_XTR_ARG \"proto_xtr\"\n \n static const char * const ice_valid_args[] = {\n \tICE_SAFE_MODE_SUPPORT_ARG,\n+\tICE_PIPELINE_MODE_SUPPORT_ARG,\n \tICE_PROTO_XTR_ARG,\n \tNULL\n };\n@@ -1833,6 +1835,11 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)\n \n \tret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,\n \t\t\t\t &parse_bool, &ad->devargs.safe_mode_support);\n+\tif (ret)\n+\t\tgoto bail;\n+\n+\tret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,\n+\t\t\t\t &parse_bool, &ad->devargs.pipe_mode_support);\n \n bail:\n \trte_kvargs_free(kvlist);\n@@ -4298,7 +4305,8 @@ RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);\n RTE_PMD_REGISTER_KMOD_DEP(net_ice, \"* igb_uio | uio_pci_generic | vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(net_ice,\n \t\t\t ICE_PROTO_XTR_ARG \"=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>\"\n-\t\t\t ICE_SAFE_MODE_SUPPORT_ARG \"=<0|1>\");\n+\t\t\t ICE_SAFE_MODE_SUPPORT_ARG \"=<0|1>\"\n+\t\t\t ICE_PIPELINE_MODE_SUPPORT_ARG \"=<0|1>\");\n \n RTE_INIT(ice_init_log)\n {\ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 2fd98817b..6790f64d4 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -289,6 +289,7 @@ struct ice_pf {\n struct ice_devargs {\n \tint safe_mode_support;\n \tuint8_t proto_xtr_dflt;\n+\tint pipe_mode_support;\n \tuint8_t proto_xtr[ICE_MAX_QUEUE_NUM];\n };\n \n", "prefixes": [ "v5", "2/5" ] }