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GET /api/patches/60583/?format=api
{ "id": 60583, "url": "https://patches.dpdk.org/api/patches/60583/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191006201409.8770-5-rmody@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191006201409.8770-5-rmody@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191006201409.8770-5-rmody@marvell.com", "date": "2019-10-06T20:14:04", "name": "[v2,4/9] net/qede/base: rename HSI datatypes and funcs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "daf38e8db86bf9d91284dbdd97bb1f0d03c4cfc5", "submitter": { "id": 1211, "url": "https://patches.dpdk.org/api/people/1211/?format=api", "name": "Rasesh Mody", "email": "rmody@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191006201409.8770-5-rmody@marvell.com/mbox/", "series": [ { "id": 6709, "url": "https://patches.dpdk.org/api/series/6709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6709", "date": "2019-10-06T20:14:04", "name": null, "version": 2, "mbox": "https://patches.dpdk.org/series/6709/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/60583/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/60583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8524D1D17B;\n\tSun, 6 Oct 2019 22:14:34 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 18B4F1D161\n\tfor <dev@dpdk.org>; Sun, 6 Oct 2019 22:14:28 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx96KENHp010574; Sun, 6 Oct 2019 13:14:28 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2verhrc80u-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 06 Oct 2019 13:14:27 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 6 Oct 2019 13:14:25 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 6 Oct 2019 13:14:25 -0700", "from irv1user08.caveonetworks.com (unknown [10.104.116.105])\n\tby maili.marvell.com (Postfix) with ESMTP id 937933F703F;\n\tSun, 6 Oct 2019 13:14:24 -0700 (PDT)", "(from rmody@localhost)\n\tby irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id\n\tx96KENAn008858; Sun, 6 Oct 2019 13:14:24 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type; s=pfpt0818;\n\tbh=uYDTpa2E7q4WAPhzwjWhHHkSvpFqCla8qw3MPulLp6Y=; \n\tb=NXMjdEFCjm8yepxx/Oj5zhm5pVRfsF5p4HRdlDb0AxZ/3iKT124T+qYbch3L0OOhEk28\n\tz1UYPol1fb8AqYq9C+nHHpwQBgEhhGa1tlLtd/ufVS7tOqn6+s/JveJ7SQNlZcxcWoh4\n\tcM6/LVwBz9eEpJVuinqCS8Mg+/wSkR3F0ZBEiwiQ7lRYAOheTKyGJAWHMxd3IRvaHeg4\n\tEGHdmlilenD/H6uCo3ra2tkYO8AY0WqcUv4Qio8OCidz4eO1FDQ0jlweMnomkZjaau22\n\tUliH4/fHiMDxgDZGqlifZFJuNA+/3BGqrPX4gLFCG/n0VwT2o2/TlR3WeCZAMP6WxPFh\n\tnQ== ", "X-Authentication-Warning": "irv1user08.caveonetworks.com: rmody set sender to\n\trmody@marvell.com using -f", "From": "Rasesh Mody <rmody@marvell.com>", "To": "<dev@dpdk.org>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>", "CC": "Rasesh Mody <rmody@marvell.com>, <GR-Everest-DPDK-Dev@marvell.com>", "Date": "Sun, 6 Oct 2019 13:14:04 -0700", "Message-ID": "<20191006201409.8770-5-rmody@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20190930024921.21818-1-rmody@marvell.com>", "References": "<20190930024921.21818-1-rmody@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-06_08:2019-10-03,2019-10-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 4/9] net/qede/base: rename HSI datatypes and\n\tfuncs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch changes code with E4/E5/e4/e5/BB_K2 prefixes and suffixes.\n - HSI datatypes renaming - removed all e5 datatypes and renamed\n all e4 datatypes to be prefix less/suffix less.\n (s/_E4//; s/_e4//; s/E4_//).\n - HSI functions - removed e4/e5 prefixes/suffixes.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n drivers/net/qede/base/common_hsi.h | 93 +-\n drivers/net/qede/base/ecore_cxt.c | 4 +-\n drivers/net/qede/base/ecore_dcbx.c | 2 +-\n drivers/net/qede/base/ecore_dev.c | 116 +-\n drivers/net/qede/base/ecore_hsi_common.h | 847 +++++-------\n drivers/net/qede/base/ecore_hsi_eth.h | 1308 ++++++++-----------\n drivers/net/qede/base/ecore_hsi_init_tool.h | 4 +-\n drivers/net/qede/base/ecore_init_fw_funcs.c | 42 +-\n drivers/net/qede/base/ecore_int.c | 8 +-\n drivers/net/qede/base/ecore_int.h | 4 +-\n drivers/net/qede/base/ecore_int_api.h | 6 +-\n drivers/net/qede/base/ecore_iov_api.h | 4 +-\n drivers/net/qede/base/ecore_mcp.c | 4 +-\n drivers/net/qede/base/ecore_spq.c | 8 +-\n drivers/net/qede/base/ecore_sriov.c | 4 +-\n drivers/net/qede/base/ecore_sriov.h | 4 +-\n drivers/net/qede/base/reg_addr.h | 65 +-\n drivers/net/qede/qede_rxtx.c | 8 +-\n 18 files changed, 1077 insertions(+), 1454 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h\nindex 7047eb9f8..b878a92aa 100644\n--- a/drivers/net/qede/base/common_hsi.h\n+++ b/drivers/net/qede/base/common_hsi.h\n@@ -106,59 +106,43 @@\n /* PCI functions */\n #define MAX_NUM_PORTS_BB (2)\n #define MAX_NUM_PORTS_K2 (4)\n-#define MAX_NUM_PORTS_E5 (4)\n-#define MAX_NUM_PORTS (MAX_NUM_PORTS_E5)\n+#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)\n \n #define MAX_NUM_PFS_BB (8)\n #define MAX_NUM_PFS_K2 (16)\n-#define MAX_NUM_PFS_E5 (16)\n-#define MAX_NUM_PFS (MAX_NUM_PFS_E5)\n+#define MAX_NUM_PFS (MAX_NUM_PFS_K2)\n #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */\n \n #define MAX_NUM_VFS_BB (120)\n #define MAX_NUM_VFS_K2 (192)\n-#define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2)\n-#define MAX_NUM_VFS_E5 (240)\n-#define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5)\n+#define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_K2)\n \n #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)\n #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)\n-#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4)\n \n /* in both BB and K2, the VF number starts from 16. so for arrays containing all\n * possible PFs and VFs - we need a constant for this size\n */\n #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)\n #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)\n-#define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4)\n-#define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5)\n-#define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5)\n+#define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_K2)\n \n #define MAX_NUM_VPORTS_K2 (208)\n #define MAX_NUM_VPORTS_BB (160)\n-#define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2)\n-#define MAX_NUM_VPORTS_E5 (256)\n-#define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5)\n+#define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)\n \n #define MAX_NUM_L2_QUEUES_BB\t(256)\n #define MAX_NUM_L2_QUEUES_K2 (320)\n-#define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */\n-#define MAX_NUM_L2_QUEUES\t\t(MAX_NUM_L2_QUEUES_E5)\n \n /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */\n #define NUM_PHYS_TCS_4PORT_K2 4\n-#define NUM_PHYS_TCS_4PORT_TX_E5 6\n-#define NUM_PHYS_TCS_4PORT_RX_E5 4\n #define NUM_OF_PHYS_TCS 8\n #define PURE_LB_TC NUM_OF_PHYS_TCS\n #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)\n-#define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1)\n-#define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1)\n #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)\n \n /* CIDs */\n-#define NUM_OF_CONNECTION_TYPES_E4 (8)\n-#define NUM_OF_CONNECTION_TYPES_E5 (16)\n+#define NUM_OF_CONNECTION_TYPES (8)\n #define NUM_OF_TASK_TYPES (8)\n #define NUM_OF_LCIDS (320)\n #define NUM_OF_LTIDS (320)\n@@ -412,9 +396,8 @@\n #define CAU_FSM_ETH_TX 1\n \n /* Number of Protocol Indices per Status Block */\n-#define PIS_PER_SB_E4 12\n-#define PIS_PER_SB_E5 8\n-#define MAX_PIS_PER_SB_E4\t OSAL_MAX_T(PIS_PER_SB_E4, PIS_PER_SB_E5)\n+#define PIS_PER_SB 12\n+#define MAX_PIS_PER_SB\t PIS_PER_SB\n \n /* fsm is stopped or not valid for this sb */\n #define CAU_HC_STOPPED_STATE\t\t3\n@@ -430,8 +413,7 @@\n \n #define MAX_SB_PER_PATH_K2\t\t\t(368)\n #define MAX_SB_PER_PATH_BB\t\t\t(288)\n-#define MAX_SB_PER_PATH_E5\t\t\t(512)\n-#define MAX_TOT_SB_PER_PATH\t\t\tMAX_SB_PER_PATH_E5\n+#define MAX_TOT_SB_PER_PATH\t\t\tMAX_SB_PER_PATH_K2\n \n #define MAX_SB_PER_PF_MIMD\t\t\t129\n #define MAX_SB_PER_PF_SIMD\t\t\t64\n@@ -639,12 +621,8 @@\n #define MAX_NUM_ILT_RECORDS \\\n \tOSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)\n \n-#define PXP_NUM_ILT_RECORDS_E5 13664\n-\n-\n // Host Interface\n-#define PXP_QUEUES_ZONE_MAX_NUM_E4\t320\n-#define PXP_QUEUES_ZONE_MAX_NUM_E5\t512\n+#define PXP_QUEUES_ZONE_MAX_NUM\t320\n \n \n /*****************/\n@@ -691,11 +669,12 @@\n /* PBF CONSTANTS */\n /******************/\n \n-/* Number of PBF command queue lines. Each line is 32B. */\n-#define PBF_MAX_CMD_LINES_E4 3328\n-#define PBF_MAX_CMD_LINES_E5 5280\n+/* Number of PBF command queue lines. */\n+#define PBF_MAX_CMD_LINES 3328 /* Each line is 256b */\n \n /* Number of BTB blocks. Each block is 256B. */\n+#define BTB_MAX_BLOCKS_BB 1440 /* 2880 blocks of 128B */\n+#define BTB_MAX_BLOCKS_K2 1840 /* 3680 blocks of 128B */\n #define BTB_MAX_BLOCKS 1440\n \n /*****************/\n@@ -1435,40 +1414,20 @@ enum rss_hash_type {\n /*\n * status block structure\n */\n-struct status_block_e4 {\n-\t__le16 pi_array[PIS_PER_SB_E4];\n-\t__le32 sb_num;\n-#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF\n-#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0\n-#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F\n-#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9\n-#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF\n-#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16\n-\t__le32 prod_index;\n-#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF\n-#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0\n-#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF\n-#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24\n-};\n-\n-\n-/*\n- * status block structure\n- */\n-struct status_block_e5 {\n-\t__le16 pi_array[PIS_PER_SB_E5];\n+struct status_block {\n+\t__le16 pi_array[PIS_PER_SB];\n \t__le32 sb_num;\n-#define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF\n-#define STATUS_BLOCK_E5_SB_NUM_SHIFT 0\n-#define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F\n-#define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9\n-#define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF\n-#define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16\n+#define STATUS_BLOCK_SB_NUM_MASK 0x1FF\n+#define STATUS_BLOCK_SB_NUM_SHIFT 0\n+#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F\n+#define STATUS_BLOCK_ZERO_PAD_SHIFT 9\n+#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF\n+#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16\n \t__le32 prod_index;\n-#define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF\n-#define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0\n-#define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF\n-#define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24\n+#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF\n+#define STATUS_BLOCK_PROD_INDEX_SHIFT 0\n+#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF\n+#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24\n };\n \n \ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex 5c3370e10..bc5628c4e 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -54,8 +54,8 @@\n \n /* connection context union */\n union conn_context {\n-\tstruct e4_core_conn_context core_ctx;\n-\tstruct e4_eth_conn_context eth_ctx;\n+\tstruct core_conn_context core_ctx;\n+\tstruct eth_conn_context eth_ctx;\n };\n \n /* TYPE-0 task context - iSCSI, FCOE */\ndiff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c\nindex cbc69cde7..b82ca49ff 100644\n--- a/drivers/net/qede/base/ecore_dcbx.c\n+++ b/drivers/net/qede/base/ecore_dcbx.c\n@@ -159,7 +159,7 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,\n \tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) &&\n \t (type == DCBX_PROTOCOL_ROCE)) {\n \t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);\n-\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP_BB_K2, prio << 1);\n+\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP, prio << 1);\n \t}\n }\n \ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex b183519b5..749aea4e8 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -935,7 +935,7 @@ enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,\n \treturn rc;\n }\n \n-struct ecore_llh_filter_e4_details {\n+struct ecore_llh_filter_details {\n \tu64 value;\n \tu32 mode;\n \tu32 protocol_type;\n@@ -944,10 +944,10 @@ struct ecore_llh_filter_e4_details {\n };\n \n static enum _ecore_status_t\n-ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,\n-\t\t\t struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,\n-\t\t\t struct ecore_llh_filter_e4_details *p_details,\n-\t\t\t bool b_write_access)\n+ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,\n+\t\t\tstruct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,\n+\t\t\tstruct ecore_llh_filter_details *p_details,\n+\t\t\tbool b_write_access)\n {\n \tu8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);\n \tstruct ecore_dmae_params params;\n@@ -1008,7 +1008,7 @@ ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t\t abs_ppfid, addr);\n \n \t/* Filter header select */\n-\taddr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 + filter_idx * 0x4;\n+\taddr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;\n \tif (b_write_access)\n \t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,\n \t\t\t p_details->hdr_sel);\n@@ -1035,7 +1035,7 @@ ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t\tu8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,\n \t\t\tu32 high, u32 low)\n {\n-\tstruct ecore_llh_filter_e4_details filter_details;\n+\tstruct ecore_llh_filter_details filter_details;\n \n \tfilter_details.enable = 1;\n \tfilter_details.value = ((u64)high << 32) | low;\n@@ -1048,22 +1048,22 @@ ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t\t 1 : /* protocol-based classification */\n \t\t\t 0; /* MAC-address based classification */\n \n-\treturn ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n-\t\t\t\t\t &filter_details,\n-\t\t\t\t\t true /* write access */);\n+\treturn ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t&filter_details,\n+\t\t\t\ttrue /* write access */);\n }\n \n static enum _ecore_status_t\n ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn,\n \t\t\t struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)\n {\n-\tstruct ecore_llh_filter_e4_details filter_details;\n+\tstruct ecore_llh_filter_details filter_details;\n \n \tOSAL_MEMSET(&filter_details, 0, sizeof(filter_details));\n \n-\treturn ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n-\t\t\t\t\t &filter_details,\n-\t\t\t\t\t true /* write access */);\n+\treturn ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t &filter_details,\n+\t\t\t\t true /* write access */);\n }\n \n static enum _ecore_status_t\n@@ -1468,7 +1468,7 @@ static enum _ecore_status_t\n ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t\tu8 ppfid)\n {\n-\tstruct ecore_llh_filter_e4_details filter_details;\n+\tstruct ecore_llh_filter_details filter_details;\n \tu8 abs_ppfid, filter_idx;\n \tu32 addr;\n \tenum _ecore_status_t rc;\n@@ -1486,9 +1486,9 @@ ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \tfor (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;\n \t filter_idx++) {\n \t\tOSAL_MEMSET(&filter_details, 0, sizeof(filter_details));\n-\t\trc = ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid,\n-\t\t\t\t\t\t filter_idx, &filter_details,\n-\t\t\t\t\t\t false /* read access */);\n+\t\trc = ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t filter_idx, &filter_details,\n+\t\t\t\t\t false /* read access */);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n \n@@ -1862,7 +1862,7 @@ static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)\n \n \t\tp_qm_port->active = 1;\n \t\tp_qm_port->active_phys_tcs = active_phys_tcs;\n-\t\tp_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;\n+\t\tp_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;\n \t\tp_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;\n \t}\n }\n@@ -2730,10 +2730,8 @@ static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,\n \n \tecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);\n \n-\tif (CHIP_REV_IS_EMUL(p_dev) &&\n-\t (ECORE_IS_AH(p_dev)))\n-\t\tecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,\n-\t\t\t 0x3ffffff);\n+\tif (ECORE_IS_AH(p_dev))\n+\t\tecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff);\n \n \t/* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */\n \t/* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */\n@@ -3017,49 +3015,59 @@ static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,\n \tecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);\n }\n \n-static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,\n+static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,\n \t\t\t\t struct ecore_ptt *p_ptt)\n {\n+\tu32 mac_base, mac_config_val = 0xa853;\n \tu8 port = p_hwfn->port_id;\n-\tu32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;\n \n-\tDP_INFO(p_hwfn->p_dev, \"Configurating Emulation Link %02x\\n\", port);\n-\n-\tecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),\n-\t\t (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |\n+\tecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),\n+\t\t (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT) |\n \t\t (port <<\n-\t\t CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |\n-\t\t (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));\n+\t\t CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT) |\n+\t\t (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT));\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,\n-\t\t 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);\n+\tmac_base = NWM_REG_MAC0_K2 + (port << 2) * NWM_REG_MAC0_SIZE;\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,\n-\t\t 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2,\n+\t\t 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT);\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,\n-\t\t 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2,\n+\t\t 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT);\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,\n-\t\t 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2,\n+\t\t 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT);\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2,\n+\t\t 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT);\n+\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2,\n \t\t (0xA <<\n-\t\t ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |\n+\t\t ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT) |\n \t\t (8 <<\n-\t\t ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));\n+\t\t ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT));\n \n-\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,\n-\t\t 0xa853);\n+\t/* Strip the CRC field from the frame */\n+\tmac_config_val &= ~ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2;\n+\tecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2,\n+\t\t mac_config_val);\n }\n \n static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,\n \t\t\t\t struct ecore_ptt *p_ptt)\n {\n-\tif (ECORE_IS_AH(p_hwfn->p_dev))\n-\t\tecore_emul_link_init_ah_e5(p_hwfn, p_ptt);\n-\telse /* BB */\n+\tu8 port = ECORE_IS_BB(p_hwfn->p_dev) ? p_hwfn->port_id * 2\n+\t\t\t\t\t : p_hwfn->port_id;\n+\n+\tDP_INFO(p_hwfn->p_dev, \"Emulation: Configuring Link [port %02x]\\n\",\n+\t\tport);\n+\n+\tif (ECORE_IS_BB(p_hwfn->p_dev))\n \t\tecore_emul_link_init_bb(p_hwfn, p_ptt);\n+\telse\n+\t\tecore_emul_link_init_ah(p_hwfn, p_ptt);\n+\n+\treturn;\n }\n \n static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,\n@@ -4190,13 +4198,13 @@ static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)\n \t/* clear indirect access */\n \tif (ECORE_IS_AH(p_hwfn->p_dev)) {\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);\n+\t\t\t PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);\n+\t\t\t PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);\n+\t\t\t PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);\n+\t\t\t PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);\n \t} else {\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n \t\t\t PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);\n@@ -5178,7 +5186,7 @@ static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,\n #endif\n \t\tfor (i = 0; i < MAX_NUM_PORTS_K2; i++) {\n \t\t\tport = ecore_rd(p_hwfn, p_ptt,\n-\t\t\t\t\tCNIG_REG_NIG_PORT0_CONF_K2_E5 +\n+\t\t\t\t\tCNIG_REG_NIG_PORT0_CONF_K2 +\n \t\t\t\t\t(i * 4));\n \t\t\tif (port & 1)\n \t\t\t\tp_dev->num_ports_in_engine++;\n@@ -5612,13 +5620,13 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,\n \tif (CHIP_REV_IS_FPGA(p_dev)) {\n \t\tDP_NOTICE(p_hwfn, false,\n \t\t\t \"FPGA: workaround; Prevent DMAE parities\\n\");\n-\t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,\n+\t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2,\n \t\t\t 7);\n \n \t\tDP_NOTICE(p_hwfn, false,\n \t\t\t \"FPGA: workaround: Set VF bar0 size\\n\");\n \t\tecore_wr(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);\n+\t\t\t PGLUE_B_REG_VF_BAR0_SIZE_K2, 4);\n \t}\n #endif\n \ndiff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h\nindex 2ce0ea9e5..7a94ed506 100644\n--- a/drivers/net/qede/base/ecore_hsi_common.h\n+++ b/drivers/net/qede/base/ecore_hsi_common.h\n@@ -73,306 +73,219 @@ struct xstorm_core_conn_st_ctx {\n \t__le32 reserved0[55] /* Pad to 15 cycles */;\n };\n \n-struct e4_xstorm_core_conn_ag_ctx {\n+struct xstorm_core_conn_ag_ctx {\n \tu8 reserved0 /* cdu_validation */;\n \tu8 core_state /* state */;\n \tu8 flags0;\n-/* exist_in_qm0 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n-/* exist_in_qm1 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1\n-/* exist_in_qm2 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2\n-/* exist_in_qm3 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n-/* bit4 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */\n+#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */\n+#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4\n /* cf_array_active */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5\n-/* bit6 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6\n-/* bit7 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7\n \tu8 flags1;\n-/* bit8 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0\n-/* bit9 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1\n-/* bit10 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2\n-/* bit11 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3\n-/* bit12 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4\n-/* bit13 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5\n-/* bit14 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n-/* bit15 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */\n+#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n \tu8 flags2;\n-/* timer0cf */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0\n-/* timer1cf */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2\n-/* timer2cf */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n+#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n+#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4\n /* timer_stop_all */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3\n+#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6\n \tu8 flags3;\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6\n \tu8 flags4;\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2\n-/* cf10 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4\n-/* cf11 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6\n \tu8 flags5;\n-/* cf12 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0\n-/* cf13 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2\n-/* cf14 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4\n-/* cf15 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6\n \tu8 flags6;\n-/* cf16 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0\n-/* cf_array_cf */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2\n-/* cf18 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4\n-/* cf19 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */\n+#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */\n+#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */\n+#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n \tu8 flags7;\n-/* cf20 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n-/* cf21 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2\n-/* cf22 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n-/* cf0en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6\n-/* cf1en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */\n+#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */\n+#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7\n \tu8 flags8;\n-/* cf2en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0\n-/* cf3en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1\n-/* cf4en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2\n-/* cf5en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3\n-/* cf6en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4\n-/* cf7en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5\n-/* cf8en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6\n-/* cf9en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7\n \tu8 flags9;\n-/* cf10en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0\n-/* cf11en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1\n-/* cf12en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2\n-/* cf13en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3\n-/* cf14en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4\n-/* cf15en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5\n-/* cf16en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */\n+#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6\n /* cf_array_cf_en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1\n+#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7\n \tu8 flags10;\n-/* cf18en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n-/* cf19en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n-/* cf20en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n-/* cf21en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3\n-/* cf22en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n-/* cf23en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5\n-/* rule0en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6\n-/* rule1en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */\n+#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */\n+#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */\n+#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */\n+#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */\n+#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7\n \tu8 flags11;\n-/* rule2en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0\n-/* rule3en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1\n-/* rule4en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n-/* rule5en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3\n-/* rule6en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4\n-/* rule7en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5\n-/* rule8en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n-/* rule9en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */\n+#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */\n+#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7\n \tu8 flags12;\n-/* rule10en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0\n-/* rule11en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1\n-/* rule12en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n-/* rule13en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n-/* rule14en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4\n-/* rule15en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5\n-/* rule16en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6\n-/* rule17en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7\n \tu8 flags13;\n-/* rule18en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0\n-/* rule19en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1\n-/* rule20en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n-/* rule21en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n-/* rule22en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n-/* rule23en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n-/* rule24en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n-/* rule25en */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n+#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */\n+#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */\n+#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n \tu8 flags14;\n-/* bit16 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0\n-/* bit17 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1\n-/* bit18 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2\n-/* bit19 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3\n-/* bit20 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4\n-/* bit21 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1\n-#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5\n-/* cf23 */\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3\n-#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6\n+#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0\n+#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1\n+#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2\n+#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3\n+#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4\n+#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */\n+#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5\n+#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */\n+#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6\n \tu8 byte2 /* byte2 */;\n \t__le16 physical_q0 /* physical_q0 */;\n \t__le16 consolid_prod /* physical_q1 */;\n@@ -426,89 +339,89 @@ struct e4_xstorm_core_conn_ag_ctx {\n \t__le16 word15 /* word15 */;\n };\n \n-struct e4_tstorm_core_conn_ag_ctx {\n+struct tstorm_core_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 byte1 /* state */;\n \tu8 flags0;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n+#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3\n+#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */\n+#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5\n+#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n+#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6\n \tu8 flags1;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n+#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n+#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6\n \tu8 flags2;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6\n \tu8 flags3;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7\n+#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n+#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5\n+#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7\n \tu8 flags4;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7\n+#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1\n+#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3\n+#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5\n+#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n+#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7\n \tu8 flags5;\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n-#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7\n+#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0\n+#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1\n+#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2\n+#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3\n+#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4\n+#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5\n+#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6\n+#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n+#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7\n \t__le32 reg0 /* reg0 */;\n \t__le32 reg1 /* reg1 */;\n \t__le32 reg2 /* reg2 */;\n@@ -530,63 +443,63 @@ struct e4_tstorm_core_conn_ag_ctx {\n \t__le32 reg10 /* reg10 */;\n };\n \n-struct e4_ustorm_core_conn_ag_ctx {\n+struct ustorm_core_conn_ag_ctx {\n \tu8 reserved /* cdu_validation */;\n \tu8 byte1 /* state */;\n \tu8 flags0;\n-#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n-#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6\n+#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n+#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n+#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n+#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n+#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n+#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2\n+#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n+#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4\n+#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6\n \tu8 flags1;\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6\n+#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n+#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0\n+#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2\n+#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4\n+#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6\n \tu8 flags2;\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7\n+#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0\n+#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1\n+#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2\n+#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3\n+#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4\n+#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5\n+#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6\n+#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7\n \tu8 flags3;\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n-#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7\n+#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0\n+#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1\n+#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2\n+#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3\n+#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4\n+#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5\n+#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6\n+#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n+#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7\n \tu8 byte2 /* byte2 */;\n \tu8 byte3 /* byte3 */;\n \t__le16 word0 /* conn_dpi */;\n@@ -616,7 +529,7 @@ struct ustorm_core_conn_st_ctx {\n /*\n * core connection context\n */\n-struct e4_core_conn_context {\n+struct core_conn_context {\n /* ystorm storm context */\n \tstruct ystorm_core_conn_st_ctx ystorm_st_context;\n \tstruct regpair ystorm_st_padding[2] /* padding */;\n@@ -626,11 +539,11 @@ struct e4_core_conn_context {\n /* xstorm storm context */\n \tstruct xstorm_core_conn_st_ctx xstorm_st_context;\n /* xstorm aggregative context */\n-\tstruct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;\n+\tstruct xstorm_core_conn_ag_ctx xstorm_ag_context;\n /* tstorm aggregative context */\n-\tstruct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;\n+\tstruct tstorm_core_conn_ag_ctx tstorm_ag_context;\n /* ustorm aggregative context */\n-\tstruct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;\n+\tstruct ustorm_core_conn_ag_ctx ustorm_ag_context;\n /* mstorm storm context */\n \tstruct mstorm_core_conn_st_ctx mstorm_st_context;\n /* ustorm storm context */\n@@ -2104,90 +2017,6 @@ enum dmae_cmd_src_enum {\n };\n \n \n-struct e4_mstorm_core_conn_ag_ctx {\n-\tu8 byte0 /* cdu_validation */;\n-\tu8 byte1 /* state */;\n-\tu8 flags0;\n-#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n-#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6\n-\tu8 flags1;\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7\n-\t__le16 word0 /* word0 */;\n-\t__le16 word1 /* word1 */;\n-\t__le32 reg0 /* reg0 */;\n-\t__le32 reg1 /* reg1 */;\n-};\n-\n-\n-\n-\n-\n-struct e4_ystorm_core_conn_ag_ctx {\n-\tu8 byte0 /* cdu_validation */;\n-\tu8 byte1 /* state */;\n-\tu8 flags0;\n-#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0\n-#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6\n-\tu8 flags1;\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7\n-\tu8 byte2 /* byte2 */;\n-\tu8 byte3 /* byte3 */;\n-\t__le16 word0 /* word0 */;\n-\t__le32 reg0 /* reg0 */;\n-\t__le32 reg1 /* reg1 */;\n-\t__le16 word1 /* word1 */;\n-\t__le16 word2 /* word2 */;\n-\t__le16 word3 /* word3 */;\n-\t__le16 word4 /* word4 */;\n-\t__le32 reg2 /* reg2 */;\n-\t__le32 reg3 /* reg3 */;\n-};\n \n \n struct fw_asserts_ram_section {\n@@ -2416,23 +2245,23 @@ struct qm_rf_opportunistic_mask {\n /*\n * QM hardware structure of QM map memory\n */\n-struct qm_rf_pq_map_e4 {\n+struct qm_rf_pq_map {\n \t__le32 reg;\n-#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */\n-#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0\n-#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */\n-#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1\n+#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */\n+#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0\n+#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */\n+#define QM_RF_PQ_MAP_RL_ID_SHIFT 1\n /* the first PQ associated with the VPORT and VOQ of this PQ */\n-#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF\n-#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9\n-#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */\n-#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18\n-#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */\n-#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23\n-#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */\n-#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25\n-#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F\n-#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26\n+#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF\n+#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9\n+#define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */\n+#define QM_RF_PQ_MAP_VOQ_SHIFT 18\n+#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */\n+#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23\n+#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */\n+#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25\n+#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F\n+#define QM_RF_PQ_MAP_RESERVED_SHIFT 26\n };\n \n \ndiff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h\nindex 7bc094792..b1cab2910 100644\n--- a/drivers/net/qede/base/ecore_hsi_eth.h\n+++ b/drivers/net/qede/base/ecore_hsi_eth.h\n@@ -32,312 +32,224 @@ struct xstorm_eth_conn_st_ctx {\n \t__le32 reserved[60];\n };\n \n-struct e4_xstorm_eth_conn_ag_ctx {\n+struct xstorm_eth_conn_ag_ctx {\n \tu8 reserved0 /* cdu_validation */;\n \tu8 eth_state /* state */;\n \tu8 flags0;\n /* exist_in_qm0 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n /* exist_in_qm1 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1\n /* exist_in_qm2 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2\n /* exist_in_qm3 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n-/* bit4 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4\n /* cf_array_active */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5\n-/* bit6 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6\n-/* bit7 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7\n \tu8 flags1;\n-/* bit8 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0\n-/* bit9 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1\n-/* bit10 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2\n-/* bit11 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3\n-/* bit12 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4\n-/* bit13 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5\n-/* bit14 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n-/* bit15 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */\n+#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */\n+#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */\n+#define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */\n+#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n \tu8 flags2;\n-/* timer0cf */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0\n-/* timer1cf */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2\n-/* timer2cf */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n+#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n+#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4\n /* timer_stop_all */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3\n+#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6\n \tu8 flags3;\n-/* cf4 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0\n-/* cf5 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2\n-/* cf6 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4\n-/* cf7 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6\n \tu8 flags4;\n-/* cf8 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0\n-/* cf9 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2\n-/* cf10 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4\n-/* cf11 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6\n \tu8 flags5;\n-/* cf12 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0\n-/* cf13 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2\n-/* cf14 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4\n-/* cf15 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */\n+#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6\n \tu8 flags6;\n-/* cf16 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */\n+#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0\n /* cf_array_cf */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2\n-/* cf18 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4\n-/* cf19 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3\n+#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */\n+#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n \tu8 flags7;\n-/* cf20 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n-/* cf21 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2\n-/* cf22 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n-/* cf0en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6\n-/* cf1en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */\n+#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */\n+#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7\n \tu8 flags8;\n-/* cf2en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0\n-/* cf3en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1\n-/* cf4en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2\n-/* cf5en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3\n-/* cf6en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4\n-/* cf7en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5\n-/* cf8en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6\n-/* cf9en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7\n \tu8 flags9;\n-/* cf10en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0\n-/* cf11en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1\n-/* cf12en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2\n-/* cf13en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3\n-/* cf14en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4\n-/* cf15en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5\n-/* cf16en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */\n+#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */\n+#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6\n /* cf_array_cf_en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1\n+#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7\n \tu8 flags10;\n-/* cf18en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n-/* cf19en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n-/* cf20en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n-/* cf21en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3\n-/* cf22en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n-/* cf23en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5\n-/* rule0en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6\n-/* rule1en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */\n+#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */\n+#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */\n+#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */\n+#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */\n+#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7\n \tu8 flags11;\n-/* rule2en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0\n-/* rule3en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1\n-/* rule4en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n-/* rule5en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3\n-/* rule6en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4\n-/* rule7en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5\n-/* rule8en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n-/* rule9en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */\n+#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */\n+#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7\n \tu8 flags12;\n-/* rule10en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0\n-/* rule11en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1\n-/* rule12en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n-/* rule13en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n-/* rule14en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4\n-/* rule15en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5\n-/* rule16en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6\n-/* rule17en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7\n \tu8 flags13;\n-/* rule18en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0\n-/* rule19en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1\n-/* rule20en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n-/* rule21en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n-/* rule22en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n-/* rule23en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n-/* rule24en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n-/* rule25en */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n+#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */\n+#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */\n+#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n \tu8 flags14;\n-/* bit16 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0\n-/* bit17 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1\n-/* bit18 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2\n-/* bit19 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3\n-/* bit20 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4\n-/* bit21 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1\n-#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5\n-/* cf23 */\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3\n-#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */\n+#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3\n+#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */\n+#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4\n+#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */\n+#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5\n+#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */\n+#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6\n \tu8 edpm_event_id /* byte2 */;\n \t__le16 physical_q0 /* physical_q0 */;\n \t__le16 e5_reserved1 /* physical_q1 */;\n@@ -398,47 +310,37 @@ struct ystorm_eth_conn_st_ctx {\n \t__le32 reserved[8];\n };\n \n-struct e4_ystorm_eth_conn_ag_ctx {\n+struct ystorm_eth_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 state /* state */;\n \tu8 flags0;\n-/* exist_in_qm0 */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n-/* exist_in_qm1 */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2\n-#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4\n-#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n+#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n+#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n+#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n+#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n+#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */\n+#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2\n+#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */\n+#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4\n+#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n+#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n \tu8 flags1;\n-/* cf0en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0\n-/* cf1en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1\n-/* cf2en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n-/* rule0en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3\n-/* rule1en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4\n-/* rule2en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5\n-/* rule3en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6\n-/* rule4en */\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1\n-#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7\n+#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */\n+#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0\n+#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */\n+#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1\n+#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n+#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3\n+#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4\n+#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5\n+#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6\n+#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7\n \tu8 tx_q0_int_coallecing_timeset /* byte2 */;\n \tu8 byte3 /* byte3 */;\n \t__le16 word0 /* word0 */;\n@@ -452,89 +354,89 @@ struct e4_ystorm_eth_conn_ag_ctx {\n \t__le32 reg3 /* reg3 */;\n };\n \n-struct e4_tstorm_eth_conn_ag_ctx {\n+struct tstorm_eth_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 byte1 /* state */;\n \tu8 flags0;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n+#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3\n+#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */\n+#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5\n+#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */\n+#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6\n \tu8 flags1;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */\n+#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */\n+#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6\n \tu8 flags2;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6\n \tu8 flags3;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7\n+#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n+#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5\n+#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7\n \tu8 flags4;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7\n+#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1\n+#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3\n+#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5\n+#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n+#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7\n \tu8 flags5;\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n-#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7\n+#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0\n+#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1\n+#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2\n+#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3\n+#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4\n+#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */\n+#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5\n+#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6\n+#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n+#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7\n \t__le32 reg0 /* reg0 */;\n \t__le32 reg1 /* reg1 */;\n \t__le32 reg2 /* reg2 */;\n@@ -556,88 +458,66 @@ struct e4_tstorm_eth_conn_ag_ctx {\n \t__le32 reg10 /* reg10 */;\n };\n \n-struct e4_ustorm_eth_conn_ag_ctx {\n+struct ustorm_eth_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 byte1 /* state */;\n \tu8 flags0;\n /* exist_in_qm0 */\n-#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n+#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1\n+#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0\n /* exist_in_qm1 */\n-#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n-/* timer0cf */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2\n-/* timer1cf */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4\n-/* timer2cf */\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n+#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1\n+#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n+#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */\n+#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2\n+#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */\n+#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4\n+#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */\n+#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n \tu8 flags1;\n /* timer_stop_all */\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0\n-/* cf4 */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2\n-/* cf5 */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4\n-/* cf6 */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6\n+#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3\n+#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0\n+#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */\n+#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2\n+#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */\n+#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4\n+#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */\n+#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6\n \tu8 flags2;\n-/* cf0en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0\n-/* cf1en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1\n-/* cf2en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n-/* cf3en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3\n-/* cf4en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4\n-/* cf5en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5\n-/* cf6en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6\n-/* rule0en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7\n+#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */\n+#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0\n+#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */\n+#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1\n+#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n+#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3\n+#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */\n+#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4\n+#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */\n+#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5\n+#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */\n+#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6\n+#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7\n \tu8 flags3;\n-/* rule1en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0\n-/* rule2en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1\n-/* rule3en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2\n-/* rule4en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3\n-/* rule5en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4\n-/* rule6en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5\n-/* rule7en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6\n-/* rule8en */\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1\n-#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7\n+#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0\n+#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1\n+#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2\n+#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3\n+#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4\n+#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5\n+#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6\n+#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */\n+#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7\n \tu8 byte2 /* byte2 */;\n \tu8 byte3 /* byte3 */;\n \t__le16 word0 /* conn_dpi */;\n@@ -667,7 +547,7 @@ struct mstorm_eth_conn_st_ctx {\n /*\n * eth connection context\n */\n-struct e4_eth_conn_context {\n+struct eth_conn_context {\n /* tstorm storm context */\n \tstruct tstorm_eth_conn_st_ctx tstorm_st_context;\n \tstruct regpair tstorm_st_padding[2] /* padding */;\n@@ -676,15 +556,15 @@ struct e4_eth_conn_context {\n /* xstorm storm context */\n \tstruct xstorm_eth_conn_st_ctx xstorm_st_context;\n /* xstorm aggregative context */\n-\tstruct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;\n+\tstruct xstorm_eth_conn_ag_ctx xstorm_ag_context;\n /* ystorm storm context */\n \tstruct ystorm_eth_conn_st_ctx ystorm_st_context;\n /* ystorm aggregative context */\n-\tstruct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;\n+\tstruct ystorm_eth_conn_ag_ctx ystorm_ag_context;\n /* tstorm aggregative context */\n-\tstruct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;\n+\tstruct tstorm_eth_conn_ag_ctx tstorm_ag_context;\n /* ustorm aggregative context */\n-\tstruct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;\n+\tstruct ustorm_eth_conn_ag_ctx ustorm_ag_context;\n /* ustorm storm context */\n \tstruct ustorm_eth_conn_st_ctx ustorm_st_context;\n /* mstorm storm context */\n@@ -1875,37 +1755,37 @@ struct E4XstormEthConnAgCtxDqExtLdPart {\n };\n \n \n-struct e4_mstorm_eth_conn_ag_ctx {\n+struct mstorm_eth_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 byte1 /* state */;\n \tu8 flags0;\n-#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n-#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n+#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */\n+#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n+#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */\n+#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1\n+#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */\n+#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2\n+#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */\n+#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4\n+#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */\n+#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6\n \tu8 flags1;\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n-#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7\n+#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0\n+#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1\n+#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2\n+#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */\n+#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3\n+#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */\n+#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4\n+#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */\n+#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5\n+#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */\n+#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6\n+#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */\n+#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7\n \t__le16 word0 /* word0 */;\n \t__le16 word1 /* word1 */;\n \t__le32 reg0 /* reg0 */;\n@@ -1916,289 +1796,243 @@ struct e4_mstorm_eth_conn_ag_ctx {\n \n \n \n-struct e4_xstorm_eth_hw_conn_ag_ctx {\n+struct xstorm_eth_hw_conn_ag_ctx {\n \tu8 reserved0 /* cdu_validation */;\n \tu8 eth_state /* state */;\n \tu8 flags0;\n /* exist_in_qm0 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0\n /* exist_in_qm1 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1\n /* exist_in_qm2 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2\n /* exist_in_qm3 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n-/* bit4 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4\n /* cf_array_active */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7\n \tu8 flags1;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1\n-/* bit10 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2\n-/* bit11 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3\n-/* bit12 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4\n-/* bit13 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5\n-/* bit14 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n-/* bit15 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7\n \tu8 flags2;\n /* timer0cf */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0\n /* timer1cf */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2\n /* timer2cf */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4\n /* timer_stop_all */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6\n \tu8 flags3;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6\n \tu8 flags4;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6\n \tu8 flags5;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6\n \tu8 flags6;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0\n /* cf_array_cf */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6\n \tu8 flags7;\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n-/* cf0en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6\n-/* cf1en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7\n \tu8 flags8;\n-/* cf2en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0\n-/* cf3en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1\n-/* cf4en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2\n-/* cf5en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3\n-/* cf6en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4\n-/* cf7en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5\n-/* cf8en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6\n-/* cf9en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7\n \tu8 flags9;\n-/* cf10en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0\n-/* cf11en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1\n-/* cf12en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2\n-/* cf13en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3\n-/* cf14en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4\n-/* cf15en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5\n-/* cf16en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6\n /* cf_array_cf_en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7\n \tu8 flags10;\n-/* cf18en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n-/* cf19en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n-/* cf20en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n-/* cf21en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3\n-/* cf22en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n-/* cf23en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5\n-/* rule0en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6\n-/* rule1en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7\n \tu8 flags11;\n-/* rule2en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0\n-/* rule3en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1\n-/* rule4en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n-/* rule5en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3\n-/* rule6en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4\n-/* rule7en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5\n-/* rule8en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n-/* rule9en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7\n \tu8 flags12;\n /* rule10en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0\n /* rule11en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1\n /* rule12en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2\n /* rule13en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3\n /* rule14en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4\n /* rule15en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5\n /* rule16en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6\n /* rule17en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7\n \tu8 flags13;\n /* rule18en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0\n /* rule19en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1\n /* rule20en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2\n /* rule21en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3\n /* rule22en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4\n /* rule23en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5\n /* rule24en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6\n /* rule25en */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7\n \tu8 flags14;\n-/* bit16 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0\n-/* bit17 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1\n-/* bit18 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2\n-/* bit19 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3\n-/* bit20 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4\n-/* bit21 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */\n-#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3\n+#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4\n+#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */\n+#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6\n \tu8 edpm_event_id /* byte2 */;\n \t__le16 physical_q0 /* physical_q0 */;\n \t__le16 e5_reserved1 /* physical_q1 */;\ndiff --git a/drivers/net/qede/base/ecore_hsi_init_tool.h b/drivers/net/qede/base/ecore_hsi_init_tool.h\nindex 0e157f9bc..1fe4bfc61 100644\n--- a/drivers/net/qede/base/ecore_hsi_init_tool.h\n+++ b/drivers/net/qede/base/ecore_hsi_init_tool.h\n@@ -23,7 +23,6 @@\n enum chip_ids {\n \tCHIP_BB,\n \tCHIP_K2,\n-\tCHIP_E5,\n \tMAX_CHIP_IDS\n };\n \n@@ -134,7 +133,8 @@ enum init_modes {\n \tMODE_PORTS_PER_ENG_2,\n \tMODE_PORTS_PER_ENG_4,\n \tMODE_100G,\n-\tMODE_E5,\n+\tMODE_SKIP_PRAM_INIT,\n+\tMODE_EMUL_MAC,\n \tMAX_INIT_MODES\n };\n \ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c\nindex cfc1156eb..928d41b46 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.c\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.c\n@@ -18,12 +18,12 @@\n \n #define CDU_VALIDATION_DEFAULT_CFG 61\n \n-static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {\n+static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = {\n \t{ 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */\n \t{ 528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */\n \t{ 608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */\n };\n-static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {\n+static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = {\n \t{ 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */\n };\n \n@@ -160,19 +160,18 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {\n #define QM_CMD_SET_FIELD(var, cmd, field, value) \\\n \tSET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)\n \n-#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, \\\n-\t\t\t vp_pq_id, rl_id, ext_voq, wrr) \\\n-\tdo {\t\t\t\t\t\t\\\n-\t\tOSAL_MEMSET(&map, 0, sizeof(map)); \\\n-\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); \\\n-\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_VALID, rl_valid); \\\n-\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, vp_pq_id); \\\n-\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_ID, rl_id); \\\n-\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VOQ, ext_voq); \\\n-\t\tSET_FIELD(map.reg, \\\n-\t\t\t QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, wrr); \\\n-\t\tSTORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, \\\n-\t\t\t *((u32 *)&map)); \\\n+#define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, \\\n+\t\t\t rl_valid, rl_id, voq, wrr) \\\n+\tdo { \\\n+\t\tOSAL_MEMSET(&(map), 0, sizeof(map)); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_PQ_VALID, 1); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_RL_ID, rl_id); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_VP_PQ_ID, vp_pq_id); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_VOQ, voq); \\\n+\t\tSET_FIELD(map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, wrr); \\\n+\t\tSTORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \\\n+\t\t\t *((u32 *)&(map))); \\\n \t} while (0)\n \n #define WRITE_PQ_INFO_TO_RAM\t\t1\n@@ -497,12 +496,11 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t}\n \n \t\t/* Prepare PQ map entry */\n-\t\tstruct qm_rf_pq_map_e4 tx_pq_map;\n+\t\tstruct qm_rf_pq_map tx_pq_map;\n \n-\t\tQM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, E4, pq_id, rl_valid ?\n-\t\t\t\t 1 : 0,\n-\t\t\t\t first_tx_pq_id, rl_valid ?\n-\t\t\t\t pq_params[i].vport_id : 0,\n+\t\tQM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, pq_id, first_tx_pq_id,\n+\t\t\t\t rl_valid ? 1 : 0,\n+\t\t\t\t rl_valid ? pq_params[i].vport_id : 0,\n \t\t\t\t ext_voq, pq_params[i].wrr_group);\n \n \t\t/* Set PQ base address */\n@@ -1577,9 +1575,9 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,\n \t\treturn;\n \n \t/* Update DORQ registers */\n-\tecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,\n+\tecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2,\n \t\t eth_geneve_enable ? 1 : 0);\n-\tecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,\n+\tecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2,\n \t\t ip_geneve_enable ? 1 : 0);\n }\n \ndiff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c\nindex 7368d55f7..c8536380c 100644\n--- a/drivers/net/qede/base/ecore_int.c\n+++ b/drivers/net/qede/base/ecore_int.c\n@@ -29,7 +29,7 @@ struct ecore_pi_info {\n struct ecore_sb_sp_info {\n \tstruct ecore_sb_info sb_info;\n \t/* per protocol index data */\n-\tstruct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];\n+\tstruct ecore_pi_info pi_info_arr[MAX_PIS_PER_SB];\n };\n \n enum ecore_attention_type {\n@@ -1514,7 +1514,7 @@ static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,\n \tif (IS_VF(p_hwfn->p_dev))\n \t\treturn;/* @@@TBD MichalK- VF CAU... */\n \n-\tsb_offset = igu_sb_id * PIS_PER_SB_E4;\n+\tsb_offset = igu_sb_id * MAX_PIS_PER_SB;\n \tOSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));\n \n \tSET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);\n@@ -2692,10 +2692,10 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,\n \tp_info->igu_cons = ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t IGU_REG_CONSUMER_MEM + sbid * 4);\n \n-\tfor (i = 0; i < PIS_PER_SB_E4; i++)\n+\tfor (i = 0; i < MAX_PIS_PER_SB; i++)\n \t\tp_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,\n \t\t\t\t\t CAU_REG_PI_MEMORY +\n-\t\t\t\t\t sbid * 4 * PIS_PER_SB_E4 +\n+\t\t\t\t\t sbid * 4 * MAX_PIS_PER_SB +\n \t\t\t\t\t i * 4);\n \n \treturn ECORE_SUCCESS;\ndiff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h\nindex ff2310cff..5042cd1d1 100644\n--- a/drivers/net/qede/base/ecore_int.h\n+++ b/drivers/net/qede/base/ecore_int.h\n@@ -16,8 +16,8 @@\n #define ECORE_SB_ATT_IDX\t0x0001\n #define ECORE_SB_EVENT_MASK\t0x0003\n \n-#define SB_ALIGNED_SIZE(p_hwfn)\t\t\t\t\t\\\n-\tALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)\n+#define SB_ALIGNED_SIZE(p_hwfn) \\\n+\tALIGNED_TYPE_SIZE(struct status_block, p_hwfn)\n \n #define ECORE_SB_INVALID_IDX\t0xffff\n \ndiff --git a/drivers/net/qede/base/ecore_int_api.h b/drivers/net/qede/base/ecore_int_api.h\nindex 42538a46c..abea2a716 100644\n--- a/drivers/net/qede/base/ecore_int_api.h\n+++ b/drivers/net/qede/base/ecore_int_api.h\n@@ -24,7 +24,7 @@ enum ecore_int_mode {\n #endif\n \n struct ecore_sb_info {\n-\tstruct status_block_e4 *sb_virt;\n+\tstruct status_block *sb_virt;\n \tdma_addr_t sb_phys;\n \tu32 sb_ack;\t\t/* Last given ack */\n \tu16 igu_sb_id;\n@@ -42,7 +42,7 @@ struct ecore_sb_info {\n struct ecore_sb_info_dbg {\n \tu32 igu_prod;\n \tu32 igu_cons;\n-\tu16 pi[PIS_PER_SB_E4];\n+\tu16 pi[MAX_PIS_PER_SB];\n };\n \n struct ecore_sb_cnt_info {\n@@ -65,7 +65,7 @@ static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)\n \t/* barrier(); status block is written to by the chip */\n \t/* FIXME: need some sort of barrier. */\n \tprod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &\n-\t STATUS_BLOCK_E4_PROD_INDEX_MASK;\n+\t STATUS_BLOCK_PROD_INDEX_MASK;\n \tif (sb_info->sb_ack != prod) {\n \t\tsb_info->sb_ack = prod;\n \t\trc |= ECORE_SB_IDX;\ndiff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h\nindex 55de7086d..c998dbf8d 100644\n--- a/drivers/net/qede/base/ecore_iov_api.h\n+++ b/drivers/net/qede/base/ecore_iov_api.h\n@@ -740,7 +740,7 @@ ecore_iov_pf_configure_vf_queue_coalesce(struct ecore_hwfn *p_hwfn,\n * @param p_hwfn\n * @param rel_vf_id\n *\n- * @return MAX_NUM_VFS_E4 in case no further active VFs, otherwise index.\n+ * @return MAX_NUM_VFS_K2 in case no further active VFs, otherwise index.\n */\n u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id);\n \n@@ -764,7 +764,7 @@ void ecore_iov_set_vf_hw_channel(struct ecore_hwfn *p_hwfn, int vfid,\n \n #define ecore_for_each_vf(_p_hwfn, _i)\t\t\t\t\t\\\n \tfor (_i = ecore_iov_get_next_active_vf(_p_hwfn, 0);\t\t\\\n-\t _i < MAX_NUM_VFS_E4;\t\t\t\t\t\\\n+\t _i < MAX_NUM_VFS_K2;\t\t\t\t\t\\\n \t _i = ecore_iov_get_next_active_vf(_p_hwfn, _i + 1))\n \n #endif\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 1a5152ec5..23336c282 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -1703,7 +1703,7 @@ static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,\n \n \t\t\t/* Configure DB to add external vlan to EDPM packets */\n \t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);\n-\t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,\n+\t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID,\n \t\t\t\t p_hwfn->hw_info.ovlan);\n \t\t} else {\n \t\t\tecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);\n@@ -1711,7 +1711,7 @@ static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,\n \n \t\t\t/* Configure DB to add external vlan to EDPM packets */\n \t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);\n-\t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);\n+\t\t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID, 0);\n \t\t}\n \n \t\tecore_sp_pf_update_stag(p_hwfn);\ndiff --git a/drivers/net/qede/base/ecore_spq.c b/drivers/net/qede/base/ecore_spq.c\nindex 88ad961e7..486b21dd9 100644\n--- a/drivers/net/qede/base/ecore_spq.c\n+++ b/drivers/net/qede/base/ecore_spq.c\n@@ -188,7 +188,7 @@ ecore_spq_fill_entry(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry *p_ent)\n static void ecore_spq_hw_initialize(struct ecore_hwfn *p_hwfn,\n \t\t\t\t struct ecore_spq *p_spq)\n {\n-\tstruct e4_core_conn_context *p_cxt;\n+\tstruct core_conn_context *p_cxt;\n \tstruct ecore_cxt_info cxt_info;\n \tu16 physical_q;\n \tenum _ecore_status_t rc;\n@@ -210,14 +210,14 @@ static void ecore_spq_hw_initialize(struct ecore_hwfn *p_hwfn,\n \n \tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) {\n \t\tSET_FIELD(p_cxt->xstorm_ag_context.flags10,\n-\t\t\t E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);\n+\t\t\t XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);\n \t\tSET_FIELD(p_cxt->xstorm_ag_context.flags1,\n-\t\t\t E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);\n+\t\t\t XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);\n \t\t/* SET_FIELD(p_cxt->xstorm_ag_context.flags10,\n \t\t *\t E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN, 1);\n \t\t */\n \t\tSET_FIELD(p_cxt->xstorm_ag_context.flags9,\n-\t\t\t E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);\n+\t\t\t XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);\n \t}\n \n \t/* CDU validation - FIXME currently disabled */\ndiff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c\nindex 7d73ef9fb..d771ac6d4 100644\n--- a/drivers/net/qede/base/ecore_sriov.c\n+++ b/drivers/net/qede/base/ecore_sriov.c\n@@ -1787,7 +1787,7 @@ static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn,\n \t/* fill in pfdev info */\n \tpfdev_info->chip_num = p_hwfn->p_dev->chip_num;\n \tpfdev_info->db_size = 0;\t/* @@@ TBD MichalK Vf Doorbells */\n-\tpfdev_info->indices_per_sb = PIS_PER_SB_E4;\n+\tpfdev_info->indices_per_sb = MAX_PIS_PER_SB;\n \n \tpfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |\n \t\t\t\t PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;\n@@ -4383,7 +4383,7 @@ u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id)\n \t\t\treturn i;\n \n out:\n-\treturn MAX_NUM_VFS_E4;\n+\treturn MAX_NUM_VFS_K2;\n }\n \n enum _ecore_status_t ecore_iov_copy_vf_msg(struct ecore_hwfn *p_hwfn,\ndiff --git a/drivers/net/qede/base/ecore_sriov.h b/drivers/net/qede/base/ecore_sriov.h\nindex 50c7d2c93..e748e67d7 100644\n--- a/drivers/net/qede/base/ecore_sriov.h\n+++ b/drivers/net/qede/base/ecore_sriov.h\n@@ -14,7 +14,7 @@\n #include \"ecore_l2.h\"\n \n #define ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS \\\n-\t(MAX_NUM_VFS_E4 * ECORE_ETH_VF_NUM_VLAN_FILTERS)\n+\t(MAX_NUM_VFS_K2 * ECORE_ETH_VF_NUM_VLAN_FILTERS)\n \n /* Represents a full message. Both the request filled by VF\n * and the response filled by the PF. The VF needs one copy\n@@ -173,7 +173,7 @@ struct ecore_vf_info {\n * capability enabled.\n */\n struct ecore_pf_iov {\n-\tstruct ecore_vf_info\tvfs_array[MAX_NUM_VFS_E4];\n+\tstruct ecore_vf_info\tvfs_array[MAX_NUM_VFS_K2];\n \tu64\t\t\tpending_flr[ECORE_VF_ARRAY_LENGTH];\n \n #ifndef REMOVE_DBG\ndiff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h\nindex be59f7738..9277b46fa 100644\n--- a/drivers/net/qede/base/reg_addr.h\n+++ b/drivers/net/qede/base/reg_addr.h\n@@ -134,7 +134,7 @@\n \t0x009060UL\n #define MISCS_REG_CLK_100G_MODE\t\\\n \t0x009070UL\n-#define MISCS_REG_RESET_PL_HV_2 \\\n+#define MISCS_REG_RESET_PL_HV_2_K2 \\\n \t0x009150UL\n #define MSDM_REG_ENABLE_IN1 \\\n \t0xfc0004UL\n@@ -1109,7 +1109,7 @@\n #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL\n #define MISCS_REG_FUNCTION_HIDE 0x0096f0UL\n #define PCIE_REG_PRTY_MASK 0x0547b4UL\n-#define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL\n+#define PGLUE_B_REG_VF_BAR0_SIZE_K2 0x2aaeb4UL\n #define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL\n #define SEM_FAST_REG_INT_RAM_SIZE 20480\n #define MCP_REG_SCRATCH_SIZE 57344\n@@ -1136,12 +1136,12 @@\n #define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL\n #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL\n #define PRS_REG_SEARCH_FCOE 0x1f0408UL\n-#define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL\n+#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL\n #define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL\n-#define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL\n-#define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL\n+#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL\n+#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL\n #define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL\n-#define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL\n+#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL\n #define IGU_REG_WRITE_DONE_PENDING 0x180900UL\n #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL\n #define PRS_REG_MSG_INFO 0x1f0a1cUL\n@@ -1157,30 +1157,30 @@\n #define CDU_REG_CCFC_CTX_VALID1 0x580404UL\n #define CDU_REG_TCFC_CTX_VALID0 0x580408UL\n \n-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL\n-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL\n-#define MISCS_REG_RESET_PL_HV_2_K2_E5 0x009150UL\n+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL\n+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL\n #define CNIG_REG_NW_PORT_MODE_BB 0x218200UL\n #define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL\n #define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL\n #define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL\n-#define NWM_REG_MAC0_K2_E5 0x800400UL\n-#define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL\n-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0\n-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1\n-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3\n-#define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL\n-#define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0\n-#define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL\n-#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0\n-#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL\n-#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0\n-#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL\n-#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0\n-#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL\n-#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16\n-#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0\n-#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL\n+#define NWM_REG_MAC0_K2 0x800400UL\n+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT 0\n+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT 1\n+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT 3\n+#define ETH_MAC_REG_XIF_MODE_K2 0x000080UL\n+ #define ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT 0\n+#define ETH_MAC_REG_FRM_LENGTH_K2 0x000014UL\n+ #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT 0\n+#define ETH_MAC_REG_TX_IPG_LENGTH_K2 0x000044UL\n+ #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT 0\n+#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2 0x00001cUL\n+ #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT 0\n+#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2 0x000020UL\n+ #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT 16\n+ #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT 0\n+ #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2 (0x1 << 6)\n+ #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_SHIFT 6\n+#define ETH_MAC_REG_COMMAND_CONFIG_K2 0x000008UL\n #define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL\n #define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL\n #define XMAC_REG_MODE_BB 0x210008UL\n@@ -1192,17 +1192,12 @@\n #define XMAC_REG_RX_CTRL_BB 0x210030UL\n #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12)\n \n-#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL\n-#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL\n-#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5 0x2aafa0UL\n-#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5 0x2aafa4UL\n #define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL\n #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL\n #define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL\n #define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL\n #define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL\n-#define PCIE_REG_PRTY_MASK_K2_E5 0x0547b4UL\n-#define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL\n+#define PCIE_REG_PRTY_MASK_K2 0x0547b4UL\n \n #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL\n \n@@ -1233,10 +1228,10 @@\n #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL\n #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL\n #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL\n-#define DORQ_REG_PF_PCP_BB_K2 0x1008c4UL\n-#define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL\n+#define DORQ_REG_PF_PCP 0x1008c4UL\n+#define DORQ_REG_PF_EXT_VID 0x1008c8UL\n #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL\n #define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL\n #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL\n #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL\n-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL\n+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL 0x501b40UL\ndiff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex fffccf070..d6382b62c 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -569,12 +569,12 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,\n \t\t uint16_t sb_id)\n {\n \tstruct ecore_dev *edev = QEDE_INIT_EDEV(qdev);\n-\tstruct status_block_e4 *sb_virt;\n+\tstruct status_block *sb_virt;\n \tdma_addr_t sb_phys;\n \tint rc;\n \n \tsb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,\n-\t\t\t\t\t sizeof(struct status_block_e4));\n+\t\t\t\t\t sizeof(struct status_block));\n \tif (!sb_virt) {\n \t\tDP_ERR(edev, \"Status block allocation failed\\n\");\n \t\treturn -ENOMEM;\n@@ -584,7 +584,7 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,\n \tif (rc) {\n \t\tDP_ERR(edev, \"Status block initialization failed\\n\");\n \t\tOSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,\n-\t\t\t\t sizeof(struct status_block_e4));\n+\t\t\t\t sizeof(struct status_block));\n \t\treturn rc;\n \t}\n \n@@ -683,7 +683,7 @@ void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)\n \t\tif (fp->sb_info) {\n \t\t\tOSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,\n \t\t\t\tfp->sb_info->sb_phys,\n-\t\t\t\tsizeof(struct status_block_e4));\n+\t\t\t\tsizeof(struct status_block));\n \t\t\trte_free(fp->sb_info);\n \t\t\tfp->sb_info = NULL;\n \t\t}\n", "prefixes": [ "v2", "4/9" ] }