Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/59956/?format=api
{ "id": 59956, "url": "https://patches.dpdk.org/api/patches/59956/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190927062533.19005-2-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190927062533.19005-2-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190927062533.19005-2-rnagadheeraj@marvell.com", "date": "2019-09-27T06:26:25", "name": "[v6,1/8] crypto/nitrox: add Nitrox PMD library", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "3e358d43eb7d0798eb57bfa7647b8bf029f9add9", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190927062533.19005-2-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6560, "url": "https://patches.dpdk.org/api/series/6560/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6560", "date": "2019-09-27T06:26:22", "name": "add Nitrox crypto device support", "version": 6, "mbox": "https://patches.dpdk.org/series/6560/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59956/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59956/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C20BA2C37;\n\tFri, 27 Sep 2019 08:26:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CAB611E34\n\tfor <dev@dpdk.org>; Fri, 27 Sep 2019 08:26:29 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx8R5nZuG002309; Thu, 26 Sep 2019 23:26:29 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2v8vf2468a-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 26 Sep 2019 23:26:28 -0700", "from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 26 Sep 2019 23:26:27 -0700", "from NAM05-DM3-obe.outbound.protection.outlook.com (104.47.49.58)\n\tby SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1367.3 via Frontend Transport; Thu, 26 Sep 2019 23:26:26 -0700", "from BYAPR18MB2792.namprd18.prod.outlook.com (20.179.56.216) by\n\tBYAPR18MB2984.namprd18.prod.outlook.com (20.179.59.97) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.2284.19; Fri, 27 Sep 2019 06:26:25 +0000", "from BYAPR18MB2792.namprd18.prod.outlook.com\n\t([fe80::7112:68c6:eb44:e9aa]) by\n\tBYAPR18MB2792.namprd18.prod.outlook.com\n\t([fe80::7112:68c6:eb44:e9aa%3]) with mapi id 15.20.2284.028;\n\tFri, 27 Sep 2019 06:26:25 +0000" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : references : in-reply-to : content-type\n\t: content-transfer-encoding : mime-version; s=pfpt0818;\n\tbh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=;\n\tb=XZItLDgpSdIUvBxTxl4Rem/6n0F7lUd3tf4kDPatDNc3onEGnSAxKkFNCaYgDAlUXX1H\n\tZxO4IQgMIEjUgqk12Eogz96OXMoUwDQv6Qo5bOyD0kiAGe9qmK0Vb8wpPVhRbesRS7EL\n\tiBd6gSfF7qAJuZ0qhGFEYwjUzCAytF1SKJ+/F/FH8dbCRUdjixZSJxTAUvqyLyopkn6F\n\tqPnXmQlcwJk68CrJhBjc9urhGdV4Zf+Uf5b1SSgxrgnizDLXjXipmB7a1eW3S91fno8Z\n\tG2UJ6jJcd0XR23pbfinVeH1sF+KCSdENxFnaUdNdIQDJXfKowHcCbEXPooy+UXPtPwXX\n\t6Q== ", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=;\n\tb=Is7ZxuPXQzoF+CFHffG3HhZREHiDWlgf7Gnji8D7ZI1y7NO3ju5Z5nbr9YFiXzt1HWFk3h1KK5Q991UPgsEn04RygA9pHDyhZZAaI0kRNYcoZ8cB1fv2nu906CNdqSeMSAEtOqQ4rl5qXHQmXTopuFkS3hE7Oq7t07Lw8Z/0tTo=" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n\tb=cPFm1DsfaLDW0sI/QwELiPbn1Ow3GipbMVcAgM3yKZ8ybK+m9rpDziqcX4CvLoX8XLFuy59RY/+pHRqX/4H+fo+PwmDubkA585RyiHaYlaAc6pm5RPWeji20MJHYgS6n9IdRKA7m21bN30YhN6Xb/sdnrm9zcv1Er+yY8CQaAcU0xMZAMyFI+7O+QrHbA3aRxkKlX01r4dMXljUyvaJ9LOOQDAdyys5e+VWbPw3nCMhGcBEouuqI9YE61YZRrFMhXFr0s4xHkqfb4qgBDbgSIGT8hB1x9VNDn0CuXnlqbesdY+3ba/Z8/VEfijmb6OBm5Mlm6Mz5MqVrDH4rKGFaRQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n\ts=arcselector9901;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=gmoJND0c0j3ShNiWvxYSRQ+WHQKtBF9lZ2hux8cfJYk=;\n\tb=GJJy7zJvWimMxiwVJc4HqrxYlGtMOoi54YrKYRaUaygKlpNf5rMisi08NoQ+rgzzuaHuCbRbCLSpm3nmwREOR1O5z9HuJ0ClhpbUIGRtgg36I/BxP2nkoZlpWcXHGRHWLaj3rEs22bGk1hDZUs9ofkz92sFnG/lDeWr+JkR4S32oW0uoOGJpqfGvm5BT6+LZ5V0vllLwZYlyn7ZpCb1NSrBOuv8nqKzD33R04grvjvwbXhIPpGb/g7+KJ6EPp9YsRTCRUNOk3z5QZoO1R1Zn8vbAFROVeNlhqQwobVLLJwPl4ImRX16HgoSJiFeVPKUwf9Jm+xmxXsj+7qIoWhnkdw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n\tsmtp.mailfrom=marvell.com;\n\tdmarc=pass action=none header.from=marvell.com; \n\tdkim=pass header.d=marvell.com; arc=none", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "\"akhil.goyal@nxp.com\" <akhil.goyal@nxp.com>,\n\t\"pablo.de.lara.guarch@intel.com\" <pablo.de.lara.guarch@intel.com>", "CC": "Srikanth Jampala <jsrikanth@marvell.com>, \"dev@dpdk.org\" <dev@dpdk.org>, \n\tNagadheeraj Rottela <rnagadheeraj@marvell.com>", "Thread-Topic": "[PATCH v6 1/8] crypto/nitrox: add Nitrox PMD library", "Thread-Index": "AQHVdPx91b4XK9MXGUmk2oy8+ZyGDQ==", "Date": "Fri, 27 Sep 2019 06:26:25 +0000", "Message-ID": "<20190927062533.19005-2-rnagadheeraj@marvell.com>", "References": "<20190716091016.4788-1-rnagadheeraj@marvell.com>\n\t<20190927062533.19005-1-rnagadheeraj@marvell.com>", "In-Reply-To": "<20190927062533.19005-1-rnagadheeraj@marvell.com>", "Accept-Language": "en-IN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "PN1PR0101CA0025.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:c::11) To BYAPR18MB2792.namprd18.prod.outlook.com\n\t(2603:10b6:a03:105::24)", "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.13.6", "x-originating-ip": "[115.113.156.2]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "21f0c945-f84b-48f9-a058-08d743139f69", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);\n\tSRVR:BYAPR18MB2984; ", "x-ms-traffictypediagnostic": "BYAPR18MB2984:", "x-ms-exchange-purlcount": "2", "x-ms-exchange-transport-forked": "True", "x-microsoft-antispam-prvs": "<BYAPR18MB2984A6F257E9610DF71F7909D6810@BYAPR18MB2984.namprd18.prod.outlook.com>", "x-ms-oob-tlc-oobclassifiers": "OLM:2733;", "x-forefront-prvs": "0173C6D4D5", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(4636009)(396003)(376002)(136003)(366004)(39860400002)(346002)(189003)(199004)(6436002)(26005)(30864003)(2906002)(107886003)(14444005)(102836004)(3846002)(1076003)(66066001)(14454004)(6486002)(55236004)(36756003)(305945005)(256004)(478600001)(186003)(6506007)(66946007)(110136005)(76176011)(8936002)(8676002)(54906003)(6116002)(71190400001)(5660300002)(71200400001)(52116002)(386003)(66556008)(66446008)(446003)(11346002)(2501003)(86362001)(81166006)(64756008)(966005)(316002)(4326008)(66476007)(25786009)(6306002)(50226002)(99286004)(2616005)(476003)(7736002)(486006)(81156014)(6512007);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2984;\n\tH:BYAPR18MB2792.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: marvell.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "QXbSj2UR3eZrPsd9/orle4PJu/TxcQWcjU2CrRG1i2ifOmu3ysxYrkK7hf6CX98ezg3yPbuLDnLq0FPKJEH3X/bpii29yIxiDhq5ltC9fcpXx6o7flumA8sXtYxbxWcnpa/YBqOVWdrfNR6gz/zae1cDIpz0kKcn7es0oNW5yOuKpUWYxu9YHkZMMuqKxMANBG3luTbHwGD/KUj++4L1uvRRYAb2VDNxAGWCRMg1s4lMXWiycjGFCwllGyWHB+5crP06jLnwXuDyWkkdzaDIOgZRmxaJ/QPhij6n3rBoRKMBwrEoJLpxqqqIy8Ko11WC9a3CXCA2Mr8ryOOQcV7GAiHai9me7maNHfyXF7XBB1+EuyW3A9H5pdVZWBRlfK0x5yM9xJpR+sHsXvAjGFWXKVeUMeAdkTLFqc15Tklmw1NKZK/orN2tK7Bxgr3NmsdCCqm4SniFt8+plgANNa3T6w==", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "21f0c945-f84b-48f9-a058-08d743139f69", "X-MS-Exchange-CrossTenant-originalarrivaltime": "27 Sep 2019 06:26:25.6102\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "jDtCCeheRA0ex4EkbWfzzD8UOmu2TQwuoF1iiPwu+vY917nXWA6BwDxC7ceXQlewldDwBE7QT8/C8VslL5Ev9pTy7+UKFrvsXnm5doApaUs=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR18MB2984", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-09-27_04:2019-09-25,2019-09-27 signatures=0", "Subject": "[dpdk-dev] [PATCH v6 1/8] crypto/nitrox: add Nitrox PMD library", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add bare minimum Nitrox PMD library which handles pci probe, remove and\nhardware initialization. Add logs, documentation and update maintainers\nfile.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n MAINTAINERS | 7 ++\n config/common_base | 5 +\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/nitrox.rst | 30 ++++++\n drivers/crypto/Makefile | 1 +\n drivers/crypto/meson.build | 4 +-\n drivers/crypto/nitrox/Makefile | 30 ++++++\n drivers/crypto/nitrox/meson.build | 15 +++\n drivers/crypto/nitrox/nitrox_csr.h | 28 ++++++\n drivers/crypto/nitrox/nitrox_device.c | 111 +++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_device.h | 18 ++++\n drivers/crypto/nitrox/nitrox_hal.c | 85 +++++++++++++++++\n drivers/crypto/nitrox/nitrox_hal.h | 37 ++++++++\n drivers/crypto/nitrox/nitrox_logs.c | 14 +++\n drivers/crypto/nitrox/nitrox_logs.h | 15 +++\n drivers/crypto/nitrox/rte_pmd_nitrox_version.map | 3 +\n mk/rte.app.mk | 1 +\n 17 files changed, 403 insertions(+), 2 deletions(-)\n create mode 100644 doc/guides/cryptodevs/nitrox.rst\n create mode 100644 drivers/crypto/nitrox/Makefile\n create mode 100644 drivers/crypto/nitrox/meson.build\n create mode 100644 drivers/crypto/nitrox/nitrox_csr.h\n create mode 100644 drivers/crypto/nitrox/nitrox_device.c\n create mode 100644 drivers/crypto/nitrox/nitrox_device.h\n create mode 100644 drivers/crypto/nitrox/nitrox_hal.c\n create mode 100644 drivers/crypto/nitrox/nitrox_hal.h\n create mode 100644 drivers/crypto/nitrox/nitrox_logs.c\n create mode 100644 drivers/crypto/nitrox/nitrox_logs.h\n create mode 100644 drivers/crypto/nitrox/rte_pmd_nitrox_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex b3d9aaddd..c881fd023 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -963,6 +963,13 @@ F: drivers/crypto/mvsam/\n F: doc/guides/cryptodevs/mvsam.rst\n F: doc/guides/cryptodevs/features/mvsam.ini\n \n+Nitrox\n+M: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n+M: Srikanth Jampala <jsrikanth@marvell.com>\n+F: drivers/crypto/nitrox/\n+F: doc/guides/cryptodevs/nitrox.rst\n+F: doc/guides/cryptodevs/features/nitrox.ini\n+\n Null Crypto\n M: Declan Doherty <declan.doherty@intel.com>\n F: drivers/crypto/null/\ndiff --git a/config/common_base b/config/common_base\nindex 8ef75c203..92ecb4a68 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -664,6 +664,11 @@ CONFIG_RTE_LIBRTE_PMD_CCP=n\n CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n\n \n #\n+# Compile PMD for NITROX crypto device\n+#\n+CONFIG_RTE_LIBRTE_PMD_NITROX=y\n+\n+#\n # Compile generic security library\n #\n CONFIG_RTE_LIBRTE_SECURITY=y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 83610e64f..d1e0d3203 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -21,6 +21,7 @@ Crypto Device Drivers\n octeontx\n openssl\n mvsam\n+ nitrox\n null\n scheduler\n snow3g\ndiff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst\nnew file mode 100644\nindex 000000000..cb7f92755\n--- /dev/null\n+++ b/doc/guides/cryptodevs/nitrox.rst\n@@ -0,0 +1,30 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(C) 2019 Marvell International Ltd.\n+\n+Marvell NITROX Crypto Poll Mode Driver\n+======================================\n+\n+The Nitrox crypto poll mode driver provides support for offloading\n+cryptographic operations to the NITROX V security processor. Detailed\n+information about the NITROX V security processor can be obtained here:\n+\n+* https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/\n+\n+Installation\n+------------\n+\n+For compiling the Nitrox crypto PMD, please check if the\n+CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file.\n+\n+* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y``\n+\n+Initialization\n+--------------\n+\n+Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the\n+platform. Nitrox PF driver is required to create VF devices which will\n+be used by the PMD. Each VF device can enable one cryptodev PMD.\n+\n+Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK\n+and it's installation instructions can be obtained from:\n+`Marvell Technical Documentation Portal <https://support.cavium.com/>`_.\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nindex 009f8443d..7129bcfc9 100644\n--- a/drivers/crypto/Makefile\n+++ b/drivers/crypto/Makefile\n@@ -25,5 +25,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr\n endif # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC\n endif # CONFIG_RTE_LIBRTE_SECURITY\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex 83e78860e..1a358ff8b 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -2,8 +2,8 @@\n # Copyright(c) 2017 Intel Corporation\n \n drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',\n-\t'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler',\n-\t'snow3g', 'virtio', 'zuc']\n+\t'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',\n+\t'scheduler', 'snow3g', 'virtio', 'zuc']\n \n std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile\nnew file mode 100644\nindex 000000000..7681a6603\n--- /dev/null\n+++ b/drivers/crypto/nitrox/Makefile\n@@ -0,0 +1,30 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_nitrox.a\n+\n+# build flags\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+\n+# library version\n+LIBABIVER := 1\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_nitrox_version.map\n+\n+# external library dependencies\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+LDLIBS += -lrte_cryptodev\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build\nnew file mode 100644\nindex 000000000..ad81f8cd8\n--- /dev/null\n+++ b/drivers/crypto/nitrox/meson.build\n@@ -0,0 +1,15 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+\n+if not is_linux\n+\tbuild = false\n+\treason = 'only supported on Linux'\n+endif\n+\n+deps += ['bus_pci']\n+allow_experimental_apis = true\n+sources = files(\n+\t\t'nitrox_device.c',\n+\t\t'nitrox_hal.c',\n+\t\t'nitrox_logs.c',\n+\t\t)\ndiff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h\nnew file mode 100644\nindex 000000000..879104515\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_csr.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_CSR_H_\n+#define _NITROX_CSR_H_\n+\n+#include <rte_common.h>\n+#include <rte_io.h>\n+\n+#define CSR_DELAY\t30\n+\n+/* AQM Virtual Function Registers */\n+#define AQMQ_QSZX(_i)\t\t\t(0x20008 + ((_i)*0x40000))\n+\n+static inline uint64_t\n+nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)\n+{\n+\treturn rte_read64(bar_addr + offset);\n+}\n+\n+static inline void\n+nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value)\n+{\n+\trte_write64(value, (bar_addr + offset));\n+}\n+\n+#endif /* _NITROX_CSR_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_device.c b/drivers/crypto/nitrox/nitrox_device.c\nnew file mode 100644\nindex 000000000..a73528211\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_device.c\n@@ -0,0 +1,111 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_malloc.h>\n+\n+#include \"nitrox_device.h\"\n+#include \"nitrox_hal.h\"\n+\n+#define PCI_VENDOR_ID_CAVIUM\t0x177d\n+#define NITROX_V_PCI_VF_DEV_ID\t0x13\n+\n+TAILQ_HEAD(ndev_list, nitrox_device);\n+static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list);\n+\n+static struct nitrox_device *\n+ndev_allocate(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tndev = rte_zmalloc_socket(\"nitrox device\", sizeof(*ndev),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t pdev->device.numa_node);\n+\tif (!ndev)\n+\t\treturn NULL;\n+\n+\tTAILQ_INSERT_TAIL(&ndev_list, ndev, next);\n+\treturn ndev;\n+}\n+\n+static void\n+ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev)\n+{\n+\tenum nitrox_vf_mode vf_mode;\n+\n+\tndev->pdev = pdev;\n+\tndev->bar_addr = pdev->mem_resource[0].addr;\n+\tvf_mode = vf_get_vf_config_mode(ndev->bar_addr);\n+\tndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode);\n+}\n+\n+static struct nitrox_device *\n+find_ndev(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tTAILQ_FOREACH(ndev, &ndev_list, next)\n+\t\tif (ndev->pdev == pdev)\n+\t\t\treturn ndev;\n+\n+\treturn NULL;\n+}\n+\n+static void\n+ndev_release(struct nitrox_device *ndev)\n+{\n+\tif (!ndev)\n+\t\treturn;\n+\n+\tTAILQ_REMOVE(&ndev_list, ndev, next);\n+\trte_free(ndev);\n+}\n+\n+static int\n+nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\tstruct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\t/* Nitrox CSR space */\n+\tif (!pdev->mem_resource[0].addr)\n+\t\treturn -EINVAL;\n+\n+\tndev = ndev_allocate(pdev);\n+\tif (!ndev)\n+\t\treturn -ENOMEM;\n+\n+\tndev_init(ndev, pdev);\n+\treturn 0;\n+}\n+\n+static int\n+nitrox_pci_remove(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tndev = find_ndev(pdev);\n+\tif (!ndev)\n+\t\treturn -ENODEV;\n+\n+\tndev_release(ndev);\n+\treturn 0;\n+}\n+\n+static struct rte_pci_id pci_id_nitrox_map[] = {\n+\t{\n+\t\t/* Nitrox 5 VF */\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, NITROX_V_PCI_VF_DEV_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+static struct rte_pci_driver nitrox_pmd = {\n+\t.id_table = pci_id_nitrox_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = nitrox_pci_probe,\n+\t.remove = nitrox_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map);\ndiff --git a/drivers/crypto/nitrox/nitrox_device.h b/drivers/crypto/nitrox/nitrox_device.h\nnew file mode 100644\nindex 000000000..0d0167de2\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_device.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_DEVICE_H_\n+#define _NITROX_DEVICE_H_\n+\n+#include <rte_bus_pci.h>\n+#include <rte_cryptodev.h>\n+\n+struct nitrox_device {\n+\tTAILQ_ENTRY(nitrox_device) next;\n+\tstruct rte_pci_device *pdev;\n+\tuint8_t *bar_addr;\n+\tuint16_t nr_queues;\n+};\n+\n+#endif /* _NITROX_DEVICE_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c\nnew file mode 100644\nindex 000000000..ed1882016\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_hal.c\n@@ -0,0 +1,85 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_memory.h>\n+#include <rte_byteorder.h>\n+\n+#include \"nitrox_hal.h\"\n+#include \"nitrox_csr.h\"\n+\n+#define MAX_VF_QUEUES\t8\n+#define MAX_PF_QUEUES\t64\n+\n+int\n+vf_get_vf_config_mode(uint8_t *bar_addr)\n+{\n+\tunion aqmq_qsz aqmq_qsz;\n+\tuint64_t reg_addr;\n+\tint q, vf_mode;\n+\n+\taqmq_qsz.u64 = 0;\n+\taqmq_qsz.s.host_queue_size = 0xDEADBEEF;\n+\treg_addr = AQMQ_QSZX(0);\n+\tnitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\taqmq_qsz.u64 = 0;\n+\tfor (q = 1; q < MAX_VF_QUEUES; q++) {\n+\t\treg_addr = AQMQ_QSZX(q);\n+\t\taqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t\tif (aqmq_qsz.s.host_queue_size == 0xDEADBEEF)\n+\t\t\tbreak;\n+\t}\n+\n+\tswitch (q) {\n+\tcase 1:\n+\t\tvf_mode = NITROX_MODE_VF128;\n+\t\tbreak;\n+\tcase 2:\n+\t\tvf_mode = NITROX_MODE_VF64;\n+\t\tbreak;\n+\tcase 4:\n+\t\tvf_mode = NITROX_MODE_VF32;\n+\t\tbreak;\n+\tcase 8:\n+\t\tvf_mode = NITROX_MODE_VF16;\n+\t\tbreak;\n+\tdefault:\n+\t\tvf_mode = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn vf_mode;\n+}\n+\n+int\n+vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode)\n+{\n+\tint nr_queues;\n+\n+\tswitch (vf_mode) {\n+\tcase NITROX_MODE_PF:\n+\t\tnr_queues = MAX_PF_QUEUES;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF16:\n+\t\tnr_queues = 8;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF32:\n+\t\tnr_queues = 4;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF64:\n+\t\tnr_queues = 2;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF128:\n+\t\tnr_queues = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tnr_queues = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn nr_queues;\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h\nnew file mode 100644\nindex 000000000..6184211a5\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_hal.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_HAL_H_\n+#define _NITROX_HAL_H_\n+\n+#include <rte_cycles.h>\n+#include <rte_byteorder.h>\n+\n+#include \"nitrox_csr.h\"\n+\n+union aqmq_qsz {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz : 32;\n+\t\tuint64_t host_queue_size : 32;\n+#else\n+\t\tuint64_t host_queue_size : 32;\n+\t\tuint64_t raz : 32;\n+#endif\n+\t} s;\n+};\n+\n+enum nitrox_vf_mode {\n+\tNITROX_MODE_PF = 0x0,\n+\tNITROX_MODE_VF16 = 0x1,\n+\tNITROX_MODE_VF32 = 0x2,\n+\tNITROX_MODE_VF64 = 0x3,\n+\tNITROX_MODE_VF128 = 0x4,\n+};\n+\n+int vf_get_vf_config_mode(uint8_t *bar_addr);\n+int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);\n+\n+#endif /* _NITROX_HAL_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_logs.c b/drivers/crypto/nitrox/nitrox_logs.c\nnew file mode 100644\nindex 000000000..007056cb4\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_logs.c\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_log.h>\n+\n+int nitrox_logtype;\n+\n+RTE_INIT(nitrox_init_log)\n+{\n+\tnitrox_logtype = rte_log_register(\"pmd.crypto.nitrox\");\n+\tif (nitrox_logtype >= 0)\n+\t\trte_log_set_level(nitrox_logtype, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_logs.h b/drivers/crypto/nitrox/nitrox_logs.h\nnew file mode 100644\nindex 000000000..50e52f396\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_logs.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_LOGS_H_\n+#define _NITROX_LOGS_H_\n+\n+#define LOG_PREFIX \"NITROX: \"\n+#define NITROX_LOG(level, fmt, args...)\t\t\t\t\t\\\n+\trte_log(RTE_LOG_ ## level, nitrox_logtype,\t\t\t\\\n+\t\tLOG_PREFIX \"%s:%d \" fmt, __func__, __LINE__, ## args)\n+\n+extern int nitrox_logtype;\n+\n+#endif /* _NITROX_LOGS_H_ */\ndiff --git a/drivers/crypto/nitrox/rte_pmd_nitrox_version.map b/drivers/crypto/nitrox/rte_pmd_nitrox_version.map\nnew file mode 100644\nindex 000000000..0a539ae48\n--- /dev/null\n+++ b/drivers/crypto/nitrox/rte_pmd_nitrox_version.map\n@@ -0,0 +1,3 @@\n+DPDK_19.08 {\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex ba5c39e01..fb496692b 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -279,6 +279,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += -lrte_pmd_caam_jr\n endif # CONFIG_RTE_LIBRTE_DPAA_BUS\n endif # CONFIG_RTE_LIBRTE_SECURITY\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += -lrte_pmd_nitrox\n endif # CONFIG_RTE_LIBRTE_CRYPTODEV\n \n ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)\n", "prefixes": [ "v6", "1/8" ] }